CN107133011B - Multichannel data storage method of oscillograph - Google Patents
Multichannel data storage method of oscillograph Download PDFInfo
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- CN107133011B CN107133011B CN201710278134.3A CN201710278134A CN107133011B CN 107133011 B CN107133011 B CN 107133011B CN 201710278134 A CN201710278134 A CN 201710278134A CN 107133011 B CN107133011 B CN 107133011B
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Abstract
The invention discloses a multi-channel data storage method of an oscillograph, a data selection module selects an input signal after analog-to-digital conversion, then a data bit width conversion module converts data bit widths of different channel numbers into proper output bit widths, the proper output bit widths are input into a large-capacity dynamic memory after passing through a front-end data cache module, under the reading instruction of the memory controller, data is read out of the large-capacity dynamic memory and input into the storage data recovery FIFO array, the storage data recovery FIFO array converts the output bit width of the large-capacity dynamic memory into the data bit width corresponding to the multi-channel data stored in the large-capacity dynamic memory, after the data is processed by the storage data recovery FIFO array, and the data is sent to a snapshot module for snapshot, the sampling rate of the data is reduced, and then the data is sent to a rear-end data cache module for cache and finally sent to an upper computer.
Description
Technical Field
The invention belongs to the technical field of data storage of oscillographic recorders, and particularly relates to a multi-channel data storage method of an oscillographic recorder.
Background
The oscillograph recorder is used as a powerful portable data acquisition recorder, can capture and analyze transient time, displays a trend waveform for 200 days, and is connected with a plugging module. The oscillograph recorder can flexibly combine the measurement of electric signals and physical signals, and is widely applied to various industries, so that the oscillograph recorder is required to have multiple functions to meet the requirements of various test occasions. In the oscillograph recorder in the current market, the functions of real-time power operation, real-time recording, double capture and deep storage are necessary functions of the oscillograph recorder, and the acquired data need to be stored to realize the functions; meanwhile, in the face of different measured parameters, the storage length required by oscillography recording can be dynamically configured so as to meet the test requirements of various industries. Researches show that the storage in the domestic existing multi-channel acquisition system mainly has the following defects,
(1) hardware storage resource waste, for example, if a 4-channel acquisition system uses a memory with a storage length of L, the storage length of each channel is
When the user chooses to observe single-channel data, the memory stores
The storage resource storage user does not care about the data, resulting in the waste of storage resources.
(2) After the design of most multi-channel acquisition systems is finished, the number of acquisition channels cannot be changed, so that when a user wants to observe additional acquired data, the user only can compare the acquired data by using a plurality of acquisition systems, but the method is inconvenient.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a multichannel data storage method of an oscillograph, which realizes the storage of multichannel data by selecting and converting bit widths of data of a plurality of channels.
In order to achieve the above object, the present invention provides a multi-channel data storage method for an oscillograph, which is characterized by comprising the following steps:
(1) acquiring the plugging and unplugging states of the board cards by a user to obtain data streams of N channels;
(2) setting corresponding parameters of a data selection module, a data bit width conversion module and a stored data recovery FIFO array through a human-computer interaction interface of the oscillograph recorder;
(3) inputting the data stream of the N channels into a data selection module, and randomly selecting 2 from the data selection modulet(2tN, t is equal to or less than 0,1,2 …), and sending the data as an output data stream to the data bit width conversion module;
(4) the data bit width conversion module receives the output data stream according to the clock period, and the bit width of the effective output data stream received in each clock period is 2tm bits, then the bit width is 2 through the data bit width conversion moduletThe effective output data stream of M bits is converted into data with the bit width of M/2 bits, M is the data bit width of each channel, and M is the data bit width of the large-capacity memory;
(5) when the effective signal of the output data stream is set to be 1, the write enable of the front-end data cache module is effective, and data with the bit width of M/2bit is written into the front-end data cache module;
(6) when the memory controller receives a writing large-capacity dynamic storage instruction of a user, under the control of a writing enabling signal of the memory controller, writing data in the front-end data cache module into a large-capacity dynamic memory;
(7) when the memory controller receives a large-capacity dynamic storage reading instruction of a user, under the control of a read enable signal of the memory controller, reading data in the large-capacity dynamic storage and sending the data to the storage data recovery FIFO array;
(8) the storage data recovery FIFO array receives the read data of the large-capacity dynamic memory according to the clock period and converts the data received in each clock period into the data with the bit width of 2tThe m-bit data is sent to the snapshot module;
(9) the snapshot module performs snapshot on the received data, reduces the sampling rate of the data, and then sends the data to the back-end data cache, and the back-end data cache adopts a compatible unified control method to receive the data 2tAnd caching the data of each channel, and when the rear-end data cache is full, reading the data from the rear-end data cache by the upper computer and displaying the data in a cache region of the upper computer.
The invention aims to realize the following steps:
the invention relates to a multi-channel data storage method of an oscillograph, wherein a data selection module selects an input signal after analog-to-digital conversion, then a data bit width conversion module converts data bit widths of different channel numbers into proper output bit widths, the proper output bit widths are input into a large-capacity dynamic memory after passing through a front-end data cache module, under the reading instruction of the memory controller, data is read out of the large-capacity dynamic memory and input into the storage data recovery FIFO array, the storage data recovery FIFO array converts the output bit width of the large-capacity dynamic memory into the data bit width corresponding to the multi-channel data stored in the large-capacity dynamic memory, after the data is processed by the storage data recovery FIFO array, and the data is sent to a snapshot module for snapshot, the sampling rate of the data is reduced, and then the data is sent to a rear-end data cache module for cache and finally sent to an upper computer.
Meanwhile, the multichannel data storage method of the oscillograph also has the following beneficial effects:
(1) the selection of any channel data in the input data stream is realized according to the instruction of the user, and the data with different channel numbers are flexibly stored, so that the data in the memory are all the data selected by the user and have no redundant data.
(2) The invention takes the problem that the FIFO consumes the internal resources of the FPGA into consideration, and optimally selects the input and output bit width of the FIFO when the FIFO is instantiated. The data bit width output from the large-capacity dynamic memory is converted into various data bit widths required by a user in a multi-stage FIFO cascading mode, and compared with a mode of respectively converting, resources are saved.
(3) The number of the acquisition channels is flexibly configured, and the mode that the number of the acquisition channels is fixed on the traditional oscilloscope is broken through.
Drawings
FIG. 1 is a functional block diagram of a multi-channel data storage device of an oscillograph;
FIG. 2 is a flow chart of a multi-channel data storage method of an oscillograph according to the present invention;
FIG. 3 is a schematic diagram of a channel and corresponding data selection in a data selection module;
FIG. 4 is a schematic diagram of bit width conversion;
FIG. 5 is a schematic diagram illustrating bit width conversion of read data of different channels by the FIFO array for storing data recovery;
FIG. 6 is a schematic diagram of the snapshot module and the back-end data cache.
Detailed Description
The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.
Examples
FIG. 1 is a schematic block diagram of a multi-channel data storage device for an oscillograph.
In this embodiment, as shown in fig. 1, the multi-channel data storage device of the oscillograph includes a data selection module, a data bit width conversion module, a front-end data buffer module, a memory controller, a stored data recovery FIFO array, a snapshot module, a back-end data buffer module, and a large-capacity dynamic memory. The system comprises a data selection module, a data bit width conversion module, a front-end data cache module, a memory controller and a stored data recovery FIFO array, wherein the snapshot module and the back-end data cache module are all realized in an FPGA.
FIG. 2 is a flow chart of a multi-channel data storage method of the oscillograph of the present invention.
The following describes the multichannel data storage device of the oscillograph in detail with reference to fig. 1.
As shown in FIG. 2, the multi-channel data storage method of the oscillograph of the present invention comprises the following steps:
s1, the user acquires data streams of N channels by configuring the plugging and unplugging state of the acquisition board card;
in this embodiment, the number of the configured acquisition boards of the human-computer interaction interface is 8, each board has 16 channels, and the data bit width of each channel is 16 bits.
S2, setting corresponding parameters of a data selection module, a data bit width conversion module and a stored data recovery FIFO array through a human-computer interaction interface of the oscillograph;
in the bookIn an embodiment, default setting data selection module selects 2tIndividual channel data; setting bit width conversion module pair 2tCarrying out bit width conversion on the data of each channel, and setting the storage depth of the data of each channel as W2tSince the number of channels selectable by the user is variable, the storage depth of data per channel is also variable for a large-capacity dynamic memory with a constant size W, but the storage depth W of data per channel is also variable2tAnd the number of selected channels 2tThe product of (A) and (B) is less than or equal to the capacity W of the large-capacity dynamic memory; setting storage data recovery FIFO array to convert bit width of output data from large-capacity dynamic memory into 2tBit width of data required for each channel, wherein 2t≤N，t＝0,1,2…。
S3, inputting the data flow of N channels into the data selection module, wherein the data selection module randomly selects 2t(2tN, t is equal to or less than 0,1,2 …), and sending the data as an output data stream to the data bit width conversion module;
in this embodiment, the data selection module takes 128 channels of 100MHz data streams data as the acquired mass data stream as input, and the user can obtain any 2tA channel (2)t≦ 128) data stream, as shown in FIG. 3, below we take 20Road, 21Road, 22Road, 23Road, 24The lane is illustrated with a data bit width of 16 bits per lane.
When selecting 20When storing data of each channel, 2 can be arbitrarily selected in 128 data streams0Way put it in [255:240 ] of the output data stream data _ a]Bits, [239:0 ] of the output data stream data _ a]Setting the bit width to 0, and sending the bit width to a data bit width conversion module;
when selecting 21When storing data of each channel, 2 can be arbitrarily selected in 128 data streams1Way put it in [255:224 ] of the output data stream data _ a]Bits, [223:0 ] of the output data stream data _ a]Setting the bit width to 0, and sending the bit width to a data bit width conversion module;
when selecting 22When storing data of each channel, 2 can be arbitrarily selected in 128 data streams2Way put it in 255:192 of the output data stream data _ a]Bits of [191:0 ] of the output data stream data _ a]Setting the bit width to 0, and sending the bit width to a data bit width conversion module;
when selecting 23When storing data of each channel, 2 can be arbitrarily selected in 128 data streams3Way put it in 255:128 of the output data stream data _ a]Output data stream data _ a [127:0 ]]Setting the bit width to 0, and sending the bit width to a data bit width conversion module;
when selecting 24When storing data of each channel, 2 can be arbitrarily selected in 128 data streams4Way put it in [255:0 ] of the output data stream data _ a]Then sending to a data bit width conversion module;
s4, the data bit width conversion module receives the output data stream according to the clock cycle, and the bit width of the effective output data stream received in each clock cycle is 2tmbit, then the bit width is 2 through the data bit width conversion moduletConverting the mbit effective output data stream into data with a bit width of M/2bit, wherein M is the data bit width of each channel, and M is the data bit width of a large-capacity memory;
the specific process of conversion is as follows:
when 2 is intWhen M is less than or equal to M/2, each M/2t+1M clock cycles are spliced into M/2bit, M is the data bit width of the large-capacity memory, and the data stream is effectively output every M/2t+1The M clocks are effective once, and the output data stream of the first clock period is spliced in M/2-1: M/2-2 of the output data stream of the data bit width conversion moduletm]Bit, output data stream of second clock cycle is pieced into [ M/2-2 ] of output data stream of data bit width conversion moduletm-1:M/2-2t+1m]Bit, by analogy, will M/2t+1The output data stream of M clock cycles is spliced into data with the size of M/2bit, and the data is at the M/2 tht+1M +1 clocks are effective, and the output data stream effective signal is at M/2t+1m +1 clocks are valid and set to 1;
when 2 is intAnd when M is larger than M/2, intercepting the data with the size of M/2bit from the high order of the received output data stream, wherein the effective signal of the output data stream is effective once per clock and is set to be 1.
In this example, we are paired with 2 as shown in FIG. 40Road, 21Road, 22Road, 23Road, 24And (3) carrying out bit width conversion on the data stream of the path:
when selecting 20In the channel, the bit width of the received effective output data stream is 16 bits in each clock cycle. Bit width conversion counter cnt0[2:0]Counting each clock cycle active, when cnt0When it is 0, 16-bit data is put in the output data stream data _ b [127:112 ]]When cnt is used0When the data is 1, 16 bits of data are put in the output data stream data _ b [111:96 ]]When cnt is used0For 2, 16bit data is put in the output data stream data _ b [95:90 ]]When cnt is used0When the data is 3, 16 bits of data are put in the output data stream data _ b [79:64 ]]When cnt is used0At 4, 16 bits of data are placed in the output data stream data _ b [63:48 ]]When cnt is used0At 5, 16 bits of data are placed in the output data stream data _ b [47:32 ]]When cnt is used0When the data rate is 6, 16 bits of data are put in the output data stream data _ b [31:16 ]]When cnt is used0When the data is 7, 16 bits of data are put in the output data stream data _ b [15:0 ]]. And the output data stream valid signal is at cnt0The next clock cycle of 7 is set to 1 and the other times to 0.
When selecting 21During the channel, the bit width of the received effective output data stream in each clock cycle is 32 bits. Bit width conversion counter cnt1[1:0]Counting each clock cycle active, when cnt1When the data value is 0, 32-bit data is put in the output data stream data _ b [127:96 ]]When cnt is used1When the data is 1, 32bit data is put in the output data stream data _ b [95:64 ]]When cnt is used1For a value of 2, 32 bits of data are placed in the output data stream data _ b [63:32 ]]When cnt is used1When the data is 3, 32bit data is put in the output data stream data _ b [31:0 ]]And outputting the data stream valid signal at cnt1The next clock cycle of 3 is set to 1 and the other times to 0.
When selecting 22In the channel, the bit width of the received effective output data stream is 64 bits in each clock cycle. Bit width conversion counter cnt2Counting each clock cycle active, when cnt2When 0, 64bit data is put in the output data streamdata_b[127:64]When cnt is used2When the data is 1, 64bit data is put in the output data stream data _ b [63:0 ]]And outputting the data stream valid signal at cnt2The next clock cycle of 1 is set to 1 and the other times to 0.
When selecting 23In the channel, the bit width of the received effective output data stream is 128 bits per clock cycle. Bit width conversion counter cnt3Counting every clock cycle, 128 bits of data are put in the output data stream data _ b 127:0]And the output data stream valid signal is valid once per clock and is set to 1.
When selecting 24During the channel, the bit width of the received effective output data stream in each clock cycle is 256 bits. Bit width conversion counter cnt4Counting every clock cycle when cnt4When the data is 0, high 128bit data is put in the output data stream data _ b [127:0 ]](ii) a When cnt is measured4When the data is 1, the low 128bit data is put in the output data stream data _ b [127:0 ]](ii) a And the output data stream valid signal is valid once per clock and is set to 1.
S5, when the effective signal of the output data stream is set to be 1, the write enable of the front-end data cache module is effective, and data with 128bit width under the condition that the effective signal is 1 cycle is written into the front-end data cache module;
s6, when the memory controller receives the instruction of writing the large-capacity dynamic memory from the user, under the control of the write enable signal of the memory controller, the data in the front-end data cache module is written into the large-capacity dynamic memory;
in this embodiment, the input/output bit width of the large-capacity dynamic memory is 256 bits, and the output bit width of the data bit width conversion module is 128 bits, because the resource consumption of the front-end data cache module using the input bit width of 128 bits and the output of 256 bits is half of the resource consumption of the front-end data cache module using the input bit width of 256 bits and the output of 256 bits.
For a large-capacity dynamic memory with a certain capacity, when the number of channels for storing data selected by a user is 1, all the channels stored by the large-capacity dynamic memory are data of 1 channel; when the number of channels for storing data selected by the user is 2, the maximum storage depth of the data of each channel is 1/2 of the capacity of the whole large-capacity dynamic memory; when the number of channels for storing data selected by the user is 4, the maximum storage depth of the data of each channel is 1/4 of the capacity of the whole large-capacity dynamic memory; when the number of channels for storing data selected by the user is 8, the maximum storage depth of the data of each channel is 1/8 of the capacity of the whole large-capacity dynamic memory; when the number of channels for storing data selected by the user is 16, the maximum storage depth of data of each channel is 1/16 times the capacity of the entire mass dynamic memory.
S7, when the memory controller receives the instruction of reading the large-capacity dynamic memory from the user, under the control of the read enable signal of the memory controller, the data in the large-capacity dynamic memory is read and sent to the memory data recovery FIFO array;
s8, the storage data recovery FIFO array receives the read data of the large-capacity dynamic memory according to the clock cycle and converts the data received in each clock cycle into the data with the bit width of 2tThe mbit data is sent to the snapshot module;
in this embodiment, as shown in fig. 5, the FIFO array for storing data recovery can convert the data _ d with 256 bits of bit width into data with 2 bits of bit widthtData of 16 bits (t ═ 0,1,2,3, 4).
When stored in the mass dynamic memory is 24When the data of each channel is read, the bit width of the read data is 256 bits and is exactly 2 bits4The bit width of each channel data can be directly sent to the snapshot module.
When stored in the mass dynamic memory is 23When the data of each channel is needed, the data recovery FIFO array is needed to store the data, and the data with the bit width of 256 bits output from the high-capacity dynamic memory is converted into 2 bits through the first-stage FIFO3 Data bit width 2 corresponding to channel316 bits, and then sending to the snapshot module.
When stored in the mass dynamic memory is 22When the data of the channel is needed, the data recovery FIFO array is needed to be stored to convert the data with the bit width of 256 bits output from the large-capacity dynamic memory into 22 Data bit width 2 corresponding to channel216 bits, at this timeThe output data stream of the first stage FIFO needs to be converted into 2 by converting 128bit through the second stage FIFO 216 bits, and then sending to the snapshot module.
When stored in the mass dynamic memory is 21The data of the channel needs to be stored and the data recovery FIFO array is needed to convert the data with the bit width of 256 bits output from the large-capacity dynamic memory into 2 bits1 Data bit width 2 corresponding to channel116bit, the output data flow of the second stage FIFO needs to be converted into 2 bits through the third stage FIFO 116 bits, and then sending to the snapshot module.
When stored in the mass dynamic memory is 20If the data of the channel is needed, the data recovery FIFO array is required to convert the data with the bit width of 256 bits output from the large-capacity dynamic memory into 20 Data bit width 2 corresponding to channel016 bits, i.e. 256 bits need to be converted into 2 bits through four stages of FIFO in series 316 bits, then 23Conversion of 16 bits to 2216bit, then 22Conversion of 16 bits to 2116bit, then 21Conversion of 16 bits to 2016 bits, and then sending to the snapshot module.
S9, the snapshot module performs snapshot on the received data, reduces the sampling rate of the data, and sends the data to the back-end data cache, as shown in fig. 6, the back-end data cache uses a method compatible with unified control to perform snapshot on the received data 2tThe data of each channel is sent to 256bit × 2k FIFO for caching, and when the back-end data cache is full, the upper computer reads the data from the back-end data cache and the upper computer caches.
Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.
Claims (4)
1. A multichannel data storage method of an oscillograph is characterized by comprising the following steps:
(1) acquiring the plugging and unplugging states of the board cards by a user to obtain data streams of N channels;
(2) setting corresponding parameters of a data selection module, a data bit width conversion module and a stored data recovery FIFO array through a human-computer interaction interface of the oscillograph recorder;
(3) inputting the data stream of the N channels into a data selection module, and randomly selecting 2 from the data selection moduletThe data of each channel is sent to a data bit width conversion module as an output data stream, wherein 2t≤N，t＝0,1,2,…；
(4) The data bit width conversion module receives the output data stream according to the clock period, and the bit width of the effective output data stream received in each clock period is 2tm bits, then the bit width is 2 through the data bit width conversion moduletThe effective output data stream of M bits is converted into data with the bit width of M/2 bits, M is the data bit width of each channel, and M is the data bit width of the mass memory, wherein M satisfies the condition that M is 2sm，s＝0,1,2,…；
(5) When the effective signal of the output data stream is set to be 1, the write enable of the front-end data cache module is effective, and data with the bit width of M/2bit is written into the front-end data cache module;
(6) when the memory controller receives a writing large-capacity dynamic storage instruction of a user, under the control of a writing enabling signal of the memory controller, writing data in the front-end data cache module into a large-capacity dynamic memory;
(7) when the memory controller receives a large-capacity dynamic storage reading instruction of a user, under the control of a read enable signal of the memory controller, reading data in the large-capacity dynamic storage and sending the data to the storage data recovery FIFO array;
(8) the storage data recovery FIFO array receives the read data of the large-capacity dynamic memory according to the clock period and converts the data received in each clock period into the data with the bit width of 2tThe m-bit data is sent to the snapshot module;
(9) and the snapshot module performs snapshot on the received data, reduces the sampling rate of the data, and sends the data to a back-end data cache, the back-end data cache caches the received data of the 2 channels by adopting a method compatible with unified control, and when the back-end data cache is full, the upper computer reads the data from the back-end data cache and displays the data in a cache region of the upper computer.
2. The method for storing multichannel data of the oscillograph according to claim 1, wherein in the step (2), the specific parameters set through the human-computer interface of the oscillograph include:
setup data selection Module selection 2tIndividual channel data;
setting bit width conversion module pair 2tThe bit width conversion is carried out on the data of each channel, and the storage depth of the data of each channel is set as
And the storage depth of each channel
And the number of selected channels 2tThe product of (a) is less than or equal to the capacity W of the large-capacity dynamic memory;
setting storage data recovery FIFO array to convert bit width of output data of large-capacity dynamic memory into 2tThe data bit width required for each lane.
3. The method for storing multichannel data of an oscillograph according to claim 1, wherein in step (4), the data bit width converting module converts the bit width to 2tThe specific method for converting the M-bit effective output data stream into the data with the bit width of M/2bit comprises the following steps:
when 2 is intWhen M is less than or equal to M/2, each M/2t+1M clock cycles are spliced into M/2bit, M is the data bit width of the large-capacity memory, and the data stream is effectively output every M/2t+1m clocks being active once, first clock cycleOutput data stream spliced in [ M/2-1: M/2-2 ] of output data stream of data bit width conversion moduletm]Bit, output data stream of second clock cycle is pieced into [ M/2-2 ] of output data stream of data bit width conversion moduletm-1:M/2-2t+1m]Bit, by analogy, will M/2t+1The output data stream of M clock cycles is spliced into data with the size of M/2bit, and the data is M/2 tht+1M +1 clocks are effective, and the output data stream effective signal is at M/2t+1m +1 clocks are valid and set to 1;
when 2 is intAnd when M is larger than M/2, sequentially intercepting the data with the size of M/2bit from the highest bit of the received output data stream, wherein the effective signal of the output data stream is effective once per clock and is set to be 1.
4. The method for storing multichannel data of oscillograph according to claim 1, wherein in step (8), the FIFO array for storing data recovery converts the data bit width of the received data per clock cycle into 2tThe specific method of m bits is as follows:
when the user stores 2 in the large-capacity dynamic memorytWhen the channel data is stored, the memory data recovery FIFO array converts the M bit data read out by the large-capacity dynamic memory in each clock cycle into 2 bits stored by the user in the large-capacity dynamic memorytBit width 2 corresponding to data of each channeltm bit，2tN, t is 0,1,2, …; after the data stream passes through the 1-stage FIFO, the bit width of the data stream is converted from M bit to 2sm bit；
When 2 is int＞2sWhen the user stores 2 in the large-capacity dynamic memorys+1When data of each channel is processed, the data stream output by the 1 st stage FIFO must pass through the 2 nd stage FIFO in the FIFO array, and the bit width of the data stream will be from 2sm bits to 2s+1mbit, and will be 2s+1The m bit data is sent to a snapshot module; when the user stores 2 in the large-capacity dynamic memorytWhen the data of each channel is needed, the data bit width is converted into 2 until the data flow passes through the t-s + 1-level FIFOtm bits, and send the data to the snapshot moduleA block;
when 2 is int＝2s2 of the output of the 1 st stage FIFOtThe m bit data is sent to a snapshot module;
when 2 is int＜2sThen, the data converted from the 1 st stage FIFO is placed in [ M-1: M-2 ] of the output datasm]Bit, output data [ M-1-2sm:0]The position is 0, when the user stores 2 in the large-capacity dynamic memorys-1When data of each channel is processed, the data stream output by the 1 st stage FIFO must pass through the 2 nd stage FIFO in the FIFO array, and the bit width of the data stream will be from 2sm bits to 2s-1m bits; the converted data is put in [ M-1: M-2 ] of the output datas-1m]Bit, output data [ M-1-2t-1m:0]The position is 0, and the data are sent to the snapshot module; when the user stores 2 in the large-capacity dynamic memorytWhen the data of each channel is needed, the data bit width is converted into 2 until the data flow passes through the s-t + 1-level FIFOtm bits; the converted data is put in [ M-1: M-2 ] of the output datatm]Bit, output data [ M-1-2tm:0]The position is 0 and the data is sent to the snapshot module.
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| CN108776249B (en) * | 2018-06-26 | 2020-04-14 | 电子科技大学 | Oscillograph recorder with double capturing functions |
| CN109976704A (en) * | 2019-03-29 | 2019-07-05 | 西安电子科技大学 | A kind of design method of the cascade fifo module based on FPGA |
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