CN109976704A - A kind of design method of the cascade fifo module based on FPGA - Google Patents

A kind of design method of the cascade fifo module based on FPGA Download PDF

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CN109976704A
CN109976704A CN201910247025.4A CN201910247025A CN109976704A CN 109976704 A CN109976704 A CN 109976704A CN 201910247025 A CN201910247025 A CN 201910247025A CN 109976704 A CN109976704 A CN 109976704A
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fifo module
cascade
1out
fifo
module
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廖桂生
杜佩鞠
曾操
许京伟
李世东
朱圣棋
刘洋
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Xidian University
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Xidian University
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

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Abstract

The invention belongs to technical field of radar communication, disclose a kind of design method of cascade fifo module based on FPGA, cascading fifo module includes: the first fifo module and the second fifo module, the output end of the data collection system of FPGA connects the input terminal of first fifo module, the output end of first fifo module connects the input terminal of second fifo module, the input terminal of first fifo module is the input terminal for cascading fifo module, and the output end of the second fifo module is the output end for cascading fifo module.The design method of cascade fifo module based on FPGA includes: to establish the parameter model of cascade fifo module；Based on this model, the parameter of the first fifo module and the second fifo module is calculated separately.The present invention is able to solve the design constraint of existing fifo module core, provides higher input and output bit wide than saving system resource.

Description

A kind of design method of the cascade fifo module based on FPGA
Technical field
The present invention relates to technical field of radar communication more particularly to a kind of design sides of the cascade fifo module based on FPGA Method.
Background technique
During the signal processing of radar system, we usually using field programmable gate array (full name in English: Field Programmable Gate Array, english abbreviation: FPGA) store the resulting data of sampling, and will be adopted by FPGA The resulting data of sample be transferred to Digital Signal Processing (full name in English: Digital Signal Processing, english abbreviation: DSP) chip is handled.When the resulting data of sampling are transferred to dsp chip from FPGA, the bit wide of data is often mismatched , it just needs to call intellectual property built in FPGA (Intellectual Property, IP) karyogenesis first in, first out (English at this time Literary full name: First Input First Output, english abbreviation: fifo module) carry out data buffer storage be transmitted further to digital letter Number processing (full name in English: Digital Signal Processing, english abbreviation: DSP) chip.
FIFO memory is the data buffer of first in, first out, it can only be sequentially written in data, sequentially reads data, number 1 completion is added by inside read-write pointer automatically according to address, it cannot be as commonly specified address can be accessed with certainly by address wire It is fixed that data are read or are written.Due to not having exterior read-write address wire, the use of fifo module is very simple.Fifo module is general For the data transmission between different clock-domains and different bit wides.Some important parameters of fifo module have: the width of fifo module Degree refers to the data bits of read-write operation of fifo module；The depth of fifo module refers to fifo module can deposit how many number According to；Full flag bit refers to the signal sent out when fifo module has been expired or will have been expired by the status circuit of fifo module, It causes to overflow to prevent the write operation of fifo module from continuing the write-in data into fifo module；Empty flag bit refers to FIFO mould Block is empty or will be empty when a signal being sent out by the status circuit of fifo module, with prevent the read operation of fifo module after Continue the reading for reading data into fifo module and causing invalid data；It reads clock and refers to the clock that read operation is followed, each Clock temporarily reads data along next；It writes clock and refers to the clock that write operation is followed, temporarily write data along next in each clock；Read pointer It is directed toward next reading address, it is automatic after running through to add 1；Write pointer is directed toward next address to be written, automatic after writing to add 1, Read and write pointer is exactly read/write address in fact, and only this address cannot arbitrarily select, but continuous.When fifo module uses It must be noted that occurring without overflowing or reading empty state, it is necessary to protect to guarantee that data are correctly written or read Fifo module is demonstrate,proved in the case where full, write operation is not can be carried out, not can be carried out read operation in an empty state.In Digital Design In, carrying out data processing using fifo module is very universal application, for example, realize that clock domain intersects, low delay caching, and always Line bit wide adjustment etc..
The attribute of fifo module has asymmetric bit wide ratio, and fifo module supports the write port bit wide and read port of fifo module Bit wide is not identical, data bit width variation, and the range of the asymmetric bit wide ratio of write port and read port is 1: 8 to 8: 1.Due to multi-pass Under conditions of channel array high-speed sampling, the resulting data bit width of FPGA sampling can be made higher, resulting data are sampled and sending It is non-right when the fifo module of existing FPGA is data cached since DSP only receives the data of 64 and more lower-order digit when to DSP Claim bit wide smaller than range, needs to extend.And it is 1: 16 to 16: 1 etc. higher non-that existing fifo module, which cannot achieve range, Symmetrical bit wide ratio.
Summary of the invention
The embodiment of the present invention provides a kind of design method of cascade fifo module based on FPGA, is able to solve existing The design constraint of fifo module core provides higher input and output bit wide ratio, and can save system resource.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
Technical solution one
Field-programmable gate array FPGA is integrated with radar data collection system and cascade fifo module, cascades fifo module Include:
First fifo module and the second fifo module；Described in the output end connection of the radar data collection system of the FPGA The input terminal of first fifo module, the output end of first fifo module connect the input terminal of second fifo module；Institute The input terminal for stating the first fifo module is the input terminal of the cascade fifo module, and the output end of second fifo module is institute State the output end of cascade fifo module.
Technical solution two
A kind of design method of the cascade first in, first out fifo module based on FPGA is applied to the cascade fifo module, It is characterized in that, which comprises
Step 1, the parameter model of cascade fifo module is established；
Step 2, the parameter model based on the cascade fifo module, calculates separately the first fifo module and the 2nd FIFO mould The parameter of block.
A kind of design method of cascade fifo module based on FPGA provided by the invention, can be different by two Fifo module cascade, is able to solve the design constraint of existing fifo module core, provides higher input and output bit wide ratio, meanwhile, Based on actual conditions, the parameter of every level-one fifo module is designed, to save system resource.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with It obtains other drawings based on these drawings.
Fig. 1 is cascade fifo module schematic diagram；
Fig. 2 is the input data analogous diagram for cascading fifo module；
Fig. 3 is the output data analogous diagram for cascading the first fifo module in fifo module；
Fig. 4 is the output data analogous diagram for cascading fifo module.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, technical solution in the embodiment of the present invention carry out it is clear, it is complete Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other Embodiment shall fall within the protection scope of the present invention.
Technical solution one
A kind of design method of the cascade first in, first out fifo module based on field-programmable gate array FPGA cascades FIFO Module includes:
First fifo module and the second fifo module.The output end of the data collection system of FPGA connects the first fifo module Input terminal, the output end of the first fifo module connects the input terminal of the second fifo module.The input terminal of first fifo module is The input terminal of fifo module is cascaded, the output end of the second fifo module is the output end for cascading fifo module.
It is existing that first fifo module and the second fifo module use the existing fifo module of FPGA to verify.
Technical solution two
A kind of design method of the cascade first in, first out fifo module based on FPGA is applied to cascade fifo module, special Sign is that method includes:
Step 1, the parameter model of cascade fifo module is established.
Further, the parameter model of step 1 cascade fifo module, specifically:
The input data frequency for cascading fifo module is fin, the output data frequency for cascading fifo module is fout, cascade The input data bit wide of fifo module is Win, the output data bit wide for cascading fifo module is Wout, cascade the input of fifo module Output data bit wide ratio is M=m1*m2, the input data rate for cascading fifo module is Vin=Win*fin, cascade the defeated of fifo module Data rate is V outout=Wout*fout。
The clock frequency of writing of first fifo module is f1in, the reading clock frequency of the first fifo module is f1out, the first FIFO The input data bit wide of module is W1in, the output data bit wide of the first fifo module is W1out, the input of the first fifo module is defeated Data bit width ratio is m out1, the first fifo module output data rate is V1=W1out*f1out, m1∈ { 2,4,8 }.
The clock frequency of writing of second fifo module is f2in, the reading clock frequency of the second fifo module is f2out, the 2nd FIFO The input data bit wide of module is W2in, the output data bit wide of the second fifo module is W2out, the input of the first fifo module is defeated Data bit width ratio is m out2, the output data rate of the second fifo module is V2=W2out*f2out, m2∈ { 2,4,8 }.
Step 2, the parameter model based on cascade fifo module, calculates separately the first fifo module and the second fifo module Parameter.
Further, step 2 specifically includes:
Step 2.1a, enables f1in=f1out, calculate the storage change rate Δ V of the first fifo module1:
Wherein, W1in/W1out=m1。
Step 2.2a calculates the storage change rate Δ V of the second fifo module2:
ΔV2=V1-Vout=W1out*f1out-Wout*fout
=(m2fin-fout)*Wout
Step 2.3a calculates the difference of the storage change rate of the first fifo module and the storage change rate of the second fifo module
Wherein, W1out/Wout=m2。
Step 2.4a, based on keep the first fifo module storage change rate and the second fifo module storage change rate it The smallest principle of difference, is calculated:m2=8.
Step 2.5a, the depth for calculating the first fifo module areNeeded for grade fifo module Storage depth is (m2*fin-fout)*Wout*PRT。
Wherein, PRT is the pulse repetition period.
It should be noted that due in practice, m1- 2 > 0, m2> 0, fin> 0, fout> 0, Wout> 0, therefore, m2* fin*(m1-2)+fout> 0, (m2*fin*(m1-2)+fout)*Wout> 0, i.e. Δ V1-ΔV2> 0, so based on the first FIFO is kept The smallest principle of difference of the storage change rate of the storage change rate and the second fifo module of module, it can be seen that work as m2It obtains maximum When value, Δ V1-ΔV2Minimum, therefore m2=8.In addition, in actual operation, the data cached every time are the number in a PRT According to.
Further, step 2 further includes
Step 2.1b, enables f1out=fout, calculate the storage change rate Δ V of the first fifo module1':
Wherein, W1in/W1out=m1。
Step 2.2b calculates the storage change rate Δ V of the second fifo module2':
ΔV2'=V1-Vout=W1out*f1out-Wout*fout=fout*(W1out-Wout)
=fout*(m2-1)*Wout
Step 2.3b calculates the difference of the storage change rate of the first fifo module and the storage change rate of the second fifo module
Wherein, W1out/Wout=m2。
Step 2.4b enables Δ V '=0, is calculated
Step 2.5b, the depth for calculating the first fifo module areSecond fifo module Depth be fout*(m2-1)*Wout*PRT。
Wherein, PRT is the pulse repetition period.
A kind of design method of cascade fifo module based on FPGA provided by the invention, can be different by two Fifo module cascade, is able to solve the design constraint of existing fifo module core, provides higher input and output bit wide ratio, meanwhile, Based on actual conditions, the parameter of every level-one fifo module is designed, to save system resource.
A kind of design side of cascade fifo module based on FPGA is provided to the embodiment of the present invention below by emulation experiment The beneficial effect of method is further described.
Simulation parameter cascades the input data bit wide W of fifo moduleinIt is 64, output data bit wide WoutIt is 4, input Sampling rate finFor 100MHz, sampling rate f is exportedoutFor 125MHz.A kind of cascade based on FPGA provided through the invention M is calculated in the design method of fifo module1=2, m2=8, the first fifo module output data bit wide WoutIt is 32 second Fifo module output data bit wide WoutIt is 4.
In analogous diagram, wr_en is the data enable signal of writing of the first fifo module, and wr_en2 is the second fifo module Data enable signal is write, full is the full flag bit of the first fifo module, and full2 is the full flag bit of the second fifo module, Empty is the empty flag bit of the first fifo module, and empty2 is the empty flag bit of the second fifo module, and rd_en is the first FIFO The reading data enable signal of module and the second fifo module, rd_clk are the reading data clock of the second fifo module, din first The input data of fifo module, dout1 are the output data of the first fifo module, and dout2 is the output number of the second fifo module According to.
It is by Fig. 2, Fig. 3 and Fig. 4 available, a kind of cascade fifo module based on FPGA provided in an embodiment of the present invention The input data bit wide for the cascade fifo module that design method obtains is 64, and output data bit wide is 4, inputoutput data Bit wide ratio is 64/4=16, beyond the existing asymmetric bit wide of fifo module core than range (8: 1 or 1: 8), and the cascade Fifo module can accurately and effectively transmit data.
Those of ordinary skill in the art will appreciate that: realize that all or part of the steps of above method embodiment can pass through The relevant hardware of program instruction is completed, and program above-mentioned can be stored in a computer readable storage medium, the program When being executed, step including the steps of the foregoing method embodiments is executed；And storage medium above-mentioned includes: ROM, RAM, magnetic disk or light The various media that can store program code such as disk.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.

Claims (5)

1. a kind of design method of the cascade fifo module based on field-programmable gate array FPGA, the field-programmable gate array Column FPGA is integrated with radar data collection system and cascade fifo module, which is characterized in that the cascade fifo module includes:
First fifo module and the second fifo module；The output end connection described first of the radar data collection system of the FPGA The input terminal of fifo module, the output end of first fifo module connect the input terminal of second fifo module；Described The input terminal of one fifo module is the input terminal of the cascade fifo module, and the output end of second fifo module is the grade Join the output end of fifo module.
2. a kind of design side of cascade fifo module based on field-programmable gate array FPGA according to claim 1 Method, which is characterized in that it is described cascade fifo module design method include:
Step 1, the parameter model of cascade fifo module is established；
Step 2, the parameter model based on the cascade fifo module, calculates separately the parameter and the 2nd FIFO of the first fifo module The parameter of module.
3. a kind of design side of cascade fifo module based on field-programmable gate array FPGA according to claim 2 Method, which is characterized in that
The parameter model of fifo module is cascaded described in step 1, specifically:
The input data frequency of the cascade fifo module is fin, the output data frequency of the cascade fifo module is fout, institute The input data bit wide for stating cascade fifo module is Win, the output data bit wide of the cascade fifo module is Wout, the cascade The inputoutput data bit wide ratio of fifo module is M=m1*m2, the input data rate of the cascade fifo module is Vin=Win* fin, the output data rate of the cascade fifo module is Vout=Wout*fout；
The clock frequency of writing of first fifo module is f1in, the reading clock frequency of first fifo module is f1out, first The input data bit wide of fifo module is W1in, the output data bit wide of the first fifo module is W1out, first fifo module Inputoutput data bit wide ratio be m1, the first fifo module output data rate is V1=W1out*f1out, m1∈ { 2,4,8 }；
The clock frequency of writing of second fifo module is f2in, the reading clock frequency of second fifo module is f2out, second The input data bit wide of fifo module is W2in, the output data bit wide of the second fifo module is W2out, first fifo module Inputoutput data bit wide ratio be m2, the output data rate of second fifo module is V2=W2out*f2out, m2∈ 2, 4,8 }；
Wherein, fin=f1in, f1out=f2in, fout=f2out, Win=W1in, W1out=W2in, Wout=W2out, Vout=V2。
4. a kind of design side of cascade fifo module based on field-programmable gate array FPGA according to claim 2 Method, which is characterized in that
The step 2 specifically includes:
Step 2.1a, enables f1in=f1out, calculate the storage change rate Δ V of the first fifo module1:
Wherein, W1in/W1out=m1；
Step 2.2a calculates the storage change rate Δ V of the second fifo module2:
ΔV2=V1-Vout=W1out*f1out-Wout*fout
=(m2fin-fout)*Wout
Step 2.3a calculates the difference of the storage change rate of the first fifo module and the storage change rate of the second fifo module
Wherein, W1out/Wout=m2；
Step 2.4a, the storage change rate based on the storage change rate and the second fifo module that keep first fifo module it The smallest principle of difference, is calculated:m2=8；
Step 2.5a, the depth for calculating the first fifo module areStorage needed for grade fifo module Depth is (m2*fin-fout)*Wout*PRT；
Wherein, PRT is the pulse repetition period.
5. a kind of design side of cascade fifo module based on field-programmable gate array FPGA according to claim 4 Method, which is characterized in that the step 2 is specific further include:
Step 2.1b, enables f1out=fout, calculate the storage change rate Δ V of the first fifo module1':
Wherein, W1in/W1out=m1；
Step 2.2b calculates the storage change rate Δ V of the second fifo module2':
ΔV2'=V1-Vout=W1out*f1out-Wout*fout=fout*(W1out-Wout)
=fout*(m2-1)*Wout
Step 2.3b calculates the difference of the storage change rate of the first fifo module and the storage change rate of the second fifo module
Wherein, W1out/Wout=m2；
Step 2.4b enables Δ V '=0, is calculated
Step 2.5b, the depth for calculating the first fifo module areThe depth of second fifo module Degree is fout*(m2-1)*Wout*PRT；
Wherein, PRT is the pulse repetition period.
CN201910247025.4A 2019-03-29 2019-03-29 A kind of design method of the cascade fifo module based on FPGA Pending CN109976704A (en)

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Application publication date: 20190705