CN105608028A - EMIF (External Memory Interface) and dual-port RAM (Random Access Memory)-based method for realizing high-speed communication of DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) - Google Patents
EMIF (External Memory Interface) and dual-port RAM (Random Access Memory)-based method for realizing high-speed communication of DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) Download PDFInfo
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- CN105608028A CN105608028A CN201510679527.6A CN201510679527A CN105608028A CN 105608028 A CN105608028 A CN 105608028A CN 201510679527 A CN201510679527 A CN 201510679527A CN 105608028 A CN105608028 A CN 105608028A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
Abstract
The invention provides an EMIF (External Memory Interface) and dual-port RAM (Random Access Memory)-based method for realizing the high-speed communication of a DSP (Digital Signal Processor) and an FPGA (Field Programmable Gate Array). The method comprises the steps of providing the FPGA and allocating an RAM in the FPGA, wherein the RAM comprises a first storage area, a second storage area, a first port and a second port; providing the DSP and an EMIF and connecting the DSP with the first port through the EMIF, wherein the first port is connected with the first storage area; connecting the FPGA with the second port, wherein the second port is connected with the second storage area; and realizing the high-speed communication of the FPGA and the DSP. The method provided by the invention has the advantages that the data two-way rapid transmission between the DSP and the FPGA is realized through the EMIF, so that the problem that a great deal of data need to be transmitted and processed in real time is effectively solved; the method can be widely applied to signal processing systems and can particularly be applied to various real-time signal processing systems.
Description
Technical field
The invention belongs to communication technical field between DSP and FPGA, be specifically related to a kind of based on EMIF interface and twoMouth RAM realizes DSP and FPGA high-speed communication method.
Background technology
Along with airmanship, the fast development of satellite technology and modern electronic technology, airborne equipment day by day toDigitlization, modularization, integrated direction development, airborne equipment not only needs to gather, receives, processes,Send a large amount of external datas, between the each CPU of device interior, also need to carry out simultaneously mass data and information andIn time, processes and high-speed transfer. General computer platform is FPGA+DSP structure now, can give full play to DSPAdvantage and FPGA data acquisition process and the interface communication advantage of arithmetic speed, can finely meet data acquisitionCollection, processing and external communication need. In time whether inner DSP and FPGA transfer of data, effectively transmission is straightConnect the precision performance and the real-time that are determining airborne equipment. Prior art adopts asynchronous FIFO and synchronization fifoRealize the continuous transmission of DSP and FPGA data, but can not solve the real-time of transfer of data, therefore having mustPropose to improve.
Summary of the invention
The technical problem that the present invention solves: provide a kind of based on EMIF interface and dual port RAM realize DSP withFPGA high-speed communication method, sets up dual port RAM in FPGA inside, and dual port RAM one end is with memory modeCommunicate by letter with DSP by EMIF interface, the other end is communicated by letter with FPGA innernal CPU, realizes FPGA and DSP coupleThe independent read-write of this dual port RAM, solution mass data needs to process in time and the problem of transmitting.
The technical solution used in the present invention: realize DSP and FPGA is logical at a high speed based on EMIF interface and dual port RAMLetter method, comprises the steps: 1) FPGA is provided, be described FPGA internal configurations RAM, described RAM bagDraw together the first memory block, the second memory block, the first port and the second port; 2) provide DSP and EMIF interface,Described DSP is connected to described the first port and described first with described the first port by described EMIF interfaceMemory block connects; 3) described FPGA is connected to described the second port and described second with described the second portMemory block connects; 4) described FPGA and described DSP realize high-speed communication.
Preferably, 1) described FPGA is by described the second port data writing in described the second memory block;2) internal logic circuit of described FPGA produces interrupt signal, to the interrupt control unit module Shen of described DSPPlease interrupt; 3) described DSP response interrupt requests, data query collection status information, according to status information,Determine the data set that reads renewal, by described EMIF interface sense data from described the second memory block.
Preferably, 1) described DSP is by described the first port data writing in described the first memory block; 2)After completing, described DSP produces interrupt signal by GPIO module with soft interrupt mode, to the interruption of described FPGAController module application is interrupted; 3) described FPGA response interrupt requests, data query collection status information, rootAccording to status information, determine the data set that reads renewal, read the data of described the first memory block.
Preferably, described the first memory block comprises the first data set state memory block and the first data set storageDistrict, described the first data set state memory block is for more new state information of stored data sets, and described first countsBe used for storing data according to collection memory block.
Preferably, described the second memory block comprises the second data set state memory block and the second data set storageDistrict, described the second data set state memory block is for more new state information of stored data sets, and described second countsBe used for storing data according to collection memory block.
Compared to prior art, the data that the present invention has passed through EMIF Interface realization between DSP and FPGA are twoTo fast transport, efficiently solving a large amount of data needs problem the method for real-time Transmission and processing passableBe widely used in signal processing system aspect, especially can be applicable to various real time signal processings.
Brief description of the drawings:
Fig. 1 is data flow block diagram in the present invention.
Detailed description of the invention
Below in conjunction with accompanying drawing 1, embodiments of the invention are described: based on EMIF interface and dual port RAM realize DSP withFPGA high-speed communication method, comprises the steps:
1) providing FPGA, is FPGA internal configurations RAM, and RAM comprises the first memory block, the second memory block,One port and the second port; The data bit width of FPGA device can be configured to 8 according to different application scenariosPosition, 16,32,64,128; The first port and the second port have data wire, address separatelyLine, read-write control line can allow different systems its shared memory space to be conducted interviews simultaneously,Realization conducts interviews to the shared memory space of the RAM of FPGA inside with DSP and FPGA simultaneously;
2) provide DSP and EMIF interface, DSP is connected to the first port by EMIF interface with the first portBe connected with the first memory block; EMIF is connecing of communicating by letter between unit in external memory storage and TMS320C6713 sheetMouthful, when DSP access external memory, must pass through EMIF interface, EMIF interface is corresponding with FPGA internal RAMPin connect and realize DSP access FPGA internal RAM;
3) FPGA is connected with the second port, the second port is connected with the second memory block;
4) FPGA and DSP realize high-speed communication.
FPGA, to the method for DSP transmission data, comprises the steps:
1) FPGA is by the second port data writing in the second memory block;
2) internal logic circuit of FPGA produces interrupt signal, interrupts to the interrupt control unit module application of DSP;
3) DSP response interrupt requests, data query collection status information, according to status information, determines and reads moreNew data set is read data writing by EMIF interface from the second memory block.
DSP, to the method for FPGA transmission data, comprises the steps:
1) DSP is by the first port data writing in the first memory block;
2) complete after DSP produce interrupt signal by GPIO module with soft interrupt mode, to the interruption control of FPGADevice module application processed is interrupted;
3) FPGA response interrupt requests, data query collection status information, according to status information, determines and readsThe data set upgrading, reads the data of the first memory block.
In the present embodiment, described internal logic circuit, interrupt control unit module and GPIO module are all passed throughThe transmission of CPU module control signal.
By above two transmission methods, can not only realize the fast transport of data in DSP and FPGA, alsoCan realize the fast processing of data in DSP. This mode can effectively be brought into play the advantage of DSP and FPGA,To reach the transmission of optimum signal and the effect of processing, within the unit interval treatable data volume more greatly withAnd the fast transport of data.
Concrete, to communicate by letter with the correct of DSP in order to realize FPGA, the physics that first will realize between the two connectsConnect, the first port of RAM is passed through to EMIF interface accessing FPGA internal RAM for DSP, the second port is used forFPGA accesses RAM. DSP visits shared memory space by the first port, and FPGA is by the second portAccess shared memory space. Wherein the data wire of EMIF is connected respectively to data-in port and the number of RAMAccording to output port, controlled the address wire of EMIF interface and RAM by the transmission direction of AOE data signalThe address wire of the first port connects, and the clock signal of EMIF interface clock output signal ECLKOUT1 and RAM is drawnPin connects, and AOE, ARE, AWE, CE signal are connected with RAM corresponding signal through FPGA combinational logic, with realityThe read-write capability of existing DSP to FPGA internal RAM. FPGA is inner to be connected by address wire, data wire and control lineConnect RAM the second port, realize the read-write capability of FPGA to RAM.
Further, the first memory block comprises the first data set state memory block and the first data set memory block,The first data set state memory block is for more new state information of stored data sets, and the first data set memory block is usedIn storage data; The second memory block comprises the second data set state memory block and the second data set memory block,The second data set state memory block is for more new state information of stored data sets, and the second data set memory block is usedIn storage data.
Can be understood as the corresponding data set state storage of specifying of each data set in data set memory blockDistrict. After Data Update by data set state information updating in data set state memory block, can be according to state moreFresh information reads the data set of variation, improves data reading performance using redundancy. To pass according to these two kinds of transmission meansData set fix size and the address realm of these two memory blocks, DSP and FPGA access fixed address at every turnMemory block with length.
To sum up, the DSP of using provided by the invention and FPGA high-speed communication method have passed through EMIF Interface realizationData double-way fast transport between DSP and FPGA, efficiently solving a large amount of data needs real-time TransmissionCan be widely used in signal processing system aspect with problem the method for processing, especially can be applicable to variousReal time signal processing.
Above-described embodiment, is preferred embodiment of the present invention, is not used for limiting the scope of the present invention,Therefore the equivalence of being done with content described in the claims in the present invention all changes, and all should be included in right of the present invention and wantWithin asking scope.
Claims (5)
1. realize DSP and FPGA high-speed communication method based on EMIF interface and dual port RAM, it is characterized in that bagDraw together following step:
1) providing FPGA, is described FPGA internal configurations RAM, and described RAM comprises the first memory block, secondMemory block, the first port and the second port;
2) provide DSP and EMIF interface, described DSP is connected by described EMIF interface and described the first portConnect, described the first port is connected with described the first memory block;
3) described FPGA is connected with described the second port, described the second port and described the second memory block connectConnect;
4) described FPGA and described DSP realize high-speed communication.
2. according to claim 1ly realize DSP and FPGA is logical at a high speed based on EMIF interface and dual port RAMLetter method, is characterized in that:
1) described FPGA is by described the second port data writing in described the second memory block;
2) internal logic circuit of described FPGA produces interrupt signal, to the interrupt control unit module of described DSPApplication is interrupted;
3) described DSP response interrupt requests, data query collection status information, according to status information, determines and readsGet the data set of renewal, from described the second memory block, read data writing by described EMIF interface.
3. according to claim 1ly realize DSP and FPGA is logical at a high speed based on EMIF interface and dual port RAMLetter method, is characterized in that:
1) described DSP is by described the first port data writing in described the first memory block;
2) complete after described DSP produce interrupt signal by GPIO module with soft interrupt mode, to described FPGAThe application of interrupt control unit module interrupt;
3) described FPGA response interrupt requests, data query collection status information, according to status information, determinesRead the data set of renewal, read the data of described the first memory block.
4. according to claim 1ly realize DSP and FPGA is logical at a high speed based on EMIF interface and dual port RAMLetter method, is characterized in that, described the first memory block comprises the first data set state memory block and the first numberAccording to collection memory block, described the first data set state memory block is for more new state information of stored data sets, instituteState the first data set memory block for storing data.
5. according to claim 1ly realize DSP and FPGA is logical at a high speed based on EMIF interface and dual port RAMLetter method, is characterized in that, described the second memory block comprises the second data set state memory block and the second numberAccording to collection memory block, described the second data set state memory block is for more new state information of stored data sets, instituteState the second data set memory block for storing data.
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| CN201510679527.6A CN105608028A (en) | 2015-10-19 | 2015-10-19 | EMIF (External Memory Interface) and dual-port RAM (Random Access Memory)-based method for realizing high-speed communication of DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) |
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| CN106248132A (en) * | 2016-07-21 | 2016-12-21 | 中车青岛四方车辆研究所有限公司 | High-speed multiple channel analog quantity real-time detecting system with enhanced data caching |
| CN109039911A (en) * | 2018-07-27 | 2018-12-18 | 烽火通信科技股份有限公司 | It is a kind of to search the method and system that mode shares RAM based on HASH |
| CN109446126A (en) * | 2018-10-17 | 2019-03-08 | 天津津航计算技术研究所 | DSP and FPGA high-speed communication system and method based on EMIF bus |
| CN111679599A (en) * | 2020-05-22 | 2020-09-18 | 中国航空工业集团公司西安航空计算技术研究所 | High-reliability exchange method for CPU and DSP data |
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| CN106248132A (en) * | 2016-07-21 | 2016-12-21 | 中车青岛四方车辆研究所有限公司 | High-speed multiple channel analog quantity real-time detecting system with enhanced data caching |
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| CN111679599A (en) * | 2020-05-22 | 2020-09-18 | 中国航空工业集团公司西安航空计算技术研究所 | High-reliability exchange method for CPU and DSP data |
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