CN110940841B

CN110940841B - Digital three-dimensional oscilloscope rapid acquisition system based on FPGA

Info

Publication number: CN110940841B
Application number: CN201910953804.6A
Authority: CN
Inventors: 许波; 陈凯; 程玉华; 杨云鹏; 邹松庭; 颜雁军; 张硕; 韩文强; 赵佳
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2019-10-09
Filing date: 2019-10-09
Publication date: 2020-12-01
Anticipated expiration: 2039-10-09
Also published as: CN110940841A

Abstract

The invention discloses a digital three-dimensional oscilloscope rapid acquisition system based on FPGA, a signal to be detected is acquired by an ADC module and then stored in a data acquisition module through a snapshot module, a DTO _ FIFO is arranged in the data acquisition module, the reading and writing of the DTO _ FIFO are controlled by a control module through a counter, so that the DTO _ FIFO can read out the waveform data of the previous frame for mapping while storing the waveform data of the current frame; when the frame number of the waveform mapping in the digital three-dimensional mapping module reaches the set value of the upper computer, the upper computer reads and takes the mapping result stored in the RAM, and converts the mapping result into RGB values to be displayed in the display module. The invention can improve the DTO waveform capture rate and save FIFO storage resources.

Description

Digital three-dimensional oscilloscope rapid acquisition system based on FPGA

Technical Field

The invention belongs to the technical field of digital three-dimensional oscilloscopes, and particularly relates to a digital three-dimensional oscilloscope rapid acquisition system based on an FPGA.

Background

With the continuous development of electronic test technology, the capture of abnormal signals becomes a hot spot problem in the field of time domain test. The traditional oscilloscope can only move each frame of waveform meeting the trigger to a screen for displaying, and a user cannot directly observe the frequency of abnormal signals. In order to improve the capture rate of Oscilloscopes and solve the requirements of users on abnormal signal observation, a Digital Three-Dimensional oscilloscope (DTO for short) which is a new type of Digital oscilloscope gradually becomes the mainstream of the market. The data collected by the DTO is stored in a waveform database after being subjected to waveform mapping processing, and a plurality of pieces of waveform information accumulated in the database are sent to a screen for display once through multiple times of collection and mapping. Compared with the traditional DSO, the DTO has higher waveform capture rate. It intuitively expresses probability information contained in the accumulated waveform by color or luminance values through special image processing, enabling a user to better observe an abnormal signal of interest.

To improve the capture rate of DTO waveforms, some manufacturers propose a fast acquisition mode (FastAcq). In this mode, the DTO performs fast acquisition and mapping of waveforms, reducing dead time by improving the acquisition architecture, so that the waveform capture rate can reach the level of millions of waveforms per second. However, this mode also has problems of large consumption of memory resources and complicated control logic. Based on the above problems, a new FastAcq implementation is proposed herein, which enables acquisition and mapping of waveforms to be performed simultaneously by improving the architecture, and reduces dead time to 0 under the condition of using less storage resources, thereby improving the overall performance of DTO.

In the prior art, there are two main ways to realize the fast acquisition mode of waveforms:

the first mode is as follows: when a user selects a fast acquisition mode, DATA ADC _ DATA acquired by the ADC is firstly cached in a FIFO (First Input First Output, First in First out), and after the FIFO is full of a frame of waveform DATA, the DATA in the FIFO is subjected to three-dimensional mapping by opening a reading enable of the FIFO. The method is simple in logic and low in implementation difficulty, but when the FIFO data are read out for mapping, new sampling data are not written in, and a large dead time exists in the acquisition process, so that the waveform capture rate of the DTO is low.

The second mode is as follows: considering that one FIFO has larger dead time for data acquisition, the method establishes two FIFOs for ping-pong operation. After FIFO _1 is full of one frame of waveform, reading FIFO _1 to map the waveform, and simultaneously storing new acquisition data into FIFO _ 2. When the FIFO _2 is full of one frame of waveform, reading the FIFO _2 to map the waveform, and simultaneously storing new acquisition data into the FIFO _ 1. Therefore, seamless caching and mapping of ADC acquisition data are realized. The method has the advantages of reducing dead time and improving the waveform capture rate, and has the disadvantages of needing two instantiated FIFO modules, using more FIFO resources and having more complex control logic.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provide a digital three-dimensional oscilloscope rapid acquisition system based on an FPGA (field programmable gate array), which can improve the DTO waveform capture rate and save FIFO (first in first out) storage resources.

In order to achieve the above object, the digital three-dimensional oscilloscope rapid acquisition system based on the FPGA of the present invention comprises an ADC module, a snapshot module, a trigger module, a data acquisition module, a control module, a digital three-dimensional mapping module, an upper computer and a display module, wherein the snapshot module, the trigger module, the data acquisition module, the control module and the digital three-dimensional mapping module are implemented in the FPGA, and wherein:

the ADC module collects input signals, the resolution of the ADC module is recorded as M bits, a collected sampling sequence ADC _ DATA is simultaneously sent to the snapshot module and the trigger module, and the number of collection points of each system clock is recorded as N;

the snapshot module performs snapshot on the sampling sequence ADC _ DATA according to a snapshot coefficient sent by the upper computer, and when the number of acquisition points obtained by snapshot reaches N, the N DATA points are packaged into a DATA sequence DATA _ EX and sent to the trigger module; meanwhile, packing every N DATA points after snapshot into a DATA sequence DATA _ IN to be sent to a DATA acquisition module, wherein a DATA enable signal din _ valid continues to be a high level of a system clock;

the trigger module detects a sampling sequence ADC _ DATA and a DATA sequence DATA _ EX, when effective triggering is detected to arrive, the trigger module outputs a trigger signal Trig _ out to the control module continuously for one high level of a system clock, the trigger signal Trig _ out is required to be aligned with the position of an effective trigger point IN the DATA _ IN sequence when the trigger signal Trig _ out is effective, and meanwhile, a specific trigger position Addr of the effective trigger point IN N pieces of snapshot DATA is sent to the DATA acquisition module;

the DATA acquisition module is used for caching a DATA sequence DATA _ IN, 1 DTO _ FIFO is arranged IN the DATA sequence DATA _ IN, the width of the DTO _ FIFO is M × N bits, the depth D meets the condition that D × N is more than or equal to L +2N, and L represents the number of DATA points required by the display module when one waveform is displayed; the read-write state of a DTO _ FIFO of the DATA acquisition module is controlled by a write enable signal wr _ en, a read enable signal rd _ en and a DATA enable signal din _ valid sent by a control module, and when the write enable signal wr _ en and the DATA enable signal din _ valid are both high, a DATA sequence DATA _ IN is written into the DTO _ FIFO; when a read enable signal rd _ en and a DATA enable signal din _ valid are both high, DATA in a DTO _ FIFO is read OUT, when the read-OUT DATA is effective DATA of a frame waveform, a DATA acquisition module discards the previous N-pre _ depth% N + Addr DATA points, wherein pre _ depth represents a pre-trigger depth, and% represents a remainder operation, then every N effective DATA points are packed into a DATA sequence DATA _ OUT to be sent to a digital three-dimensional mapping module, and meanwhile, a read-OUT DATA effective signal dout _ valid is enabled to continue to be a high level of a system clock;

the control module is used for performing read-write control on the data acquisition module and controlling the digital three-dimensional mapping module, and is internally provided with a state machine which comprises an IDLE state, a PRE-trigger PRE _ TRIG state, a WAIT-trigger WAIT _ TRIG state and a read data VALID _ RD state;

when the state machine works in an IDLE state, the DTO _ FIFO is in a reset state, a write enable signal wr _ en and a read enable signal rd _ en are both 0, a write data counter write _ count is set to be 0, and a read data frame number counter count _ frame is set to be 0; when the control module detects that a rapid acquisition signal DTO _ Begin is 1, the DTO _ FIFO is reset, the control module receives a PRE-trigger depth PRE _ depth and a waveform mapping frame number frame _ num from an upper computer, and the state machine enters a PRE-trigger PRE _ TRIG state;

when the state machine works IN a PRE-trigger PRE _ TRIG state, the control module enables a write enable signal wr _ en to be high, when the write enable signal wr _ en and a DATA enable signal din _ valid are high level, a DATA sequence DATA _ IN is written into a DTO _ FIFO, a write DATA counter write _ count is adopted to count DATA written into the DTO _ FIFO, and the write _ count step value is N; when the write data counter meets the condition that the write _ count is more than or equal to pre _ depth, the pre-trigger depth is full, and the state machine enters a WAIT-trigger WAIT _ TRIG state;

when the state machine works in a WAIT-to-trigger WAIT _ TRIG state, the control module sets a read enable signal rd _ en high, when the read enable signal rd _ en and a data enable signal din _ valid of the DTO _ FIFO are both high level, the DTO _ FIFO is in a state of reading while writing, and when the data enable signal din _ valid is low level, the DTO _ FIFO is in a state of neither reading nor writing; at this time, the state machine waits for the arrival of a trigger signal Trig _ out, and the write _ count is more than or equal to pre _ depth and keeps unchanged; when the trigger signal Trig _ out arrives, the state machine enters a read data state VALID _ RD;

when the state machine works in a read data state VALID _ RD, a read enable signal RD _ en and a write enable signal wr _ en are both high level, and when a data enable signal din _ VALID is high level, the DTO _ FIFO is in a read-while-write state; when the write data counter write _ count is L +2N, indicating that one frame of waveform has been completely written into the DTO _ FIFO, the write data counter write _ count is set to 0 and then continues counting; reading data at the same time, and setting an output data point counter valid _ count to count a frame of output waveform data points; when the data enable signal din _ valid is at a high level, the data point read out at this time is valid data of a frame waveform, when the output data point counter valid _ count is L +2N, it indicates that a frame waveform has been completely read out from the DTO _ FIFO, the read data frame counter count _ frame is count _ frame +1, the output data point counter active _ count is set to 0, and preparation is made for waveform output counting of the next frame; if the data frame number counter count _ frame _ num is read from the DTO _ FIFO, it indicates that the waveform acquisition process is completed, sets the acquisition completion signal DTO _ done to 1, and the state machine enters an IDLE state; if the counter count _ frame < frame _ num of the read data frame number, the state machine enters a WAIT to trigger WAIT _ TRIG state;

the digital three-dimensional mapping module is used for reading a DATA sequence DATA _ OUT from the DATA acquisition module when the DATA valid signal dout _ valid is high, and then converting the DATA sequence DATA _ OUT into a statistical value corresponding to each pixel point in the display module;

the upper computer is used for controlling the FPGA and receiving data, resetting the data acquisition module, the control module and the digital three-dimensional mapping module before starting rapid acquisition, sending a pre-trigger depth pre _ depth and a waveform mapping frame _ num to the control module by the upper computer after the resetting is finished, and then setting a rapid acquisition signal DTO _ Begin to be 1; when the upper computer detects that the acquisition completion signal DTO _ done is 1, all probability data in the digital three-dimensional mapping module are read to the upper computer, and each probability data is converted into an RGB value and sent to the display module; when data acquisition needs to be stopped, setting a rapid acquisition signal DTO _ Begin to be 0;

and the display module refreshes the waveform on the screen of the oscilloscope according to the RGB value received from the upper computer.

According to the digital three-dimensional oscilloscope rapid acquisition system based on the FPGA, a signal to be detected is acquired by the ADC module and then stored in the data acquisition module through the snapshot module, a DTO _ FIFO is arranged in the data acquisition module, and the reading and writing of the DTO _ FIFO are controlled by the control module through the counter, so that the DTO _ FIFO can store the waveform data of the current frame and read the waveform data of the previous frame for mapping; when the frame number of the waveform mapping in the digital three-dimensional mapping module reaches the set value of the upper computer, the upper computer reads and takes the mapping result stored in the RAM, and converts the mapping result into RGB values to be displayed in the display module.

The invention has the following beneficial effects:

(1) compared with the first mode in the background technology, the invention can capture all effective trigger waveforms, thereby effectively reducing dead time, improving waveform capture rate,

(2) compared with the second mode in the background art, the invention only uses one FIFO, reduces the use of storage resources by 50 percent, does not need ping-pong operation and has simpler logic control.

Drawings

FIG. 1 is a block diagram of an embodiment of the rapid acquisition system of a digital three-dimensional oscilloscope based on FPGA according to the present invention;

FIG. 2 is a state machine diagram of a control module of the present invention;

FIG. 3 is a schematic diagram of a digital three-dimensional mapping module according to the present invention;

FIG. 4 is a signal real-time diagram in the waveform acquisition and mapping process of the digital three-dimensional oscilloscope.

Detailed Description

The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.

Examples

Fig. 1 is a structural diagram of a specific embodiment of the rapid acquisition system of a digital three-dimensional oscilloscope based on an FPGA according to the present invention. As shown in fig. 1, the digital three-dimensional oscilloscope rapid acquisition system based on FPGA of the present invention includes an ADC module 1, a snapshot module 2, a trigger module 3, a data acquisition module 4, a control module 5, a digital three-dimensional mapping module 6, an upper computer 7 and a display module 8, wherein the snapshot module 2, the trigger module 3, the data acquisition module 4, the control module 5 and the digital three-dimensional mapping module 6 are implemented in an FPGA (Field-Programmable Gate Array), and each module is described in detail below.

The ADC module 1 collects input signals, the resolution of the ADC module is recorded as M bits, a collected sampling sequence ADC _ DATA is sent to the snapshot module 2 and the trigger module 3, and the number of collection points of each system clock is recorded as N.

The snapshot module 2 performs snapshot on the sampling sequence ADC _ DATA according to a snapshot coefficient sent by the upper computer, and when the number of acquisition points obtained by snapshot reaches N, the N DATA points are packaged into a DATA sequence DATA _ EX and sent to the trigger module; and meanwhile, packing every N DATA points after snapshot into a DATA sequence DATA _ IN and sending the DATA sequence DATA _ IN to the DATA acquisition module, wherein the DATA enable signal din _ valid continues to be at a high level of a system clock. For a high-speed ADC, each system clock corresponds to N acquisition points, and N is more than or equal to 1. When the snapshot coefficient is 1, namely no snapshot is performed, the snapshot module 2 directly packages the acquired N DATA points into a DATA sequence DATA _ EX and a DATA sequence DATA _ IN; when the snapshot coefficient is greater than 1, IN order to facilitate the DATA acquisition module 4 to cache DATA, when the DATA points after snapshot reach N each time, the snapshot module 2 packs the N DATA points into a DATA sequence DATA _ EX and a DATA sequence DATA _ IN.

The trigger module 3 detects a sampling sequence ADC _ DATA and a DATA sequence DATA _ EX, taking the most common edge trigger IN an oscilloscope as an example, the upper computer 7 sends a trigger level to the trigger module 3, when an effective trigger arrives, the trigger module outputs a trigger signal Trig _ out to the control module 5, the trigger signal Trig _ out is pulled down after lasting for a high level of a system clock period, the trigger signal Trig _ out is required to be aligned with the position of an effective trigger point IN a DATA _ IN sequence when being effective, meanwhile, a specific trigger position Addr of the effective trigger point IN N pieces of snapshot DATA is sent to the DATA acquisition module 4, and obviously, Addr is more than or equal to 0 and less than or equal to N-1;

the DATA acquisition module 4 is used for buffering the DATA sequence DATA _ IN, and 1 DTO _ FIFO is arranged inside the DATA acquisition module. Suppose the working clock of FPGA is f_sysThe resolution of the ADC is Mbit, N data points are output by each system clock ADC, L data points are required for each waveform displayed by the display module 8, and then the width of the DTO _ FIFO is M × Nbits, and the depth D satisfies D × N ≧ L + N. The read-write state of the DTO _ FIFO of the DATA acquisition module 4 is controlled by a write enable signal wr _ en, a read enable signal rd _ en and a DATA enable signal din _ valid sent by the control module 5, and when the write enable signal wr _ en and the DATA enable signal din _ valid are high, a DATA sequence DATA _ IN is written into the DTO _ FIFO; when read is enabledWhen the signal rd _ en and the DATA enable signal din _ valid are high, the DATA in the DTO _ FIFO is read OUT, and when the read-OUT DATA is valid DATA of one frame waveform, the DATA acquisition module 4 discards the first N-pre _ depth% N + Addr DATA points, then packs each N valid DATA points into a DATA sequence DATA _ OUT and sends the DATA sequence DATA _ OUT to the digital three-dimensional mapping module 6, and meanwhile, makes the read-OUT DATA enable signal dout _ valid continue to be a high level of a system clock.

The control module 5 is used for performing read-write control on the data acquisition module 4 and controlling the digital three-dimensional mapping module 6, and a state machine is arranged in the control module. FIG. 2 is a state machine diagram of a control module of the present invention. As shown in fig. 2, the state machine of the control module 5 has four states, namely, an IDLE state, a PRE-trigger PRE _ TRIG state, a WAIT-trigger WAIT _ TRIG state, and a read data VALID _ RD state.

When the state machine works in an IDLE state, the DTO _ FIFO is in a reset state, the write enable signal wr _ en and the read enable signal rd _ en are both 0, the write data counter write _ count is set to 0, and the read data frame number counter count _ frame is set to 0. In the IDLE state, the read data valid signal dout _ valid is at a low level. When the control module 5 detects that the fast acquisition signal DTO _ Begin is equal to 1, and the DTO _ FIFO is reset, the control module 5 receives the PRE-trigger depth PRE _ depth and the waveform mapping frame number frame _ num from the upper computer 7, and the state machine enters the PRE-trigger PRE _ TRIG state.

When the state machine is operating in the PRE-trigger PRE _ TRIG state, the control block 5 asserts the write enable signal wr _ en high. According to the working process of the DATA acquisition module 4, when the write enable signal wr _ en and the DATA enable signal din _ valid are at high level, the DATA sequence DATA _ IN is written into the DTO _ FIFO. At this time, the state machine counts the data written into the DTO _ FIFO with a write data counter, write _ count, step value N. Assuming that N data are sent into the FPGA per system clock, the write data counter write _ count is write _ count + N. When the write data counter satisfies that write _ count is greater than or equal to pre _ depth, indicating that the pre-trigger depth is full, the state machine enters a WAIT for trigger WAIT _ TRIG state.

When the state machine is operating in the WAIT to trigger WAIT _ TRIG state, the control block 5 puts the read enable signal rd _ en high. According to the working process of the data acquisition module 4, when the read enable rd _ en and the data enable signal din _ valid of the DTO _ FIFO are at high levels, the DTO _ FIFO is in a state of reading while writing, and when the data enable signal din _ valid is at low levels, the DTO _ FIFO is in a state of neither reading nor writing. At this time, the state machine waits for the trigger signal Trig _ out to arrive, and the write data counter write _ count ≧ pre _ depth remains unchanged. When the trigger signal Trig _ out arrives, the state machine enters the read data state VALID _ RD.

When the state machine works in the read data state VALID _ RD, because the read enable signal RD _ en and the write enable signal wr _ en are both high level, when the data enable signal din _ VALID is high level, the DTO _ FIFO is always in the read-while-write state. In each system clock, N data points are written into the DTO _ FIFO, and a write data counter, write _ count + N, is written. When the write data counter write _ count is L +2N, indicating that one frame waveform has been completely written into the DTO _ FIFO, write _ count is set to 0 and then counting continues. And simultaneously reading out the data, and setting an output data point counter valid _ count to count the output one frame of waveform data points. When the DATA enable signal din _ valid is at a high level, the DATA point read OUT at this time is valid DATA of a frame waveform, the DATA acquisition module 4 firstly discards the previous N-pre _ depth% N + Addr DATA points, then every N DATA points are combined into DATA _ OUT to be sent to the digital three-dimensional mapping module, and meanwhile, the read DATA valid signal dout _ valid is set higher by one system period. When the output data point counter valid _ count is L +2N, it indicates that the waveform of one frame has been completely read out from the DTO _ FIFO, the read data frame counter count _ frame is count _ frame +1, and the output data point counter vaild _ count is set to 0 to prepare for the waveform output count of the next frame; if the data frame number counter count _ frame _ num is read from the DTO _ FIFO, it indicates that the waveform acquisition process is completed, sets the acquisition completion signal DTO _ done to 1, and the state machine enters an IDLE state; if the reading data frame number counter count _ frame < frame _ num, the state machine enters the WAIT for trigger WAIT _ TRIG state. It is found through research that when the output data point counter valid _ count is L +2N, the write data counter write _ count just satisfies that write _ count is greater than or equal to pre _ depth, and therefore the WAIT for trigger WAIT _ TRIG state can be directly returned.

The digital three-dimensional mapping module 6 is configured to read the DATA sequence DATA _ OUT from the DATA acquisition module 4 when the read DATA valid signal dout _ valid is high, and then convert the DATA sequence DATA _ OUT into a statistical value corresponding to each pixel point in the display module 8. Fig. 3 is a schematic diagram of a digital three-dimensional mapping module according to the present invention. As shown in FIG. 3, each RAM array has a memory bit width of A, typically 2^AFrame _ num + 1. RAM _1 is responsible for storing probability information of 0, N,2N, …, L-N columns, RAM _2 is responsible for storing probability information of 1, N +1,2N +1, …, L-N +1 columns, and so on, RAM _ N is responsible for storing probability information of N-1,2N-1,3N-1, …, L-1 columns, wherein each column corresponds to 2^MAn address. Taking RAM _1 as an example, in RAM _1, column 0 corresponds to column 2^MA memory address corresponding to 2 of the first column in the display module 8^MAnd (5) each pixel point. When the digital three-dimensional mapping module 6 determines that the read DATA valid signal dout _ valid is high, it indicates that the received read DATA _ OUT is valid, and the DATA _ OUT DATA bit width is M × Nbit, which indicates that each system clock corresponds to N DATA values, which are respectively denoted as DATA _ OUT _1, DATA _ OUT _2, …, and DATA _ OUT _ N. And taking the N data values as addresses, respectively reading out the data values in the corresponding addresses in the corresponding N RAM arrays, and writing the data values into the original addresses again after adding 1 to the data values. When the second DATA _ OUT DATA is valid, 2 is added to the N DATA values DATA _ OUT _1, DATA _ OUT _2, …, DATA _ OUT _ N^MAnd reading out the data values in the corresponding addresses in the corresponding N RAM arrays, and writing the data values back to the original addresses after adding 1 to the data values. By analogy, when the C-th valid DATA _ OUT arrives, the N DATA values DATA _ OUT _1, DATA _ OUT _2, …, DATA _ OUT _ N are added by (C-1) × 2^MAnd reading out the data values in the corresponding addresses in the corresponding N RAM arrays, and writing the data values back to the original addresses after adding 1 to the data values. When NC is L, the mapping process indicating one frame waveform is completed. The mapping process of the waveform adopts a pipeline operation, so that the data cannot be jammed. Due to the fact thatThis part is prior art and is not central to the present invention and will not be described in detail here.

The upper computer 7 is used for controlling the FPGA and receiving data, the upper computer 7 resets the data acquisition module 4, the control module 5 and the digital three-dimensional mapping module 6 before starting rapid acquisition, after the resetting is completed, the upper computer 7 sends a snapshot coefficient to the snapshot module 2, sends a pre-trigger depth pre _ depth and a waveform mapping frame number frame _ num to the control module 5, then sets a rapid acquisition signal DTO _ Begin to be 1, and tells the control module 5 to start waveform acquisition; after the mapping process of the waveform is completed, all probability data in the digital three-dimensional mapping module 6 are read to the upper computer, and each probability data is converted into an RGB value and sent to the display module 8. When the data acquisition needs to be stopped, the fast acquisition signal DTO _ Begin is set to 0, and the control module 5 is told to stop the acquisition of the waveform.

The display module 8 refreshes the waveform on the screen of the oscilloscope according to the RGB values received from the upper computer 7.

In the embodiment, the rapid acquisition system of the digital three-dimensional oscilloscope based on the FPGA is integrated in the existing digital three-dimensional oscilloscope, and the specific working flow is as follows:

step 1: after the user selects the data rapid acquisition mode, the upper computer 7 resets the data acquisition module 4, the control module 5 and the digital three-dimensional mapping module 6, after the resetting is completed, the upper computer 7 sends the pre-trigger depth pre _ depth 201 and the waveform mapping frame number frame _ num 255 to the module 5, the upper computer 7 sends the snapshot coefficient 1 to the snapshot module 2, and then the rapid acquisition signal DTO _ Begin is set to 1. In this embodiment, the resolution of the oscillographic area screen is 500 × 256, the number of waveform points L in one frame is 500, the resolution of the ADC is M8 bits, and the sampling rate f of the ADC is_sSystem clock f of 1.25GSPS, FPGA working_sys312.5MHz, so each operating clock corresponds to N4 samples of data.

And 2, packing and storing every 4 DATA points of the sampling DATA ADC _ DATA into a DTO _ FIFO in the DATA acquisition module 4, and enabling a DATA enable signal din _ valid to last for a high level of one system clock period. The depth D of the DTO _ FIFO is 127, and the bit width is M × N is 32 bits. The control module 5 performs read-write control on the DTO _ FIFO by using a state machine, and the specific process is as follows:

IDLE: DTO _ Begin is set to 1 and the state machine enters the PRE _ TRIG state.

PRE _ TRIG: the control module asserts the write enable signal wr _ en high and DATA _ IN is written into the DTO _ FIFO when the write enable signal wr _ en and the DATA enable signal din _ valid of the DTO _ FIFO are high. The write data counter write _ count + 4. When the write data counter write _ count is 204, the write _ count ≧ pre _ depth is satisfied, indicating that the pre-trigger depth is full, the state machine enters the WAIT _ TRIG state.

WAIT _ TRIG: the control module 5 sets the read enable signal rd _ en high, and when the read enable signal rd _ en and the data enable signal din _ valid of the DTO _ FIFO are high, the DTO _ FIFO is in a read-while-write state. At this time, the state machine waits for the trigger signal Trig _ out to arrive, and the write data counter write _ count 204 remains unchanged. When the trigger signal Trig _ out arrives, the state machine enters a VALID _ RD state, and meanwhile, the snapshot module sends a specific position Addr of the trigger point in the 4 data to the data acquisition module, assuming that Addr is 2.

VALID _ RD: since the read enable signal rd _ en and the write enable signal wr _ en are both high level, the DTO _ FIFO is always in a state of reading while writing when the data enable signal din _ valid is high level. In each system cycle, 4 data points are written into the DTO _ FIFO, and a data write counter write _ count +4 is written. When the write data counter write _ count 508 is satisfied, indicating that a frame waveform has been completely written into the DTO _ FIFO, the write data counter write _ count is set to 0 and continues counting. And simultaneously reading data, when the data enable signal din _ valid is at a high level, in each system cycle, 4 data points are read from the DTO _ FIFO, the output data point counter valid _ count is responsible for counting one frame of output waveform data points, and the output data point counter valid _ count is valid _ count + 4. When the DATA enable signal din _ valid is at a high level, the DATA point read OUT at this time is valid DATA of a frame waveform, the previous N-pre _ depth% N + Addr is lost as 5 DATA points, then every 4 DATA points are combined into DATA _ OUT to be sent to the digital three-dimensional mapping module, meanwhile, the read DATA valid signal dout _ valid is set higher by one system period, which indicates that the DATA read OUT at this time is valid DATA of a frame waveform, and the read DATA _ OUT and the read DATA valid signal dout _ valid are sent to the digital three-dimensional mapping module 6 to be mapped with the waveform. When valid _ count 508 indicates that a frame of waveform has been completely read out from the DTO _ FIFO, count _ frame +1, and the read data valid signals dout _ valid and vaild _ count are set to 0. At this time, if the waveform frame number count _ frame read from the DTO _ FIFO is frame _ num is 255, it indicates that the waveform acquisition process is completed, the acquisition completion signal DTO _ done is set to 1, and the state machine enters an IDLE state, as shown in fig. 4, where fig. 4 is actual test data captured by an ILA core in the FPGA during the waveform acquisition mapping process of the digital three-dimensional oscilloscope. If the waveform frame number participating in the mapping has not reached frame _ num, the state machine enters the WAIT _ TRIG state.

Step 3, the digital three-dimensional mapping module 6 comprises 4 RAM modules, RAM _1 is responsible for storing probability information of 0 th, 4 th, 8 th, … th and 496 th columns on the screen, RAM _2 is responsible for storing probability information of 1 st, 5 th, 9 th, … th and 497 th columns on the screen, RAM _3 is responsible for storing probability information of 2 nd, 6 th, 10 th, … th and 498 th columns on the screen, and RAM _4 is responsible for storing probability information of 3 rd, 7 th, 11 th, … th and 499 th columns on the screen. As shown in FIG. 3, each column corresponds to 2⁸The RAM stores 256 memory addresses, and the bit width A is 8 bits. When the read DATA valid signal dout _ valid is high, it indicates that the DATA _ OUT DATA coming in and going OUT at this time is valid. Assuming that 4-way DATA _ OUT _1 is 1, DATA _ OUT _2 is 2, DATA _ OUT _3 is 3, and DATA _ OUT _4 is 4, DATA at the 1 st address in RAM _1, DATA at the 2 nd address in RAM _2, DATA at the 3 rd address in RAM _3, and DATA at the 4 th address in RAM _4 are read OUT at the same time, and added with 1 and then written back to the original address, and count _ frame is 1. When the second valid DATA _ OUT DATA arrives, the 4-way DATA _ OUT _1 is 5, DATA _ OUT _2 is 6, DATA _ OUT _3 is 7, and DATA _ OUT _4 is 8, and then the 5+2 th DATA _ OUT _1 is simultaneously read OUT⁸Data in address, 6+2 th in RAM _2⁸Data in individual addresses, 7+2 in RAM _3⁸An addressData in (1), 8+2 th in RAM _4⁸The data in each address is read, added with 1, and then written back to the original address again, and count _ frame is 2. By analogy, when count _ frame _ num is 255, it indicates that the mapping process of the waveform has been completed.

And 4, after the mapping process of the waveform is completed, reading out the statistical value data in the digital three-dimensional mapping module 6 by the upper computer 7, converting the statistical value in the RAM address into an RGB value according to the table 1, finally sending the RGB value to the display module for displaying, resetting the data acquisition module 4, the control module 5 and the digital three-dimensional mapping module 6 again by the upper computer, and starting the next waveform acquisition and mapping process.

Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.

Claims

1. The utility model provides a digital three-dimensional oscilloscope quick acquisition system based on FPGA which characterized in that includes the ADC module, the snapshot module, trigger module, data acquisition module, control module, digital three-dimensional mapping module, host computer and display module, wherein the snapshot module, trigger module, data acquisition module, control module, digital three-dimensional mapping module realizes in FPGA, wherein: