CN109142835B - Data acquisition system with waveform multi-frame recording function - Google Patents
Data acquisition system with waveform multi-frame recording function Download PDFInfo
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- CN109142835B CN109142835B CN201810668113.7A CN201810668113A CN109142835B CN 109142835 B CN109142835 B CN 109142835B CN 201810668113 A CN201810668113 A CN 201810668113A CN 109142835 B CN109142835 B CN 109142835B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
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Abstract
The invention discloses a data acquisition system with waveform multi-frame recording function, which carries out multi-frame recording on the acquired data besides conventional acquisition, caching and display of the acquired data, and the specific method comprises the following steps: a user sets a plurality of trigger types, generates trigger signals, divides an external memory into a plurality of independent memory areas and distributes the independent memory areas to each trigger type; and writing the acquired data into a certain independent storage area, then performing triggering judgment and storage by using a corresponding triggering signal to obtain deep storage waveform data, and performing snapshot and display on the deep storage waveform data according to the computed snapshot coefficient. The invention deeply stores the data and stores the waveforms meeting the triggering parameters in a multi-frame and regional way, thereby facilitating the observation of waveform details by users.
Description
Technical Field
The invention belongs to the technical field of data acquisition systems, and particularly relates to a data acquisition system with a waveform multi-frame recording function.
Background
With the rapid development of modern electronic technology and information processing, the acquisition and display functions of modern test instruments are more and more diversified, especially, the digital oscilloscope with powerful functions can integrate the functions of waveform acquisition, a multimeter function, a signal generator, a frequency spectrograph and the like, the sampling rate and the bandwidth of the digital oscilloscope are rapidly increased, electric signals and physical signals in multiple fields can be measured and acquired, and a friendly man-machine interaction interface is provided for a user to observe waveform changes from multiple angles, but the digital oscilloscope still has the following defects in a data acquisition system:
(1) although the existing data acquisition system has a storage function with enough depth, continuous capture of a group of key events in long-time testing is lacked, for example, when a device continuously records a plurality of key events for a long time without monitoring, the requirement of a user cannot be met.
(2) Although the existing data acquisition system has a strong trigger function and can accurately capture any key event, the multidirectional combination of trigger types is lacked, the key event or a plurality of different key events can possibly occur repeatedly in a detected signal within a period of time, and the trigger types need to be combined to form a trigger array so as to capture variable abnormal events.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a data acquisition system with a waveform multi-frame recording function, which can deeply store data and perform multi-frame regional storage on waveforms meeting triggering parameters, so that a user can conveniently observe waveform details.
In order to achieve the above object, the data acquisition system with waveform multi-frame recording function of the present invention comprises an acquisition module, a central control module, a trigger module, a channel data selection module, a trend waveform snapshot module, a trend waveform cache module, a deep-storage waveform front-end cache and conversion module, a memory control module, a deep-storage waveform back-end cache and conversion module, a deep-storage waveform snapshot module, an external memory, an upper computer and a display screen, wherein the central control module, the trigger module, the channel data selection module, the trend waveform snapshot module, the trend waveform cache module, the deep-storage waveform front-end cache and conversion module, the memory control module, the deep-storage waveform back-end cache and conversion module and the deep-storage waveform snapshot module are implemented in an FPGA;
the acquisition module is used for gathering the data source, and the channel quantity of keeping the acquisition module is N, and the sampling rate is χ, sends the N data stream of gathering to the channel data selection module:
the central control module receives the channel serial number n sent by the upper computer, forwards the channel serial number n to the channel data selection module, and receives the trend waveform snapshot coefficient epsilon sent by the upper computer1The data is forwarded to a trend waveform snapshot module and receives a deep storage waveform snapshot coefficient epsilon sent by an upper computer2Forwarding to a deep storage waveform snapshot module, receiving a trend waveform write operation instruction sent by an upper computer, forwarding to a trend waveform cache module, and receiving the storage depth Q of a multi-frame record sent by the upper computer1And recording frame number phi corresponding to M, K trigger types of independent storage area numberkForwarding a deep storage waveform writing operation instruction and a deep storage waveform reading operation instruction to a memory control module, wherein the captured waveform writing operation instruction comprises a writing initial address, a pre-trigger depth predept and a post-trigger depth postdepth, and receiving K trigger parameters T of trigger types sent by an upper computerkForwarding to the triggering module; trend waveform Data read from trend waveform cache modulei2The deep storage waveform data is received from the memory control module, the full mark signal is transmitted to the upper computer, and the deep storage waveform data is received from the deep storage waveform snapshot module and transmitted to the upper computer;
the trigger module is used for receiving K trigger parameters T of trigger types forwarded by the central control modulekGenerating K corresponding trigger signals SigkSending the data to a memory control module;
the channel Data selection module receives the channel serial number n forwarded by the central control module, gates the channel n of the acquisition module, receives the Data acquired by the channel Data selection module and sends the Data to the trend waveform snapshot module and the deep storage waveform front-end cache and conversion module;
trend waveform snapshot module receptionTrend waveform snapshot coefficient epsilon sent by central control module1Sampling the collected Data to obtain main waveform Datai1Sending the trend waveform to a trend waveform cache module;
the trend waveform cache module receives the main waveform Data after receiving the trend waveform write operation instructioni1Caching;
the deep storage waveform front end caching and converting module is used for receiving the acquired Data for caching, converting the Data into a clock of an external memory, and converting the converted Dataj1Output to the memory control module;
the memory control module is used for performing write operation control and read operation control on an external memory, and comprises the following specific contents:
the memory control module receives the deep stored waveform writing operation signal forwarded by the central control module and the storage depth Q recorded by multiple frames1And recording frame number phi corresponding to M, K trigger types of independent storage area numberkCalculating the address range lambda of each independent storage area according to the writing initial address and the number M of the independent storage areasm(ii) a The memory control module receives the recording frame number phi corresponding to the K trigger types forwarded by the central control modulekAssign phi to the kth trigger typekA separate storage area;
the memory control module receives K trigger signals Sig from the trigger modulekEach trigger signal is sequentially selected to trigger and store the deep storage waveform, and the specific process is as follows:
1) making the sequence number r of the independent storage area of the kth trigger type equal to 1;
2) data read from deep storage waveform front end buffer and conversion modulej1Data of Dataj1Circularly writing the data into the corresponding r independent storage area of the k trigger type and according to the k trigger signal SigkPerforming trigger judgment, if not, doing nothing, if triggered, locking the trigger address tri _ addrk,rContinuously writing postdepth data into the external memory and then sending a kth trigger type kth frame to the central control moduleA deep storage data full flag signal; if the trigger is not realized within the preset time T, the current address is latched as the trigger address tri _ addrk,rContinuously writing postdepth data into the external memory, and then sending a kth trigger type nth frame deep storage data full flag signal to the central control module;
3) if r < phikIf so, making r equal to r +1, returning to the step 2), otherwise, selecting the next trigger signal;
the storage control module receives a deep storage waveform reading operation signal forwarded by the central control module, and sequentially calculates a read start address begin _ addr of the kth trigger type nth frame deep storage data in the external memory to be tri _ addrk,r-predepth, reading α from the corresponding independent storage area starting from the read start address2Data of will phi1+φ2+...+φNData composed of frame depth storage waveform Dataj2Sending the waveform to a deep storage waveform rear-end caching and converting module;
the deep storage waveform back end cache and conversion module is used for Dataj2Buffering, converting to FIFO read clock, and converting the Dataj3Outputting the data to a deep storage waveform snapshot module;
the deep storage waveform snapshot module receives a deep storage waveform snapshot coefficient epsilon sent by the central control module2For Dataj3Performing snapshot to obtain Dataj4Sending the data to a central control module;
the external memory is used for storing deep storage waveform data;
the host computer calculates the parameter of each module according to the parameter that the user set up, sets up each module through central control module to handle the data that receive, specifically include:
1) receiving storage depth Q of multi-frame record set by user1Dividing the external memory into multiple frames, where L is the recording length of each frame and W is the bit width of each data point
A plurality of mutually independent memory areas, wherein Q is the memory capacity of the external memory,
represents rounding down, M is 1,2, …, M;
2) receiving trigger parameters T of trigger types set by userskAnd the recording frame number phi corresponding to each trigger typekK is 1,2, …, K indicates the number of trigger types, and needs to satisfy phi1+φ2+...+φN≤M；
3) The upper computer receives a channel selection sequence number n and a slow time base gear T input by a useriAnd fast time base gear TjCalculating the coefficient epsilon of the snapshot of the trend waveform1And deep storage waveform snapshot coefficient epsilon2Wherein the coefficient of snapshot of the trend waveform is ε1The calculation formula of (a) is as follows:
α represents a data point required by the display screen to display a frame of main waveform, β represents the number of grids for the display screen to display the main waveform;
deep storage waveform snapshot coefficient epsilon2The calculation method of (2) is as follows:
solving according to the following formula to obtain the applicable equivalent sampling rate χ2And the number of sample points α2The combination of (A) and (B):
χ2＝α2/(β*Tj)
s.t.χ2≤χ,α2＜Q1
at an applicable equivalent sampling rate χ according to requirements2And the number of sample points α2Is selected and then the deep storage waveform snapshot coefficient epsilon is calculated2＝χ/χ2；
The upper computer selects the channel serial number n and the calculated trend waveform snapshot coefficient epsilon1And deep storage waveform snapshot coefficient epsilon2Storage depth Q of multi-frame recording1M, K trigger types for independent storage area numberTrigger parameter T ofkAnd the recording frame number phi corresponding to the K trigger typeskSending the trend waveform writing operation signal and the deep storage waveform writing operation signal to the central control module, wherein the deep storage waveform writing operation signal comprises a writing initial address, a pre-trigger depth predeth and a post-trigger depth postdepth, and the predeth + postdepth is α2；
When the upper computer receives one-screen trend waveform data forwarded by the central control module, the trend waveform data is sent to the display screen to be displayed; whenever the upper computer receives the phi forwarded by the central control module1+φ2+...+φKAfter the storage waveform is written with the mark signal, the storage waveform is sent to the central control module to read the operation signal, and the phi fed back by the central control module is received1+φ2+...+φKStoring waveform data frame by frame depth, then sending the waveform data frame by frame to a display screen for displaying, or else, not performing any operation;
the display screen is used for displaying the received trend waveform data and the deep storage waveform data.
The invention discloses a data acquisition system with waveform multi-frame recording function, which carries out multi-frame recording on the acquired data besides conventional acquisition, caching and display of the acquired data, and comprises the following specific steps: a user sets a plurality of trigger types, generates trigger signals, divides an external memory into a plurality of independent memory areas and distributes the independent memory areas to each trigger type; and writing the acquired data into a certain independent storage area, then performing triggering judgment and storage by using a corresponding triggering signal to obtain deep storage waveform data, and performing snapshot and display on the deep storage waveform data according to the computed snapshot coefficient.
The invention has the following technical effects:
1) the method supports the user to preset the trigger type and the recording frame number of each type, and the data acquisition system can automatically and continuously record the key event with the trigger condition after the trigger type and the recording frame number are set, so that the key event which the user wants to capture cannot be missed in a continuous time period, and the recording is strictly carried out according to the trigger type queue preset by the user;
2) the method and the device facilitate a user to observe the general view of the waveform through the real-time display of the trend waveform, and facilitate the user to observe the details of the waveform through the display of the deeply stored waveform data;
3) the invention can capture abnormal events for a long time in a long-term unattended use scene, can realize that a user remotely sets the trigger type to start the data acquisition system by simple setting, and sets that the trigger time is recorded when each trigger is carried out, thereby realizing the recording of days or weeks of a data source, and the user can extract data for analysis according to the trigger time after the recording is finished.
Drawings
FIG. 1 is a block diagram of an embodiment of a data acquisition system with waveform multi-frame recording function according to the present invention;
fig. 2 is a schematic diagram of the division of the external memory in the present embodiment.
Detailed Description
The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.
Examples
Fig. 1 is a structural diagram of a data acquisition system with a waveform multi-frame recording function according to an embodiment of the present invention. As shown in fig. 1, the data acquisition system with waveform multi-frame recording function of the present invention comprises an acquisition module 1, a central control module 2, a trigger module 3, a channel data selection module 4, a trend waveform snapshot module 5, a trend waveform cache module 6, a deep storage waveform front end cache and conversion module 7, a memory control module 8, a deep storage waveform back end cache and conversion module 9, a deep storage waveform snapshot module 10, an external memory 11, an upper computer 12, and a display screen 13, the central control module 2, the trigger module 3, the channel data selection module 4, the trend waveform snapshot module 5, the trend waveform cache module 6, the deep-stored waveform front-end cache and conversion module 7, the memory control module 8, the deep-stored waveform back-end cache and conversion module 9, and the deep-stored waveform snapshot module 10 are implemented in an FPGA (Field-Programmable Gate Array).
The acquisition module 1 is used for acquiring a data source, recording the number of channels of the acquisition module 1 as N and the sampling rate as χ, and transmitting the acquired N paths of data streams to the channel data selection module 4. In this embodiment, the acquisition module 1 adopts 128 channels of ADC acquisition boards, the data bit width is 16bit, and the sampling rate is 100 MS/s.
The central control module 2 is used for transferring control information and data between the upper computer 12 and other modules, and comprises:
receiving the channel serial number n sent by the upper computer 12, forwarding the channel serial number n to the channel data selection module 4, and receiving the trend waveform snapshot coefficient epsilon sent by the upper computer 121The data is forwarded to a trend waveform snapshot module 5, and a deep storage waveform snapshot coefficient epsilon sent by an upper computer 12 is received2The data are forwarded to a deep storage waveform snapshot module 10, trend waveform write operation instructions sent by an upper computer 12 are received and forwarded to a trend waveform cache module 6, and the storage depth Q of multi-frame records sent by the upper computer 12 is received1And recording frame number phi corresponding to M, K trigger types of independent storage area numberkThe deep storage waveform writing operation instruction and the deep storage waveform reading operation instruction are forwarded to the memory control module 8, wherein the captured waveform writing operation instruction comprises a writing initial address, a pre-trigger depth predept and a post-trigger depth postdepth, and K trigger type trigger parameters T sent by the upper computer 12 are receivedkForwarding to the trigger module 3;
trend waveform Data is read from trend waveform cache module 6i2And the signals are transmitted to the upper computer 12, the deep storage waveform data full flag signals are received from the memory control module 8 and are transmitted to the upper computer 12, and the deep storage waveform data are received from the deep storage waveform snapshot module 10 and are transmitted to the upper computer 12.
The trigger module 3 is used for receiving K trigger parameters T of trigger types forwarded by the central control module 2kGenerating K corresponding trigger signals SigkTo the memory control module 8.
The channel Data selection module 4 receives the channel serial number n forwarded by the central control module 2, gates the channel n of the acquisition module 1, receives the Data acquired by the channel Data selection module and sends the Data to the trend waveform snapshot module 5 and the deep storage waveform front-end cache and conversion module 7.
The trend waveform snapshot module 5 receives the trend waveform snapshot coefficient epsilon sent by the central control module 21Sampling points are carried out on the collected Data to obtain trend waveform Datai1To the trend waveform buffer module 6.
The trend waveform caching module 6 receives trend waveform Data after receiving a trend waveform writing operation instructioni1And carrying out caching. In the invention, the trend waveform is sampled, stored and displayed in a rolling mode working under a slow time base, and a module capable of writing and reading at the same time is required to buffer the waveform, so the trend waveform buffer module 6 is realized by adopting FIFO (first in first out) in an FPGA (field programmable gate array). Setting the Data read-write bit width as W, wherein W is the bit width of Data, and setting the storage depth of FIFO under the condition of saving resources.
The deep storage waveform front end caching and converting module 7 is used for receiving the collected Data for caching, converting the Data into a clock of an external memory, and converting the converted Dataj1Output to the memory control module 8. Similarly, the deep storage waveform cache module is also realized by adopting FIFO inside the FPGA, the read-write bit width is set to be W, and the storage depth of the FIFO is set by taking the least logic resource as a rule. The read port clock of the FIFO is connected to the synchronous clock for collecting Data, which is 100Mhz in this embodiment, and the write port clock of the FIFO is connected to the user clock of the external memory, which is 200Mhz in this embodiment, so as to implement the cross-clock domain conversion from Data to the external memory.
The memory control module 8 is configured to perform write operation control and read operation control on the external memory 11, and includes the following specific contents:
the memory control module 8 receives the deep stored waveform writing operation signal forwarded by the central control module 2 and the storage depth Q recorded by multiple frames1And recording frame number phi corresponding to M, K trigger types of independent storage area numberkAccording to the write initial address and the number of independent storage areasM is calculated to obtain the address range lambda of each independent storage area in the external memory 11m. Fig. 2 is a schematic diagram of the division of the external memory in the present embodiment. As shown in fig. 2, in this embodiment, a continuous allocation mode is adopted, and if an initial address is written as a, an address range λ of an m-th independent storage areamIs [ A + (m-1) Q1,A+mQ1]. The memory control module 8 receives the recording frame number phi corresponding to the K trigger types forwarded by the central control module 2kAssign phi to the kth trigger typekA separate storage area.
The memory control module 8 receives K trigger signals Sig from the trigger module 3kEach trigger signal is sequentially selected to trigger and store the deep storage waveform, and the specific process is as follows:
1) let the independent storage area sequence number r of the kth trigger type be 1.
2) Data read from deep storage waveform front end buffer and conversion module 7j1Data of Dataj1Circularly writing the data into the corresponding r independent storage area of the k trigger type and according to the k trigger signal SigkPerforming trigger judgment, if not, doing nothing, if triggered, locking the trigger address tri _ addrk,rContinuously writing postdepth data into the external memory, and then sending a kth trigger type nth frame deep storage data full flag signal to the central control module 2; if the trigger is not realized within the preset time T, the current address is latched as the trigger address tri _ addrk,rAnd continuously writing postdepth data into the external memory, and then sending a kth trigger type nth frame deep storage data full flag signal to the central control module 2. That is, if the kth trigger type does not implement a trigger in the current data, it is sufficient to store the current data when the time expires.
3) If r < phikAnd if the trigger signal is not the trigger signal, the step 2) is returned to, and if the trigger signal is not the trigger signal, the next trigger signal is selected.
The storage control module receives the deep storage waveform read operation signal forwarded by the central control module 2, sequentially calculates the kth trigger type tth frame deep storage data and stores the kth trigger type tth frame deep storage data outsideThe read start address begin _ addr of the device 11 is tri _ addrk,r-predepth, reading α from the corresponding independent storage area starting from the read start address2Data of will phi1+φ2+...+φNData composed of frame depth storage waveform Dataj2And sending to a deep storage waveform back-end buffer and conversion module 9.
The deep storage waveform back end buffer and conversion module 9 is used for Dataj2Buffering, converting to FIFO read clock, and converting the Dataj3And outputs to the deep stored waveform snapshot module 10. Similarly, the deep storage waveform back-end cache and conversion module 9 is also implemented by using an FIFO inside the FPGA, and sets the read-write bit width to be epsilon, and sets the storage depth of the FIFO using the least occupied logic resource as a rule. FIFO read port clock is connected with user clock of memory, FIFO write port clock is connected with Dataj2To implement a cross-clock domain conversion of the external memory 11 to the FPGA internal data.
The deep storage waveform snapshot module 10 receives the deep storage waveform snapshot coefficient epsilon sent by the central control module 22For Dataj3Performing snapshot to obtain Dataj4To the central control module 2.
The external memory 11 is used to store deep-stored waveform data.
The upper computer 12 calculates parameters of each module according to parameters set by a user, sets each module through the central control module 2, processes and displays received data, and specifically comprises:
1) the upper computer 12 receives the storage depth Q of the multi-frame record set by the user1L is the recording length (unit: points) of each frame when recording multiple frames, W is the bit width of each data point, and the external memory 11 is divided into
A mutually independent memory area, where Q is the memory capacity of the external memory 11,
meaning rounded down, M is 1,2, …, M.
2) The upper computer 12 receives the trigger type T set by the userkAnd the recording frame number phi corresponding to each trigger typekK is 1,2, …, K indicates the number of trigger types, and needs to satisfy phi1+φ2+...+φN≤M。
3) The upper computer 12 receives the channel selection serial number n and the slow time base gear T input by the useriAnd fast time base gear TjCalculating a trend waveform snapshot coefficient and a captured waveform snapshot coefficient, wherein the calculation methods are respectively as follows:
coefficient of trend waveform snapshot
The display screen 13 needs α data points for displaying a frame of trend waveform, and the total number of data points is β, so that the sampling time of a frame of trend waveform is β × TiThe time interval between two points on the display screen 13 is t1＝(β*Ti) /α, display sampling rate of trend waveform as chi1＝[α/(β*Ti)]That is, when the selected value of the time base gear cannot be divided by the integer, χ is selected1Is an approximate integer value, thereby calculating the trend waveform snapshot coefficient under the current time base gear
In this embodiment, a waveform of one frame of the display screen 13 requires 1000 data points, 10 data points in total, and 100 data points in each data point, so that the maximum storage depth is set to 1 kpts. Assuming that the slow time base gear set by the user is 200ms/div, the two-point time interval t of the display 131Sample rate χ is shown (200ms by 10)/1000 ms by 2ms11/2 ms-500S/S, so as to calculate the trend waveform snapshot coefficient epsilon1＝100M/500＝2×105。
Deep-stored waveform snapshot coefficient
Recording the storage depth of the external memory 11 as delta, wherein delta > α, the sampling rate chi of the acquisition module 1 is the upper limit of the sampling rate of the captured waveform, therefore, in the invention, the fast time-base gear T is calculatedjThe following equivalent sampling rate and number of sampling points must guarantee two conditions:
(a) not exceeding χ tries to ensure that the higher the equivalent sampling rate, the better.
(b) Number of guaranteed samples α2Less than the current storage depth delta.
Due to the equivalent sampling rate χ2And the number of sample points α2Has a relation of2＝α2/(β*Tj)α2＝χ2*β*TjTherefore, the applicable equivalent sampling rate χ is obtained by solving the following formula2And the number of sample points α2The combination of (A) and (B):
χ2＝α2/(β*Tj)
s.t.χ2≤χ,α2＜δ
at an applicable equivalent sampling rate χ according to requirements2And the number of sample points α2In which a group is selected, generally preference is given to the equivalent sampling rate χ2The largest combination. Then calculating the snapshot coefficient epsilon of the deep storage waveform2＝χ/χ2。
Assuming that 100M is the highest sampling rate, the equivalent sampling rate χ is determined firstly under the condition of 100kpts of storage depth and 10 mus/div of time base2Is 100MS/s, the number of sampling points is calculated to be α2The deep stored waveform snapshot coefficient ε is calculated by (10 μ s 10) 100M 10kpts2100M/100M 1, i.e. no snapshot; for example, under the conditions of 100kpts of storage depth and 500 mus/div of time base, the maximum sampling rate 100M is used as the equivalent sampling rate χ2Then the number of sampling points is α2The number of sampling points is determined to be 100kpts, and the equivalent sampling rate χ is calculated, because (500 mus 10) 100M 500kpts is larger than the current storage depth 100kpts2100k/(500 mus 10) 20MS/s, and the deep-stored-waveform snapshot coefficient e is calculated2＝100M/20M＝5。
The upper computer 12 selects the channel selection serial number n and the calculated trend waveform snapshot coefficient epsilon1And deep storage waveform snapshot coefficient epsilon2Storage depth Q of multi-frame recording1M, K trigger types T of independent storage area numberkAnd the recording frame number phi corresponding to the K trigger typeskSends the trend waveform to the central control module 2 and sends the trend waveform to the central control module 2A write operation signal and a deep storage waveform write operation signal, the deep storage waveform write operation signal including a write initial address, a pre-trigger depth predeth and a post-trigger depth postdepth, wherein the pre + postdepth is α2In general, to locate the data corresponding to the trigger address in the captured waveform in the middle of the display 13, let predpth be α2/2。
Each current upper computer 12 receives one screen of trend waveform data transmitted by the central control module 2, namely α1Trend waveform data, α1The number of sampling points representing the trend waveform is sent to the display 13 for display. Every time the upper computer 12 receives phi forwarded by the central control module 21+φ2+...+φNAfter the storage waveform is written with the mark signal, a deep storage waveform reading operation signal is sent to the central control module 2, and phi fed back by the central control module 2 is received1+φ2+...+φNThe waveform data is stored frame-deeply and then sent to the display screen 13 frame by frame for display, otherwise, no operation is performed.
The display 13 is used to display the received trend waveform data and the deep stored waveform data. Generally, the display 13 performs sampling according to the number of sampling points and the number of display points before displaying the trend waveform data and the deep-stored waveform data.
In order to better explain the technical scheme of the invention, the working flow of the oscillograph recorder with the waveform multi-frame recording function is briefly explained.
The upper computer 12 calculates a snapshot coefficient according to a time base set by a user, and then sends the snapshot coefficient to the trend waveform snapshot module 5 and the deep storage waveform snapshot module 10 through the controller, the acquisition module 1 then performs signal acquisition, and the channel data selection module sends the serial number of the corresponding channel to the trend waveform snapshot module 5 and the deep storage waveform front-end cache and conversion module 7 according to the channel serial number set in the upper computer 12. The trend waveform snapshot module 5 performs snapshot according to the snapshot coefficient, caches the snapshot to the trend waveform cache module 6, and the trend waveform cache module is read by the central control module 2 and sent to the upper computer 12 for continuous display. The deep storage waveform front end caching and converting module 7 is used for caching the collected data.
The trigger module 3 generates K trigger signals according to K trigger parameters of trigger types set in the upper computer 12 by a user and sends the K trigger signals to the memory control module 8. The memory control module 8 divides the external memory 11 into a plurality of independent memory areas according to parameters set by a user on the upper computer, and allocates the independent memory areas to different trigger types. And then reading the acquired data from the front-end cache and conversion module 7 of the deep storage waveform, triggering by adopting trigger signals corresponding to K trigger types, storing the triggered deep storage waveform data into a corresponding independent storage area, and sending a deep storage waveform full-writing mark signal to an upper computer after the deep storage waveform data is stored fully.
The upper computer 12 reads the trend waveform data for continuous display. Then every time the upper computer 12 receives the phi forwarded by the central control module 21+φ2+...+φNAfter the storage waveform is written with the full mark signal, the central control module 2 issues a deep storage waveform read operation signal to read phi from the external memory 111+φ2+...+φNThe frame deep storage waveform data is subjected to cache and clock conversion through a deep storage waveform rear-end cache and conversion module 9, then is subjected to snapshot through a deep storage waveform snapshot module 10, is fed back to an upper computer through a central control module 2, and is sent to a display screen 13 for display.
Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.
Claims (3)
1. A data acquisition system with a waveform multi-frame recording function is characterized by comprising an acquisition module, a central control module, a trigger module, a channel data selection module, a trend waveform snapshot module, a trend waveform cache module, a deep storage waveform front-end cache and conversion module, a memory control module, a deep storage waveform rear-end cache and conversion module, a deep storage waveform snapshot module, an external memory, an upper computer and a display screen, wherein the central control module, the trigger module, the channel data selection module, the trend waveform snapshot module, the trend waveform cache module, the deep storage waveform front-end cache and conversion module, the memory control module, the deep storage waveform rear-end cache and conversion module and the deep storage waveform snapshot module are realized in an FPGA;
the acquisition module is used for gathering the data source, and the channel quantity of keeping the acquisition module is N, and the sampling rate is χ, sends the N data stream of gathering to the channel data selection module:
the central control module receives the channel serial number n sent by the upper computer, forwards the channel serial number n to the channel data selection module, and receives the trend waveform snapshot coefficient epsilon sent by the upper computer1The data is forwarded to a trend waveform snapshot module and receives a deep storage waveform snapshot coefficient epsilon sent by an upper computer2Forwarding to a deep storage waveform snapshot module, receiving a trend waveform write operation instruction sent by an upper computer, forwarding to a trend waveform cache module, and receiving the storage depth Q of a multi-frame record sent by the upper computer1And recording frame number phi corresponding to M, K trigger types of independent storage area numberkForwarding a deep storage waveform writing operation instruction and a deep storage waveform reading operation instruction to a memory control module, wherein the captured waveform writing operation instruction comprises a writing initial address, a pre-trigger depth predept and a post-trigger depth postdepth, and receiving K trigger parameters T of trigger types sent by an upper computerkForwarding to the triggering module; trend waveform Data read from trend waveform cache modulei2The deep storage waveform data is received from the memory control module, the full mark signal is transmitted to the upper computer, and the deep storage waveform data is received from the deep storage waveform snapshot module and transmitted to the upper computer;
the trigger module is used for receiving K trigger parameters T of trigger types forwarded by the central control modulekGenerating K corresponding trigger signals SigkSending the data to a memory control module;
the channel Data selection module receives the channel serial number n forwarded by the central control module, gates the channel n of the acquisition module, receives the Data acquired by the channel Data selection module and sends the Data to the trend waveform snapshot module and the deep storage waveform front-end cache and conversion module;
the trend waveform snapshot module receives a trend waveform snapshot coefficient epsilon sent by the central control module1Sampling the collected Data to obtain main waveform Datai1Sending the trend waveform to a trend waveform cache module;
the trend waveform cache module receives the main waveform Data after receiving the trend waveform write operation instructioni1Caching;
the deep storage waveform front end caching and converting module is used for receiving the acquired Data for caching, converting the Data into a clock of an external memory, and converting the converted Dataj1Output to the memory control module;
the memory control module is used for performing write operation control and read operation control on an external memory, and comprises the following specific contents:
the memory control module receives the deep stored waveform writing operation signal forwarded by the central control module and the storage depth Q recorded by multiple frames1And recording frame number phi corresponding to M, K trigger types of independent storage area numberkCalculating the address range lambda of each independent storage area according to the writing initial address and the number M of the independent storage areasm(ii) a The memory control module receives the recording frame number phi corresponding to the K trigger types forwarded by the central control modulekAssign phi to the kth trigger typekA separate storage area;
the memory control module receives K trigger signals Sig from the trigger modulekEach trigger signal is sequentially selected to trigger and store the deep storage waveform, and the specific process is as follows:
1) making the sequence number r of the independent storage area of the kth trigger type equal to 1;
2) data read from deep storage waveform front end buffer and conversion modulej1Data of Dataj1Circularly writing the data into the corresponding r independent storage area of the k trigger type and according to the k trigger signal SigkPerforming trigger judgment, and if not, not performing any operationIf triggered, the trigger address tri _ addr is latchedk,rContinuously writing postdepth data into the external memory, and then sending a kth trigger type nth frame deep storage data full flag signal to the central control module; if the trigger is not realized within the preset time T, the current address is latched as the trigger address tri _ addrk,rContinuously writing postdepth data into the external memory, and then sending a kth trigger type nth frame deep storage data full flag signal to the central control module;
3) if r < phikIf so, making r equal to r +1, returning to the step 2), otherwise, selecting the next trigger signal;
the storage control module receives a deep storage waveform reading operation signal forwarded by the central control module, and sequentially calculates a read start address begin _ addr of the kth trigger type nth frame deep storage data in the external memory to be tri _ addrk,r-predepth, reading α from the corresponding independent storage area starting from the read start address2Data of will phi1+φ2+...+φNData composed of frame depth storage waveform Dataj2Sending the waveform to a deep storage waveform rear-end caching and converting module;
the deep storage waveform back end cache and conversion module is used for Dataj2Buffering, converting to FIFO read clock, and converting the Dataj3Outputting the data to a deep storage waveform snapshot module;
the deep storage waveform snapshot module receives a deep storage waveform snapshot coefficient epsilon sent by the central control module2For Dataj3Performing snapshot to obtain Dataj4Sending the data to a central control module;
the external memory is used for storing deep storage waveform data;
the host computer calculates the parameter of each module according to the parameter that the user set up, sets up each module through central control module to handle the data that receive, specifically include:
1) receiving storage depth Q of multi-frame record set by user1L is the recording length of each frame in multi-frame recording, and W is the bit width of each data pointDividing the external memory into
A plurality of mutually independent memory areas, wherein Q is the memory capacity of the external memory,
represents rounding down, M is 1,2, …, M;
2) receiving trigger parameters T of trigger types set by userskAnd the recording frame number phi corresponding to each trigger typekK is 1,2, …, K indicates the number of trigger types, and needs to satisfy phi1+φ2+...+φN≤M；
3) The upper computer receives a channel selection sequence number n and a slow time base gear T input by a useriAnd fast time base gear TjCalculating the coefficient epsilon of the snapshot of the trend waveform1And deep storage waveform snapshot coefficient epsilon2Wherein the coefficient of snapshot of the trend waveform is ε1The calculation formula of (a) is as follows:
α represents a data point required by the display screen to display a frame of main waveform, β represents the number of grids for the display screen to display the main waveform;
deep storage waveform snapshot coefficient epsilon2The calculation method of (2) is as follows:
solving according to the following formula to obtain the applicable equivalent sampling rate χ2And the number of sample points α2The combination of (A) and (B):
χ2＝α2/(β*Tj)
s.t.χ2≤χ,α2＜Q1
at an applicable equivalent sampling rate χ according to requirements2And the number of sample points α2Is selected and then the snapshot coefficient epsilon of the captured waveform is calculated2＝χ/χ2；
The upper computer calculates the channel selection serial number nCoefficient epsilon of trend waveform snapshot1And deep storage waveform snapshot coefficient epsilon2Storage depth Q of multi-frame recording1M, K trigger type trigger parameters T of independent storage area numberkAnd the recording frame number phi corresponding to the K trigger typeskSending the trend waveform writing operation signal and the deep storage waveform writing operation signal to the central control module, wherein the deep storage waveform writing operation signal comprises a writing initial address, a pre-trigger depth predeth and a post-trigger depth postdepth, and the predeth + postdepth is α2；
When the upper computer receives one-screen trend waveform data forwarded by the central control module, the trend waveform data is sent to the display screen to be displayed; whenever the upper computer receives the phi forwarded by the central control module1+φ2+...+φKAfter the storage waveform is written with the mark signal, the storage waveform is sent to the central control module to read the operation signal, and the phi fed back by the central control module is received1+φ2+...+φKStoring waveform data frame by frame depth, then sending the waveform data frame by frame to a display screen for displaying, or else, not performing any operation;
the display screen is used for displaying the received trend waveform data and the deep storage waveform data.
2. The data acquisition system as claimed in claim 1, wherein at the applicable equivalent sampling rate χ2And the number of sample points α2Selecting an equivalent sampling rate χ in the combination of2The largest combination.
3. The data acquisition system as set forth in claim 1, wherein said pre-trigger depth is α2/2。
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