CN100529766C - Equivalent sampling device - Google Patents
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- CN100529766C CN100529766C CNB2007100502652A CN200710050265A CN100529766C CN 100529766 C CN100529766 C CN 100529766C CN B2007100502652 A CNB2007100502652 A CN B2007100502652A CN 200710050265 A CN200710050265 A CN 200710050265A CN 100529766 C CN100529766 C CN 100529766C
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Abstract
The present invention discloses an equivalent sampling device. A delay adjusting module outputs a sampling clock and a synchronous clock. The phase of the sampling clock can change accurately within a certain range, and a single change can collect a group of data. A certain phase relationship exists between the synchronous clock and the sampling clock. The synchronous module synchronizes and outputs the tested input signal and the synchronous clock to a collecting module, and collects data under the control of the sampling clock. A route of triggering signal is outputted to a triggering module through a triggering passage, the triggering module outputs the triggering signal to ensure the delay adjusting module to trigger for one time for a time of data collecting. Since the sampling can be independent of the triggering, the interval between the sample times is a known period, when the triggering comes, the interior of the triggering module can sample continuously, and the triggering depth can be preset for observing the signal before being triggered. At the same time, using the delay method to change the phase can change the sampling interval of the sampling clock, and the circuit is easy and simple.
Description
Technical field
The present invention relates to the sampling apparatus of in a kind of data acquisition equipment waveform being sampled, specifically, relate to the equivalent sampling device of in a kind of high-speed data acquisition the periodicity emphasis complex signal being sampled.
Background technology
In the prior art, the high-speed sampling of waveform there are two kinds of common implementations: real-time sampling and equivalent sampling.
In the real-time sampling, sampled point all is to gather according to a fixing order.The order of this waveform sampling is identical with the order that sampled point occurs on the oscillograph screen.As long as a trigger event just can start whole collection actions.In a lot of application scenarios, the temporal resolution that the real-time sampling mode is provided still can not satisfy the requirement of work, and in these application scenarios, the signal that observe usually is repeated, and promptly identical signal graph repeatedly occurred by the well-regulated time interval.
For these signals, many groups sampled point that oscillograph can collect from the signal period of plurality of continuous constitutes waveform, and first group of new sampled point all is to start collection by a new trigger event, and this is called equivalent time sampling.Under this pattern, after a trigger event arrived, oscillograph was for example gathered five sampled points and is deposited them in storer with regard to the part of acquired signal waveform.Another trigger event then is used for gathering five other sampled points, and it is stored in the diverse location of same storer, so go on through after the several times trigger event, enough sampled points of store memory storage, just can on screen, rebuild a complete waveform, equivalent time sampling makes oscillograph provide very high time separation rate under the Gao Shiji value of setting, so, just look like that oscillograph has had than the much higher virtual sampling rate of its actual sampling rate or claims equivalent time sampling speed.
Equivalent time sampling speed is a kind of round-about way of expression oscillograph horizontal resolution under Gao Shiji is provided with.If it shows that also the method for using real-time sampling will obtain the needed sampling rate of identical temporal resolution, the real-time sampling speed that the equivalent time sampling speed ratio can reach now is much higher.Simultaneously, adopt Equivalent Sampling Technology then can realize the product that the sampling rate index is very high with low cost, than the product of real-time sampling, except observing the transient signal, others are no less than the product of real-time sampling.
In the prior art, adopt two kinds of different technology to realize equivalent time sampling, i.e. sequential sampling and stochastic sampling.
1, sequential sampling
As shown in Figure 1, when adopting sequential sampling, the collection of sampled point is to be undertaken by a fixing order, i.e. gathering from left to right on screen, everyly come a new trigger event just to gather a sampled point, in order to fill up a complete waveform recording, there are what memory locations just to need what trigger events in the record.
And, after first trigger event arrives, just gather first sampled point immediately, and deposit it in storer.Second trigger event then is used for a super moving timing system, this timing system will produce a very little time delay Δ t, after time delay through this Δ t, gather second sampled point again, temporal resolution in the trace storer just equals this little Δ t time delay, and its value may be less than 50ps.After the 3rd trigger event arrived, this timing system then produced the time delay of 2 Δ t.Later gather the 3rd sampling again this time delay, and go on like this.
The collection of n new sampled point is to carry out after the time that has postponed (n-1) Δ t with respect to similar trigger event in other words.Consequently the waveform that shows on the oscillograph is made of the sampled point that occurs by definite sequence.Be the Far Left of first sampled point at screen, then each sampled point constitutes display waveform successively to the right.
Under the sequential sampling pattern, gather the periodicity of waveform, promptly the trigger event number equals the record length of storer.Sequential sampling can be realized back trigger delay function, but pre-trigger message can not be provided, and can not observe the signal before triggering, and is unfavorable for the analysis of signal.
2, stochastic sampling
As shown in Figure 2, in the oscillograph that uses stochastic sampling, first group of sampled point is to gather in the moment at random, and it is irrelevant with trigger event, between these sampled points the time be spaced apart the known time, determine by sampling clock, when oscillograph when waiting for that trigger event arrives, it is inner just in continuous sampling and the result is stored.A timing system when a trigger event arrives in the oscillograph just begins to adopt a moment up to the next one constantly from this and carries out time measurement.Because sampling interval is fixed, so the Time Calculation that from then on oscillograph just can be measured goes out the position of sampled point in storer of all collections.After all sampled point storages of gathering for the first time finish, just begin to gather one group of new sampled point and wait for new trigger event, after new trigger event arrived, timekeeping system was carried out new time measurement again and is calculated these new sampling point positions.These new sampled points drop on the not filling position of once gathering that produces between the some filling position of adopting, and in this way, the waveform trace just is made of the one group of group sampled point that occurs on the random site on the X-axis.
Time discriminator in the stochastic sampling is its gordian technique, it is used to discern triggers first sampled point clock of back with the mistiming between the trigger point, realize that and often need to be aided with complicated peripheral circuit the precision of measurement and the reliability of circuit are difficult to guarantee for the measurement of mistiming.The information after advantage is to provide pre-trigger message and triggers of random sampling technique.
Summary of the invention
The objective of the invention is to overcome above-mentioned deficiency of the prior art, provide a kind of circuit simple, pre-trigger message can be provided, can observe the equivalent sampling device that triggers front signal.
For achieving the above object, equivalent sampling device of the present invention comprises signal acquisition module, trigger port, trigger module, control module, it is characterized in that, also comprises a time delay adjustment module and a synchronization module;
The delay adjusting module is exported sampling clock and synchronous clock under the control of control module, sampling clock is under the delay adjusting module controls, and phase place accurately changes within the specific limits, changes once, and carries out one group of data acquisition; Definite phase relation is arranged between synchronous clock and the sampling clock;
Synchronization module carries out the synchronous clock of detected input signals and the output of delay adjusting module synchronously, and the input signal after outputs to acquisition module synchronously, under sampling clock control, carries out data acquisition;
One tunnel trigger pip outputs to trigger module through trigger port, and trigger module output trigger pip triggers once the delay adjusting module, carries out a data acquisition.
Equivalent sampling device of the present invention is to realize the foregoing invention purpose like this, and utilization signal Synchronization technology and time delay adjustment technology are realized the equivalent sampling of high speed periodic signal.By detected input signals and sampling clock is synchronous, guarantee that promptly measured signal remains consistent with the phase place of sampling clock before sampling, the phase differential between sampling clock and signal Synchronization clock is regulated in accurate then stepping, after repeated acquisition repeatedly, according to the context of phase place, with the data amalgamation of gathering at every turn together, promptly can recover a complete waveform, and significantly improve the equivalent sampling rate of signal, improve the observation ability of waveform details.Simultaneously, sampling can be irrelevant with trigger event, between these sampled points the time be spaced apart the known time, determine by sampling clock, when oscillograph when waiting for that trigger event arrives, it is inner just in continuous sampling and the result is stored, and therefore the pre-triggering degree of depth can be set, and observes the signal before triggering.
In addition, adopt the time delay method to change phase place, thereby change the sampling interval time of sampling clock, circuit is simple easily.
The present invention can realize the high-speed data acquistion system of the equivalent sampling speed of GSPS level, and can apply it in the more high-speed data acquistion system, as digital storage oscilloscope, high speed waveform analyzer etc., for civilian, military project electronic equipment provide the more modern means of testing of high target.
Description of drawings
Fig. 1 is the equivalent sampling principle figure of prior art order;
Fig. 2 is a prior art equivalent sampling schematic diagram at random;
Fig. 3 is a kind of embodiment theory diagram of equivalent sampling device of the present invention;
Fig. 4 is an equivalent sampling device schematic diagram of the present invention
Fig. 5 is a kind of embodiment theory diagram of synchronization module shown in Figure 3.
Fig. 6 is a kind of concrete implementing procedure figure of equivalent sampling waveform acquisition of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention is described.What need point out is that in the following description, when perhaps the detailed description of known function that adopts and design can desalinate subject content of the present invention, these were described in here and will be left in the basket.
Fig. 3 is a kind of embodiment theory diagram of equivalent sampling device of the present invention.Among the figure, equivalent sampling device comprises signal condition module 1, synchronization module 2, acquisition module 3, sample value storer 4, trigger port 5, trigger module 6, delay adjusting module 7, control module 8, microprocessor 9 and LCD 10.Wherein, sample value storer 4, trigger module 6, delay adjusting module 7,8 of control moulds realize that in a slice field programmable gate array (FPGA) the with dashed lines frame is partly represented among the figure.
In the present embodiment, signal condition passage 1 is transformed into the detected input signals of great dynamic range in the effective dynamic range of acquisition module 3 under the control of control module 8, to satisfy the requirement of acquisition module 3 samplings;
The synchronous clock of detected input signals that synchronization module 2 is come signal condition module 1 and 7 outputs of delay adjusting module is synchronous.Definite phase relation is arranged between sampling clock and the synchronous clock, and the detected input signals after synchronously also has the phase relation of determining with sampling clock;
Acquisition module 3 is made up of the two-forty analog to digital converter, be responsible for having the detected input signals of definite phase relation to finish Analog signals'digitalization with sampling clock with what synchronization module 2 was exported, sample value storer 4 is under the control of control module 8, digitized input signal is stored, microprocessor 9 OPADD signals then, by the Wave data of control module 8, be read in the microprocessor 9 sample value storer 4;
5 pairs of inputs of trigger port trigger pip is carried out shaping and level translation, then trigger pip is sent in the trigger module;
Microprocessor 9 is controlled the setting and the sampling work of whole equivalent device by control module 8, and with the digitized input signal reduction of sample value storer 4 storages, shows by LCD 10.
According to the difference of the actual sample rate of FPGA type selecting and employing, can design the delay adjusting device of different accuracy.For example, if adopt the sampling rate of 100MHz, if the stepping of delay adjusting is 1/500, then the delay adjusting precision of phase place is 10ns * 1/500=20ps, and the equivalent sampling rate can reach 50GSPS;
After repeatedly gathering,, with the data amalgamation of gathering at every turn together, promptly can recover a complete waveform according to the context of phase place.
In the present embodiment, employing Analog company model is that the ADC of AD9481 samples, and resolution is 8BIT, high sampling rate is 250MSPS, data output rate can be reduced to 125MHz, and its interface is supported LVTTL, and microprocessor adopts a high performance digital signal processor (DSP).
And field programmable gate array (Field Programmable Gate Array, abbreviation FPGA) adopts the SPARTAN 3A Series FPGA of Xilinx company, this a series of FPGA has strengthened the function of clock control cell specially, DCM wherein (Digital Clock Manage) clock control module can realize the accurate phase modulation to input clock, is applicable to the application that high speed signal is handled.
Fig. 4 is an equivalent sampling device schematic diagram of the present invention.Among the figure, sampling is for the second time compared with sampling for the first time, sampling clock time-delay Δ t, the 4th sampling, sampling clock time-delay Δ t, this is the same with the order equivalent sampling, but equivalent sampling device of the present invention, once trigger and to obtain one group of sampled point, and the same equivalent sampling at random of this point is the same.Sampling simultaneously depends on sampling clock, therefore, the pre-triggering degree of depth can be set, and observes the signal before triggering.
Fig. 5 is a kind of embodiment theory diagram of synchronization module shown in Figure 3.As shown in the figure, detected input signals one tunnel is input in the programmable delay line 201, in another road input comparator 202, convert digital pulse signal to, and be input in the digital phase discriminator 203 with synchronizing pulse, digital phase discriminator 203 output phase difference signals, and be input in the programmable delay line 201, detected input signals is delayed time, and last detected input signals and synchronous clock are synchronous.
Fig. 6 is a kind of concrete implementing procedure figure of equivalent sampling waveform acquisition of the present invention.As shown in the figure, in the present embodiment, initialization sampling clock phase at first, it is N that pre-triggering and repeated acquisition number of times are set, and under the control of microprocessor and control module, equivalent sampling device begins detected input signals is gathered, after gathering once, the fine setting sampling clock phase, then, judge whether current times of collection equals N,, proceed to gather if be less than N, when sampling number equals N, stop to gather, then, by each time of acquisition orders amalgamation sampled data, show at last.
Need to prove that for the conditioning of input signal, the storage of the data of collection, processing, demonstration and trigger collection etc. belong to prior art, do not repeat them here.
Although above the illustrative embodiment of the present invention is described; but should be understood that; the invention is not restricted to the scope of embodiment; to those skilled in the art; as long as various variations appended claim limit and the spirit and scope of the present invention determined in; these variations are conspicuous, and all utilize innovation and creation that the present invention conceives all at the row of protection.
Claims (3)
1. an equivalent sampling device comprises signal acquisition module, trigger port, trigger module, control module, it is characterized in that, also comprises a time delay adjustment module and a synchronization module;
The delay adjusting module is exported sampling clock and synchronous clock under the control of control module, sampling clock is under the delay adjusting module controls, and phase place accurately changes within the specific limits, changes once, and carries out one group of data acquisition; Definite phase relation is arranged between synchronous clock and the sampling clock;
Synchronization module carries out the synchronous clock of detected input signals and the output of delay adjusting module synchronously, and the input signal after outputs to acquisition module synchronously, under sampling clock control, carries out data acquisition;
One tunnel trigger pip outputs to trigger module through trigger port, and trigger module output trigger pip triggers once the delay adjusting module, carries out a data acquisition.
2. equivalent sampling device according to claim 1 is characterized in that described synchronization module comprises programmable delay line, comparer and digital phase discriminator;
Detected input signals one tunnel is input in the programmable delay line, in another road input comparator, convert digital pulse signal to, and be input in the digital phase discriminator with synchronous clock, digital phase discriminator output phase difference signal, and be input in the programmable delay line, detected input signals is delayed time, make detected input signals and synchronous clock synchronous.
3. equivalent sampling device according to claim 1 is characterized in that, also comprises signal condition module, microprocessor and LCD;
The signal condition passage is transformed into the detected input signals of great dynamic range in the effective dynamic range of acquisition module under the control of control module, to satisfy the requirement of acquisition module sampling;
The synchronous clock of detected input signals that synchronization module is come the signal condition module and the output of delay adjusting module is synchronous; Definite phase relation is arranged between sampling clock and the synchronous clock, and the detected input signals after synchronously also has the phase relation of determining with sampling clock;
Acquisition module is made up of the two-forty analog to digital converter, be responsible for having the detected input signals of definite phase relation to finish Analog signals'digitalization with sampling clock with what synchronization module was exported, the sample value storer is under the control of control module, digitized input signal is stored, microprocessor OPADD signal then, by the Wave data of control module, be read in the microprocessor the sample value storer;
Trigger port carries out shaping and level translation to the input trigger pip, then trigger pip is sent in the trigger module;
Trigger module is finished the triggering function of trigger port input signal under the control of control module, trigger the delay adjusting module and trigger sampling;
The delay adjusting module is under the control of control module, sampling clock and synchronous clock that output has definite phase relation, and the phase place of control sampling clock accurately changes within the specific limits, every variation once, just under the control of trigger module, carry out a data acquisition, and the corresponding pre-degree of depth that triggers can be set, so that observe the signal before triggering;
Microprocessor is controlled the setting and the sampling work of whole equivalent device by control module, and with the digitized input signal reduction of sample value memory stores, comes out by liquid crystal display displays.
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| CNB2007100502652A CN100529766C (en) | 2007-10-17 | 2007-10-17 | Equivalent sampling device |
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| CNB2007100502652A CN100529766C (en) | 2007-10-17 | 2007-10-17 | Equivalent sampling device |
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