CN101275973A - Digital storage oscillograph with very high waveform capturing rate - Google Patents
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Abstract
The present invention discloses a digital storage oscillograph which has a very high waveshape catching rate. A test signal is inputted and is transmitted to an ADC converting module for sampling after regulation, and is transmitted to a caching of a collecting memorizer under the controlling of triggering and time-base circuit. When a one-time waveform collection is completed, a parallel coprocessor collects data and maps to a waveshape lattice data corresponding with the lattice of the display screen, and starts a new round of collection and mapping when the mapping is completed. At the same time, a microprocessor executes the management operation, and when a timing refreshing time of the display screen is obtained, a display refreshing control logic is instantaneously activated for automatically combining the waveshape lattice data with lattice data in the display memorizer and updating the display of the display screen. The invention adopts a framework that a signal waveform collecting procession and the micro-processor operate parallelly to free the micro-process from the burdensome waveshape processing and display. The time of blind zone is reduced and the catching rate of waveshape is increased. The probability for discovering the transient abnormal signal and the test efficiency are increased.
Description
Technical field
The present invention relates to a kind of digital storage oscilloscope, specifically, relate to a kind of digital storage oscillograph with very high waveform capturing rate
Background technology
Development along with Digital Signal Processing, more and more deep based on the time-domain signal analysis aspect Study on Technology of taking a sample at a high speed, digitizing time domain testing tool has also obtained fast development, and digital storage oscilloscope has obtained widespread use as the most typical a kind of time domain testing tool.
The wave capture rate is one of important indicator of estimating digital storage oscilloscope performance quality.So-called " wave capture rate " just is meant the waveform number of times that digital oscilloscope is caught and shown in the unit interval.Wave capture rate deficiency will make the accidental signal of most transient states find, signal jitter analysis and eye pattern analysis are not more known where to begin.
As Fig. 1, traditional digital storage oscilloscope adopts a kind of Processing Structure of serial usually, and the data of sampling are sent to microprocessor from acquisition memory, through microprocessor processes, calculating parameter, finally send to demonstration.Microprocessor carry out that Wave data handles during this period of time in, oscillograph can not be gathered signal waveform, is called " blind area time " during this period of time.Usually, oscillograph sampling pull-in time approximately only accounts for 1% of total observation time.Therefore, will miss 99% waveform details in the time in the blind area, wave capture rate deficiency reduces testing efficiency greatly, under a lot of situations, can't satisfy the real-time testing application demand.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, provide a kind of wave capture rate high digital storage oscilloscope, to improve testing efficiency.
For achieving the above object, digital storage oscillograph with very high waveform capturing rate of the present invention, comprise: signal condition module, ADC modular converter, triggering and time base circuit, acquisition memory, microprocessor, display-memory, display screen, and parallel coprocessor;
Input test signal is sent into the ADC modular converter and is sampled after the conditioning of signal condition module, under the control of triggering and time base circuit sampled data is sent into the acquisition memory buffer memory;
After finishing waveform acquisition, parallel coprocessor is mapped to the image data in the acquisition memory and the corresponding waveform dot array data of display screen dot array, begins the collection and the mapping of a new round after mapping is finished again;
Meanwhile, microprocessor carries out menu management, man-machine interface management work, when arriving the display screen periodic refreshing during time, at once start and show refresh control logic, automatically the dot array data in the relevant interface data storehouse of waveform dot array data and menu management, the man-machine interface management work in the coprocessor of will walking abreast makes up in display-memory, and the demonstration of update displayed screen.
The present invention adopts the framework of signal waveform acquisition process and microprocessor concurrent working, allow microprocessor spin off from heavy waveform processing with showing, reduced the blind area time of digital storage oscilloscope, improved the wave capture rate, increased and found the probability of transient state abnormal signal, thereby also improved testing efficiency.
Description of drawings
Fig. 1 is traditional digital storage oscilloscope theory diagram;
Fig. 2 is a kind of embodiment theory diagram of digital storage oscillograph with very high waveform capturing rate of the present invention;
Fig. 3 is a kind of embodiment theory diagram of parallel coprocessor shown in Figure 2;
Fig. 4 is a kind of embodiment synoptic diagram that the sampled data in the digital storage oscillograph with very high waveform capturing rate of the present invention is mapped to the corresponding waveform database of display screen dot array;
Fig. 5 is conventional serial architecture digital storage oscilloscope capture effect figure;
Fig. 6 is digital storage oscilloscope capture effect figure of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention is described.What need point out is that although similar parts appear in the different accompanying drawings, they are endowed similar Reference numeral.In the following description, when perhaps the detailed description of known function that adopts and design can desalinate subject content of the present invention, these were described in here and will be left in the basket.
Fig. 1 is traditional digital storage oscilloscope theory diagram.Among the figure, input signal output amplitude suitable ADC modular converter 2 within the specific limits after 1 conditioning of signal condition module carries out the signal of data sampling, under the control of triggering and time base circuit 3, the Wave data of ADC modular converter 2 samplings is sent into buffer memory in the acquisition memory 4.
After finishing the primary reflection graphic data and gathering, microprocessor 5 reads in processing with the Wave data of gathering, and at last that the waveform of input signal and menu management, man-machine interface management is relevant interface data shows on display screen 7 by display-memory 6.
Fig. 2 is a kind of embodiment theory diagram of digital storage oscillograph with very high waveform capturing rate of the present invention.In the present embodiment, digital storage oscillograph with very high waveform capturing rate of the present invention comprises: signal condition module 1, ADC modular converter 2, triggering and time base circuit 3, acquisition memory 4, microprocessor 5, display-memory 6, display screen 7, and parallel coprocessor 8;
Input test signal is sent into ADC modular converter 2 and is sampled after 1 conditioning of signal condition module, under the control of triggering and time base circuit 3 and parallel coprocessor 8 sampled data is sent into acquisition memory 4 buffer memorys;
After finishing waveform acquisition, parallel coprocessor 8 is mapped to the image data in the acquisition memory 4 and the corresponding waveform dot array data of display screen dot array, begins the collection and the mapping of a new round after mapping is finished again;
Meanwhile, microprocessor 5 carries out menu management, man-machine interface management work, when arriving display screen 7 periodic refreshings during the time, at once start and show refresh control logic, automatically the dot array data in the relevant interface data storehouse of waveform dot array data and menu management, the man-machine interface management work in the coprocessor 8 of will walking abreast makes up at display-memory 6, and the demonstration of update displayed screen 7.
Fig. 3 is a kind of embodiment theory diagram of parallel coprocessor shown in Figure 2.Parallel coprocessor is the core that improves quick wave capture rate, in the present embodiment, its major function not only comprises the processing of waveform acquisition data and the demonstration of waveform, also comprise acquisition control module, be used to control the buffer memory Wave data relevant with trigger event, alleviated the computing burden of microprocessor 5 like this, further.
In the present embodiment, parallel coprocessor 8 comprises four parts, acquisition control module 801, waveform character processing module 802, waveform database 803 and data base read-write control module 804.Acquisition control module 801 is used to control the buffer memory Wave data relevant with trigger event.After finishing collection event, the control of data cache is handed to waveform character processing module 802, image data to buffer memory in the acquisition memory 4 is taken out a little or interpolation processing, then the image data pointwise is converted to the amplitude characteristic of waveform by the time relation, tie up to according to the pass of time and amplitude and to carry out the two dimensional character data storage in the waveform database 803, in waveform database, form and the corresponding waveform dot array data of display screen dot array.
After having finished once collection and having shone upon, start the collection and the mapping process of a new round immediately, when the waveform map amount, after promptly the repeated acquisition number of times reaches the grade of setting, by data base read-write control module 804 the waveform dot array data is sent to display-memory 6 again, and shows.
In the present embodiment, acquisition memory 4 adopts BLOCK RAM in the FPGA sheet is configured to the FIFO realization, and its operating rate generally can reach 250MB/s.
Gatherer process is mainly finished under the control by triggering and time base circuit 3 and acquisition control module 801.Acquisition control module 801 log-on data gatherer processes, FIFO are write and are enabled effectively, and FIFO writes clock and ADC modular converter 2 sampling clocks are synchronous, and the sampled data that modular converter 2 produces writes FIFO.Simultaneously, start pre-flip-flop number, reach the triggering depth value that presets up to pre-flip-flop number count value.During this period of time, the trigger circuit in triggering and the time base circuit 3 are in repressed state.Write data depth and equal to trigger in advance depth value in FIFO, if trigger pip does not also arrive, then make the FIFO read-write synchronously, the data number that remains in the FIFO equals to trigger in advance depth value; Trigger and arrive, it is invalid that FIFO reads to enable, and data fifo was only write and do not read this moment, till writing completely.The collection of Wave data belongs to prior art, in this enforcement, just adopts acquisition control module 801, be used to control the buffer memory Wave data relevant with trigger event, finish the Collection Co., Ltd of Wave data, like this, alleviated the computing burden of microprocessor 5 further.
In the present embodiment, after FIFO writes and expires, its control is delivered waveform character processing module 802, at this moment, control reads to enable effectively, read the data among the FIFO and carried out the 2-D data mapping in waveform database 803 by waveform character processing module 802, FIFO is read-only not to be write, and data are all read in FIFO.
Suppose to show that an amplitude wave shape always counting in the horizontal direction is that T, the resolution of ADC modular converter 2 are N, then maximum sampled value is 2
N, will regard the amplitude characteristic of waveform as, then required Wave data storage capacity is: T * 2
NIndividual bit.
Carrying out waveform when mapping, the storage work of waveform database is by from top to bottom, and mode is from left to right drawn, i.e. the T that ought once gather data, its size X
iExpression, 0≤i≤T-1 wherein, 0≤X
i≤ 2
N, in chronological order successively under the control of waveform character processing module, according to X
iValue with the i of T data drawing waveforms database row, X
iLine storage unit.
Be not difficult to find out that the start address of every row dot matrix in waveform database 803 in the waveform dot array data is 2
NIntegral multiple, promptly the start address of i row is: 2
N* i, so when i sampled data arrives waveform character processing module 802, corresponding memory location B
iBe:
B
i=2
N* i+X
iFormula 1)
When waveform database 803 shone upon, the storage unit that is addressed to promptly was marked as 1 to waveform character processing module 802 in the control image data.
After in Preset Time, carrying out the several times waveform acquisition and shining upon, just noted in the waveform database 803 and repeatedly gathered the track that the back waveform stays, promptly with the corresponding waveform dot array data of display screen dot array.
Be mapped to and corresponding this mapping process of waveform dot array data of display screen dot array in order to understand image data of the present invention more intuitively, shown in Figure 4, the address of each pixel in waveform database 803 in the digitized representation display screen dot array of about among the figure and top, each row in the numeral display screen of base, Bi represents that i image data is in this address that lists.
In the present embodiment, the number T of an image data is 500, and the resolution, N of ADC modular converter 2 is 8, image data size X
iBe followed successively by " 128,112,54,33 ... ", then needing waveform database 803 sizes is 500 * 256=128000bit, and wherein each bit is corresponding one by one with the pixel in the display screen dot array.By formula 1) as can be known,
First image data size 128 is mapped as the memory location:
B0＝0+128＝128；
Second image data size 112 is mapped as the memory location:
B1＝256+112＝368；
The 3rd image data size 54 is mapped as the memory location:
B2＝256×2+54＝566；
The 4th image data size 33 is mapped as the memory location:
B3＝256×3+33＝801；
…………。
The storage unit that is addressed to according to the memory location promptly is marked as 1, has just noted in waveform database 803 like this and has once gathered the track that the back waveform stays.
In the present embodiment, when waveform character processing module 802 is finished the waveform mapping in Preset Time after, control module 804 is read and write in the log-on data storehouse immediately, and waveform database 803 will shine upon good two-dimentional Wave data under its control sends into display-memory 6, and update displayed.
The design of data base read-write control module is simple relatively, only needs the generation address of order during its work, and Wave data is imported video memory.Be noted that and coordinate the moment that starts its work, the screen flicker that brings when to avoid because of the renewal video memory.
With the digital storage oscilloscope of traditional serial processing structure and the digital storage oscillograph with very high waveform capturing rate under the present invention to same carrier frequency 1MHz, the test of comparing of the modulated wave signal of modulating frequency 1kHz,
Because the digital storage oscilloscope of traditional serial processing structure is to gather, handle, brush screen, the time of gathering and handling is probably in the us magnitude, bigger during the brush screen because of data volume, finishing once, the brush screen needs the ms magnitude, handle and brush screen and can not gather waveform during this period of time, so the digital storage oscilloscope capture rate of traditional serial structure is quite low.Therefore, in Fig. 4, we can see, adopt the conventional digital storage oscilloscope of serial frame only to collect two amplitude wave shapes in a waveform refresh process.
And the digital storage oscillograph with very high waveform capturing rate under the present invention, when carrying out waveform processing and brush screen, in the ms magnitude time that video memory upgrades, waveform can be gathered and shine upon to parallel coprocessor also, the collection blind area time of this moment only is the us level mapping time of waveform, has improved the wave capture rate greatly.Thereby in Fig. 5, we can see, digital storage oscillograph with very high waveform capturing rate under the present invention has but been caught a large amount of waveforms, and the wave capture rate can be up to 160,000wfs/s, the truth that has reflected waveform, the waveform leak rate in having reduced to gather has improved testing efficiency.
Although above the illustrative embodiment of the present invention is described; but should be understood that; the invention is not restricted to the scope of embodiment; to those skilled in the art; as long as various variations appended claim limit and the spirit and scope of the present invention determined in; these variations are conspicuous, and all utilize innovation and creation that the present invention conceives all at the row of protection.
Claims (5)
1. digital storage oscillograph with very high waveform capturing rate comprises: signal condition module, ADC modular converter, triggering and time base circuit, acquisition memory, microprocessor, display-memory, display screen, it is characterized in that, and also comprise a parallel coprocessor;
Input test signal is sent into the ADC modular converter and is sampled after the conditioning of signal condition module, under the control of triggering and time base circuit sampled data is sent into the acquisition memory buffer memory;
After finishing waveform acquisition, parallel coprocessor is mapped to the image data in the acquisition memory and the corresponding waveform dot array data of display screen dot array, begins the collection and the mapping of a new round after mapping is finished again;
Meanwhile, microprocessor carries out menu management, man-machine interface management work, when arriving the display screen periodic refreshing during time, at once start and show refresh control logic, automatically the dot array data in the relevant interface data storehouse of waveform dot array data and menu management, the man-machine interface management work in the coprocessor of will walking abreast makes up in display-memory, and the demonstration of update displayed screen.
2. digital storage oscillograph with very high waveform capturing rate according to claim 1 is characterized in that, includes an acquisition control module in the described parallel coprocessor, is used to control the buffer memory Wave data relevant with trigger event.
3. digital storage oscillograph with very high waveform capturing rate according to claim 1 is characterized in that, described parallel coprocessor also comprises waveform character processing module and waveform database,
Described parallel coprocessor is mapped to the image data in the acquisition memory with the corresponding waveform dot array data of display screen dot array: the waveform character processing module, the image data of buffer memory in the acquisition memory is taken out a little or interpolation processing, then the image data pointwise is converted to the amplitude characteristic of waveform by the time relation, tie up to according to the pass of time and amplitude and to carry out the two dimensional character data storage in the waveform database, in waveform database, form and the corresponding waveform dot array data of display screen dot array.
4. digital storage oscillograph with very high waveform capturing rate according to claim 3, it is characterized in that, described parallel coprocessor also comprises a data base read-write control module, reach the grade of setting when the waveform map amount after, by the data base read-write control module data point battle array data in the waveform database are sent to display-memory, and show.
5. according to claim 3 or 4 described digital storage oscillograph with very high waveform capturing rate, it is characterized in that, described image data pointwise converts the amplitude characteristic of waveform to by time relation, ties up to according to the pass of time and amplitude and carries out the two dimensional character data storage in the waveform database and be:
Waveform always counting in the horizontal direction is that T, the resolution of ADC modular converter are N, and then maximum sampled value is 2
N, regard it amplitude characteristic of waveform as;
Carrying out waveform when mapping, the storage work of waveform database is by from top to bottom, and mode is from left to right drawn, the T of Cai Jiing data once, its size X
iExpression, 0≤i≤T-1 wherein, 0≤X
i≤ 2
N, in chronological order successively under the control of waveform character processing module, according to X
iValue with the i of T data drawing waveforms database row, X
iLine storage unit, the memory location B of correspondence in the waveform database
i,
B
i＝2
N×i+X
i
Storage unit promptly be marked as 1.
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