CN109116078A - A kind of digital storage oscilloscope with high speed serialization agreement triggering and decoding function - Google Patents
A kind of digital storage oscilloscope with high speed serialization agreement triggering and decoding function Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
- G01R13/0209—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form in numerical form
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
- G01R13/0218—Circuits therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
- G01R13/0218—Circuits therefor
- G01R13/0254—Circuits therefor for triggering, synchronisation
Abstract
The invention discloses a kind of digital storage oscilloscopes with high speed serialization agreement triggering and decoding function, high-speed serial signals are sampled by multi-disc ADC, then reduction of speed and pretreatment are carried out to sampled signal by corresponding acquisition FPGA, is finally sent into 1 processing FPGA and completes triggering/decoding function of high speed serialization agreement；It on the one hand can satisfy high-speed serial signals agreement triggering/decoded real-time in this way and improve the functional requirement of trigger point positioning accuracy, additionally it is possible to support triggering and decoding including various protocols such as RS232, PCIE, D-PHY, Ethernets；On the other hand the hardware circuit that entire scheme is related to is consistent with the structure of time-interleaved technology widely used in digital oscilloscope, saves hardware cost.
Description
Technical field
The invention belongs to digital oscilloscope technical fields, more specifically, are related to a kind of with high speed serialization association
The digital storage oscilloscope of view triggering and decoding function.
Background technique
Currently, with the development of electronic technology, the application range of universal serial bus has very big extension, such as medical image point
Data pass in desorption device, communicate between defeated smart phone and its camera, and multichannel real-time control etc. is realized in industrial system.It is same with this
When the serial bus signal rate that uses also be getting faster, such as the common bus signals rate of PCIe, USB 3.0, SATA all exists
1Gb/s or more, this is to digital oscilloscope serial protocol decoding/more stringent requirements are proposed for Trigger Function.However, with embedded
Wide parallel bus is replaced using universal serial bus more and more in system design, designer analyzes serial association to digital oscilloscope
More stringent requirements are proposed for the ability of view signal.
In serial protocol signal, all information all must be in a serial fashion in identical a small number of conducting wires (sometimes one)
Upper transmission.This means that a signal may include address information, control information, data information and clock information.Therefore, serially
The analysis of protocol signal needs to complete the work of two aspects, is on the one hand electrical characteristic and the waveform spy for analyzing protocol signal
Sign, such as amplitude, baud rate；It on the other hand is then to analyze its serial protocol information for being included, such as data information, address information
Deng.Ordinary numbers oscillograph is only capable of analyzing electrical characteristic and wave character, also can only according to the characteristics such as edge, pulsewidth come
Trigger signal, so digital oscilloscope is required to carry out triggering and decoded function to serial protocol signal from the angle of agreement
Energy.The main function of serial protocol decoding function be exactly when different serial protocol bus signals from digital oscilloscope input when,
Originally the Signal separator on a serial protocol line is gone out one of the various information by the operation by user to digital oscilloscope,
And the information is shown below corresponding signal waveform.And the major function of serial protocol triggering exactly shows digital oscilloscope
The interested place of user in the data information that zone location is decoded to above.
Pervious serial protocol decoding/Trigger Function mainly passes through analog comparator+programmable hardware and realizes, but the party
Case encounters difficulties when handling high-speed serial signals, and main cause is the maximum work of input deserializer (ISERDES) of programmable hardware
It is limited to make speed, cannot directly receive high-speed serial signals.For example, it is directed to currently used PCIE bus, PCIE 1.0 editions
This requires the transmission rate of 2.5Gb/s.Although the digitlization that corresponding High Speed Analog comparator will complete signal can be found,
But the 0/1 serial digital stream of high speed after digitizing is not available common chip and receives.
In serial protocol triggering decoding/function of existing digital oscilloscope, Lecroy company is touched using external hardware protocol
Hair+in house software protocol-decoding mode.Tektronix company uses asic chip as transmitter, by high-speed serial signals
Reduction of speed is converted to and carries out agreement triggering/decoding as receiver by FPGA after speed parallel signals.Although these methods solve
To protocol-decoding/Trigger Problems of high-speed serial signals, but all add additional hardware cost.
Summary of the invention
There is the triggering of high speed serialization agreement it is an object of the invention to overcome the deficiencies of the prior art and provide one kind and decode
The digital storage oscilloscope of function improves the accuracy of triggering point location to guarantee decoded real-time.
For achieving the above object, a kind of stored digital with high speed serialization agreement triggering and decoding function of the present invention
Oscillograph, which is characterized in that further include acquisition FPGA array and processing FPGA；
Acquisition FPGA array is made of the identical acquisition FPGA of multi-blocked structure, is compared again including level in every piece of acquisition FPGA
Module and OSERDES module；
User sends protocol command to industrial personal computer, and industrial personal computer generates string according to user setting and protocol command itself feature
Row protocol integrated test system word, it is then that high speed serialization protocol signal is defeated for configuring each module working condition in digital storage oscilloscope
Enter the analog channel completed to configuration, high speed serialization protocol signal is adopted by two-way ADC in each analog channel
Its sampled value is input to corresponding acquisition FPGA by sample；
Sampled value is compared by level comparison module with the agreement level that industrial personal computer configures, if sampled value is greater than agreement
Level then exports 1, otherwise exports 0, to generate the sampling point level data stream being made of " 0 ", " 1 "；The circulation of sampling point level data
Crossing OSERDES module converter is that differential parallel data is streamed into processing FPGA；
Handling FPGA includes ISERDES module, agreement main module and trigger module；Agreement main module includes pretreatment mould again
Block, timer, serial protocol triggering/decoder module, decoding RAM, decoding tag latch and triggering moment memory；Wherein,
Serial protocol triggering/decoder module includes protocol-analysis model, protocol-decoding module and agreement trigger module again；
ISERDES module will change parallel data stream into per the circulation of differential parallel data all the way, the mould configured according to industrial personal computer
Parallel data stream is grouped by quasi- port number, preprocessing module according to analog channel, in each group of parallel data stream according to
The sequence of sampled point time order and function, obtains the parallel data stream of multichannel, then searches for parallel data in each channel parallel data stream
The edge of stream, using first edge point as parallel data stream highest order, output is the parallel data stream originated with the point, finally right
Obtained each channel parallel data stream carries out snap shot, generates protocol data-flow and is sent to protocol-analysis model；
Protocol-analysis model is based on protocol data-flow and protocol type, according to different protocol types in protocol data
Search can represent the leader will that protocol frame transmission starts in stream, using leader will as starting point, decompose in protocol data-flow and represent difference
The data segment of meaning, the type of these data segments is described by state machine state, and saves the corresponding data value of these data segments
Timer moment value corresponding with data segment；
Agreement trigger module read protocol-analysis model output state machine state and data value, judge state machine state and
Whether data value meets preset trigger condition, if meeting trigger condition, output protocol trigger signal, and agreement trigger signal
After trigger module is handled, as the trigger signal of control waveform acquisition, global acquisition is controlled with this, realizes oscillography
Device waveform is shown and decoding data shows and can correspond；
Protocol-decoding module reads the state machine state and data value, timer moment value of protocol-analysis model output, will
It is organized into protocol-decoding data packet, deposit to decoding RAM；Meanwhile the timer moment is recorded at the trigger signal arrival moment
Value, and is stored in triggering moment memory, and by the write address A of the decoding RAM at the moment, decode address at the end of the writing of RAM
B, storage full scale will C is uniformly stored in decoding tag latch.
Goal of the invention of the invention is achieved in that
A kind of digital storage oscilloscope with high speed serialization agreement triggering and decoding function of the present invention, by ADC pairs of multi-disc
Then high-speed serial signals sampling carries out reduction of speed and pretreatment to sampled signal by corresponding acquisition FPGA, is finally sent into 1
Handle triggering/decoding function that high speed serialization agreement is completed in FPGA；It on the one hand can satisfy high-speed serial signals agreement in this way
Triggering/decoded real-time and the functional requirement for improving trigger point positioning accuracy, additionally it is possible to support to include RS232, PCIE, D-
The triggering and decoding of the various protocols such as PHY, Ethernet；On the other hand the hardware circuit and digital oscillography that entire scheme is related to
The structure of widely used time-interleaved technology is consistent in device, saves hardware cost.
Detailed description of the invention
Fig. 1 is a kind of specific embodiment of digital oscilloscope that the present invention has high speed serialization agreement triggering and decoding function
Schematic diagram；
Fig. 2 is that data flow extracts work flow diagram in preprocessing module；
Fig. 3 is multidiameter delay data comparison schematic diagram；
Fig. 4 is PCI-E agreement triggering/decoder module detailed structure view.
Specific embodiment
A specific embodiment of the invention is described with reference to the accompanying drawing, preferably so as to those skilled in the art
Understand the present invention.Requiring particular attention is that in the following description, when known function and the detailed description of design perhaps
When can desalinate main contents of the invention, these descriptions will be ignored herein.
Embodiment
Fig. 1 is a kind of specific embodiment of digital oscilloscope that the present invention has high speed serialization agreement triggering and decoding function
Schematic diagram.
In the present embodiment, as shown in Figure 1, a kind of number with high speed serialization agreement triggering and decoding function of the present invention
Storage oscillograph, the signal condition channel including the prior art, analog-digital converter, control module, waveform data memory, Wei Chu
Device, display screen are managed, for the acquisition, storage, display of serial protocol signal waveform, this part is identical as ordinary numbers oscillograph,
Details are not described herein.For the triggering of hardware realization high speed serialization agreement and decoding function, acquisition has also been devised in the present invention
FPGA array and processing FPGA.
As shown in Figure 1, only depicting the situation of single serial protocol analysis/decoder module for simplicity, in Fig. 1.It is more
When a agreement, the module of each agreement is similar with serial protocol analysis/decoder module example, by more in agreement main module
Road selector selection output final result decodes tag latch, triggering moment latch and agreement triggering letter to decoding RAM
Number.
In the present embodiment, acquisition FPGA array is made of the identical acquisition FPGA of 4 block structures, in every piece of acquisition FPGA again
Including level comparison module and OSERDES module；
User sends protocol command to industrial personal computer, and industrial personal computer generates string according to user setting and protocol command itself feature
Row protocol integrated test system word, it is then that high speed serialization protocol signal is defeated for configuring each module working condition in digital storage oscilloscope
Enter the analog channel 1~4 completed to configuration, high speed is gone here and there by the 8bit ADC of two-way 5GSa/s in each analog channel
Row protocol signal is sampled, its sampled value is input to corresponding acquisition FPGA；
Sampled value is compared by level comparison module with the agreement level that industrial personal computer configures, if sampled value is greater than agreement
Level then exports 1, otherwise exports 0, to generate the sampling point level data stream being made of " 0 ", " 1 "；The circulation of sampling point level data
The 1bit differential parallel data that OSERDES module converter is 4 road 1.25GSa/s is crossed to stream into processing FPGA；
Handling FPGA includes ISERDES module, agreement main module and trigger module；Agreement main module includes pretreatment mould again
Block, timer, serial protocol triggering/decoder module, decoding RAM, decoding tag latch and triggering moment memory；Wherein,
Serial protocol triggering/decoder module includes protocol-analysis model, protocol-decoding module and agreement trigger module again；
ISERDES module by 4 channels in total 32 road 1.25GSa/s 1bit differential parallel data circulation change 128 tunnels into
The 1bit parallel data stream of 312.5MSa/s, according to the analog channel number that industrial personal computer configures, preprocessing module is by 128 tunnels
The 1bit parallel data stream of 312.5MSa/s is divided into 4 groups by channel, according to sampled point time elder generation in each group of parallel data stream
After sort, obtain 4 road 32bit parallel data streams, then in each channel parallel data stream search for parallel data stream edge, with
First edge point is parallel data stream highest order, output be the 32bit parallel data stream originated with the point, finally to obtaining
Each channel parallel data stream carries out snap shot, generates protocol data-flow and is sent to protocol-analysis model；
In the present embodiment, as shown in Fig. 2, carrying out snap shot to each channel parallel data stream to generate protocol data-flow
Method are as follows:
(2.1), x [n] is set as the parallel data stream of input, and y [n] is the protocol data-flow of output；fs=10GSa/s is
Systematic sampling rate；finFor incoming serial signal rate；C, m, n are to calculate the inner mark register used, initial value 0；V is
Valid data digit in the protocol data-flow of this output, N=32 are the digit of x [n], n=0,1 ..., N-1；Operator
It indicates to be rounded downwards,Expression rounds up；
(2.2), by fsAnd finCalculate extraction ratio a, a=fs/fin；
(2.3), it reads input traffic x [n] and enters step (2.4) if a >=N, otherwise go to step (2.5)；
(2.4), when y [0]~[30]=0 y, ifThen m=m+1, v=0, y [31] are kept
Initial value；Otherwise,It gos to step again
(2.7)；
(2.5) if,When, thenValue is 0, v=
N, then go to step (2.7)；Otherwise,Enter back into step (2.6)；
(2.6), n=n+1 is enabled, circulation executes step (2.5)~(2.6) when n=31, by n reset 0, v=31, then
Enter step (2.7)；
(2.7), circulation executes step (2.3)~(2.6), protocol data-flow is generated, until agreement triggering/decoding terminates.
Protocol-analysis model is based on protocol data-flow and protocol type, according to different protocol types in protocol data
Search can represent the leader will that protocol frame transmission starts in stream, using leader will as starting point, decompose in protocol data-flow and represent difference
The data segment of meaning, the type of these data segments is described by state machine state, and saves the corresponding data value of these data segments
Timer moment value corresponding with data segment；
In the present embodiment, protocol type includes high speed serialization protocol signal and low-speed serial protocol signal, and high speed is gone here and there
Row protocol signal refers to that the serial protocol signal of a < 32 in above-mentioned processing, low-speed serial protocol signal refer to a >=32 in above-mentioned processing
Serial protocol signal；
Wherein, treatment process of the protocol-analysis model to high speed serialization protocol signal are as follows:
(3.1), high speed serialization protocol signal is setUnit of analysis be k bit, N isDigit, n=0,
1,…,N-1；V is valid data digit in high speed serialization protocol signal；Shift register is initialized, which is p
vmin, coefficient p is to meet pvmin≥vmax+ k and pvmin≥vmaxThe minimum value of+L, wherein vmax,vminFor the touching of this agreement
The maximum of v/small value in hair/decoding, L are the length of serial frame header will；The deposit of shift register low levelHigh v
Position valid data, and remove the position v data high-order in shift register；
(3.2), different protocol frames is indicated with each state of state machine, the initial state of init state machine is the free time
State；
(3.3), since shift register data is to enter in a parallel fashion, and cannot be guaranteed to meet serial frame header
Centainly there is the highest order of at a time shift register in first point of will, needs to carry out the multidiameter delay as shown in Fig. 3
Data compare.Module needs every clock to complete vmaxSecondary multilevel iudge, judges formula are as follows:
B[p·vmin- 1:pvmin- L]=H [L-1:0]
B[p·vmin- 2:pvmin- L-1]=H [L-1:0]
......
B [L-1:0]=H [L-1:0]
As L and vmaxIt when larger, be directly realized by and need to consume a large amount of FPGA resources, it is also possible to cause FPGA timing error.
Therefore, serial frame header will is searched in a shift register in such a way that parallel fragmentation compares in the present embodiment, and band
There is the data segment of frame head mark to be set as frame head, state machine enters frame head state；
(3.4), timer moment value when recording the data value of the data segment and entering the state, and it is corresponding with the data segment
State machine state export together；
(3.5), state machine enters next data segment state after notebook data section；
(3.6), circulation executes step (3.4)~(3.5), if current state is idle, jumps to step (3.3), directly
Terminate to agreement triggering/decoding；
Treatment process of the protocol-analysis model to low-speed serial protocol signal are as follows:
3.1) edge in low-speed serial protocol signal, is searched for, the timing by edge reaches 1 serially whenever the time
One signal position of output separates pulse when signal position, exports a signal position sampling pulse when reaching half of serial signal position；
3.2), between two separation pulses be a serial signal position, with serial signal position in signal position sampling pulse
Value be serial signal position value；
3.3) serial frame header will, is searched in serial signal position by the way of serially comparing, and with frame header
The data segment of will is set as frame head, and state machine enters frame head state；
3.4) timer moment value when, recording the data value of the data segment and entering the state, and it is corresponding with the data segment
State machine state export together；
3.5), state machine enters next data segment state after notebook data section；
3.6), circulation executes step 3.4)~3.5), if current state is idle, step 3.3) is jumped to, until association
View triggering/decoding terminates.
Agreement trigger module read protocol-analysis model output state machine state and data value, judge state machine state and
Whether data value meets preset trigger condition, if meeting trigger condition, output protocol trigger signal, and agreement trigger signal
After trigger module is handled, as the trigger signal of control waveform acquisition, global acquisition is controlled with this, realizes oscillography
Device waveform is shown and decoding data shows and can correspond；
In order to guarantee waveform show and decoding data show and can correspond, in addition to protocol-decoding data when
Carve outer, it is also necessary to record and waveform show known relation the reference moment and several special addresses, be respectively as follows: protocol-decoding
Module reads the state machine state and data value, timer moment value of protocol-analysis model output, is organized into protocol-decoding
Data packet, deposit to decoding RAM；Meanwhile timer moment value is recorded at the trigger signal arrival moment, and store in triggering
Memory is carved, and uniformly by address B, storage full scale will C at the end of the write address A of the decoding RAM at the moment, decoding the writing of RAM
It is stored in decoding tag latch.
Example
Below by taking the agreement of PCI-Express 1.0 triggering/decoding function is realized as an example, what the present invention will be described in detail is specific
Implement.
A kind of high speed serialization computer expansion bus standard of PCIe belongs to the point-to-point binary channels high bandwidth of high speed serialization and passes
Defeated, the equipment connected exclusively enjoys bandwidth chahnel, does not share bus bandwidth, mainly supports active power management, error reporting, end pair
The functions such as the reliability transmission at end, hot plug and service quality (QOS).Its main advantage is exactly message transmission rate height,
1.0 signal rate of PCI-Express in the present embodiment is 2.5Gb/s.
Table 1 is TLP frame format；
| STP | ID | TLP Header | Date payload | ECRC | LCRC | END |
| 1Byte | 2Bytes | 3/4DW | 0~1024DW | 1DW | 1DW | 1Byte |
Table 1
The TLP frame of PCI-E follows frame format shown in table 1, in physical layer transmission, by TLP frame in addition to STP and END
Part carry out data scrambling, after the completion of scrambling, do not scramble STP and END and the 8b/10b coding of scrambled rest part progress.
STP is encoded to K27.7, END K29.7, and rest part is to be encoded to Dxx.x.
Same Fig. 1 of digital oscilloscope structure shown in the present embodiment, analog channel 1 access PCI-E 1.0 using differential probe
Differential signal, after the completion of user setting, oscillograph starts to carry out the triggering of 1.0 serial protocol of PCI-E and decoding.The touching of PCI-E agreement
Hair/decoder module detailed construction also includes data de-scrambling as shown in figure 4, other than 3 main submodules, and 8b/10b is decoded,
CRC calculates three additional submodules.
The comparative level of level comparison module in acquisition FPGA 1A and 1B is set as 180mV.After the completion of comparing by
The ISERDES that OSERDES handles FPGA respectively receives the 32 road differential parallel data streams in each channel, switchs to 128 tunnels
312.5MS/s parallel data.
Preprocessing module selects corresponding 32 channel parallel data of analog channel 1 from 128 circuit-switched datas, when according to high sampled point
Between successively sort, search for parallel data in edge, displacement adjustment data, make first point behind highest order edge.To 32bit
Parallel data sample rate takes out 1 by 4, extracts the 30th, 26,22,18,14,10,6,2, forms 8bit protocol data-flow.
The input of protocol-analysis model arranges submodule and 8bit protocol data-flow is stored in a 40bit shift register A
In.Using 5 system clocks as the period, preceding 4 clock reads 10bit data every time, opens data effective marker, and rear 1 clock is closed
Data effective marker.When data effective marker is opened, subsequent protocol triggering/decoded processing work, data effective marker are carried out
When closing, subsequent processing work stoppage.
Head landmark search submodule searches for 10bit data value K27.7 (STP) in A, is most with STP after the completion of search
Data are newly stored into 40bit shift register B by high 10bit.
The 10b code character of input is decoded as 8b character by 8b/10b decoding sub-module, and exports D/K flag bit, is distinguished
D character and K character in 10b code.Data de-scrambling submodule will need the 8b character (D character) descrambled to carry out descrambling operation.
It in state machine submodule, is originated by IDLE state, enters stp state, latch mode after receiving the 8b character of K27.7
Value STP, data value 0 latch timer current time value T.When next 8b character (most-significant byte of ID) enter when, state machine into
Enter ID state, export state/data/moment value of latch, and latches current state value ID, data value and moment value.Equally
Method switches corresponding state, output state/data/moment value according to the frame format of input 8b character and table 1.If same shape
Multiple 8b characters of state, the most 32bit of output data, record moment are wherein high 8bit arrival moment value.
CRC computing module calculates the part check value for needing to verify in TLP frame, as a result compared with the CRC field in frame,
CRC mismark is not exported simultaneously.
PCI-E agreement trigger module judges whether according to the state value and data value of data sectional submodule state output
The trigger condition for meeting user exports PCI-E trigger signal when meeting.PCI-E trigger signal is through agreement trigger selector, from more
Output is selected in the trigger signal of a agreement.
State/data/moment value is organized into decoding data packet by PCI-E protocol-decoding module, is calculated decoding RAM and is write ground
Location opens decoding and writes enabled, by decoded output selector, writes the data packet decoding RAM.Solve code mark deposit solution code mark
Latch.
When trigger signal arrives, timer writes down triggering moment, is stored in triggering moment latch.
After waveform is shown, industrial personal computer reads the data of decoding RAM and two latch, and solution yardage is calculated and be shown
According to.
Although the illustrative specific embodiment of the present invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the present invention is not limited to the range of specific embodiment, to the common skill of the art
For art personnel, if various change the attached claims limit and determine the spirit and scope of the present invention in, these
Variation is it will be apparent that all utilize the innovation and creation of present inventive concept in the column of protection.
Claims (3)
1. a kind of digital storage oscilloscope with high speed serialization agreement triggering and decoding function, which is characterized in that further include adopting
Collect FPGA array and processing FPGA；
Acquisition FPGA array is made of the identical acquisition FPGA of multi-blocked structure, again includes level comparison module in every piece of acquisition FPGA
With OSERDES module；
User sends protocol command to industrial personal computer, and industrial personal computer generates serial association according to user setting and protocol command itself feature
Then high speed serialization protocol signal is input to by view control word for configuring each module working condition in digital storage oscilloscope
The analog channel completed is configured, high speed serialization protocol signal is sampled by two-way ADC in each analog channel, by it
Sampled value is input to corresponding acquisition FPGA；
Sampled value is compared by level comparison module with the agreement level that industrial personal computer configures, if sampled value is greater than agreement electricity
It is flat, then 1 is exported, otherwise exports 0, to generate the sampling point level data stream being made of " 0 ", " 1 "；Sampling point level data stream passes through
OSERDES module converter is that differential parallel data is streamed into processing FPGA；
Handling FPGA includes ISERDES module, agreement main module and trigger module；Agreement main module include again preprocessing module,
Timer, serial protocol triggering/decoder module, decoding RAM, decoding tag latch and triggering moment memory；Wherein, serially
Agreement triggering/decoder module includes protocol-analysis model, protocol-decoding module and agreement trigger module again；
ISERDES module will change parallel data stream into per the circulation of differential parallel data all the way, and the simulation according to industrial personal computer configuration is logical
Parallel data stream is grouped by road number, preprocessing module according to analog channel, according to sampling in each group of parallel data stream
Point time order and function sequence, obtains the parallel data stream of multichannel, parallel data stream is then searched in each channel parallel data stream
Edge, using first edge point as parallel data stream highest order, output be the parallel data stream originated with the point, finally to obtaining
Each channel parallel data stream carry out snap shot, generate protocol data-flow simultaneously be sent to protocol-analysis model；
Protocol-analysis model is based on protocol data-flow and protocol type, according to different protocol types in protocol data-flow
Search can represent the leader will that protocol frame transmission starts, to represent difference in decomposition protocol data-flow and contain using leader will as starting point
Justice data segment, the type of these data segments is described by state machine state, and save the corresponding data value of these data segments and
The corresponding timer moment value of data segment；
Agreement trigger module reads the state machine state and data value of protocol-analysis model output, judges state machine state and data
Whether value meets preset trigger condition, if meeting trigger condition, output protocol trigger signal, agreement trigger signal is passed through
After trigger module processing, as the trigger signal of control waveform acquisition, global acquisition is controlled with this, realizes oscillograph wave
Shape is shown and decoding data shows and can correspond；
Protocol-decoding module reads the state machine state and data value, timer moment value of protocol-analysis model output, by its group
It is made into protocol-decoding data packet, deposit to decoding RAM；Meanwhile timer moment value is recorded at the trigger signal arrival moment, and
It is stored in triggering moment memory, and by address B, storage at the end of the write address A of the decoding RAM at the moment, the writing of decoding RAM
Full scale will C is uniformly stored in decoding tag latch.
2. a kind of digital storage oscilloscope with high speed serialization agreement triggering and decoding function according to claim 1,
It is characterized in that, carrying out snap shot to each channel parallel data stream in the preprocessing module to generate protocol data-flow
Method are as follows:
(2.1), x [n] is set as the parallel data stream of input, and y [n] is the protocol data-flow of output；fsFor systematic sampling rate；finFor
Incoming serial signal rate；C, m, n are to calculate the inner mark register used, initial value 0；V is the agreement of this output
Valid data digit in data flow, N are the digit of x [n], n=0,1 ..., N-1；OperatorIt indicates to be rounded downwards,Indicate to
Upper rounding；
(2.2), by fsAnd finCalculate extraction ratio a, a=fs/fin；
(2.3), it reads input traffic x [n] and enters step (2.4) if a >=N, otherwise go to step (2.5)；
(2.4), as y [0]~y [N-2]=0, ifThen m=m+1, v=0, y [N-1] keep former
Value；Otherwise,M=0, then go to step (2.7)；
(2.5) if,When, thenY [0]~y [N-1-n] value is 0, v=n, then
Go to step (2.7)；Otherwise,Enter back into step (2.6)；
(2.6), n=n+1 is enabled, circulation executes step (2.5)~(2.6) when n=N-1, will reset 0, v=N-1, enter back into
Step (2.7)；
(2.7), circulation executes step (2.3)~(2.6), protocol data-flow is generated, until agreement triggering/decoding terminates.
3. a kind of digital storage oscilloscope with high speed serialization agreement triggering and decoding function according to claim 1,
It is characterized in that, the protocol type includes high speed serialization protocol signal and low-speed serial protocol signal；
Treatment process of the protocol-analysis model to high speed serialization protocol signal are as follows:
(3.1), high speed serialization protocol signal is setUnit of analysis be k bit, N isDigit, n=0,1 ..., N-
1；V is valid data digit in high speed serialization protocol signal；Shift register is initialized, which is pvmin, it is
Number p is to meet pvmin≥vmax+ k and pvmin≥vmaxThe minimum value of+L, wherein vmax,vminFor this agreement triggering/decoding
The maximum of middle v/small value, L are the length of serial frame header will；The deposit of shift register low levelHigh v significant figures
According to, and remove the position v data high-order in shift register；
(3.2), different protocol frames is indicated with each state of state machine, the initial state of init state machine is idle shape
State；
(3.3), serial frame header will is searched in a shift register in such a way that parallel fragmentation compares, and with frame header
The data segment of will is set as frame head, and state machine enters frame head state；
(3.4), timer moment value when recording the data value of the data segment and entering the state, and shape corresponding with the data segment
State machine state exports together；
(3.5), state machine enters next data segment state after notebook data section；
(3.6), circulation executes step (3.4)~(3.5), if current state is idle, jumps to step (3.3), until association
View triggering/decoding terminates；
Treatment process of the protocol-analysis model to low-speed serial protocol signal are as follows:
3.1) edge in low-speed serial protocol signal, is searched for, the timing by edge reaches 1 serial signal whenever the time
One signal position of output separates pulse when position, exports a signal position sampling pulse when reaching half of serial signal position；
3.2), between two separation pulses be a serial signal position, with value of the serial signal position in signal position sampling pulse
For the value of serial signal position；
3.3) serial frame header will, is searched in serial signal position by the way of serially comparing, and with frame head mark
Data segment is set as frame head, and state machine enters frame head state；
3.4) timer moment value when, recording the data value of the data segment and entering the state, and shape corresponding with the data segment
State machine state exports together；
3.5), state machine enters next data segment state after notebook data section；
3.6), circulation executes step 3.4)~3.5), if current state is idle, step 3.3) is jumped to, until agreement is touched
Hair/decoding terminates.
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| CN110940841A (en) * | 2019-10-09 | 2020-03-31 | 电子科技大学 | Digital three-dimensional oscilloscope rapid acquisition system based on FPGA |
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