CN108170616B - System for realizing clock domain crossing signal transmission by using latch - Google Patents

Abstract

The invention relates to a system for realizing cross-clock domain signal transmission by utilizing a latch, which is provided with a latch using a first clock domain clock aclk, a signal den to be transmitted is input into the latch to set the latch, a signal den _ latch output by the latch is connected to a three-bit register den _ pipe [2:0], and a signal output by a 1 st bit den _ pipe [1] of the register is used as a zero clearing signal of the latch and is input into the latch to reset the latch. And a signal dre _ aclk output at the 1 st bit den _ pipe [1] of the register is connected with one input port of the AND gate through a NOT gate, a signal output at the 0 th bit den _ pipe [0] of the register is connected with the other input port of the AND gate, and a signal drdy _ aclk corresponding to the second clock domain clock is obtained at an output port of the AND gate. The invention has simple structure and is suitable for clock domain crossing pulse signal transmission when high-frequency signals enter a low-frequency clock domain.

Description

System for realizing clock domain crossing signal transmission by using latch

Technical Field

The invention relates to a clock domain crossing signal transmission technology, in particular to a system for realizing clock domain crossing signal transmission by using a latch.

Background

The existing processing of clock domain crossing signals can be divided into the following methods:

1) two beats are made with a register: this method is only suitable for signals crossing from a low frequency clock to a high frequency clock.

2) A counter is used to properly stretch the high frequency signal to a width greater than one period of the low frequency clock: the essence of this method is to reduce the clock frequency, and the signal generated by the high frequency clock is reduced to a lower frequency than the original low frequency clock. This method is only suitable for the premise that the frequency relationships of each other are known.

3) Using handshake signals, RAM and fifo: the handshake protocol mode is used for processing data transmission across clock domains, and only the handshake signals (req and ack) of the two parties need to be synchronized by using a pulse detection method respectively. In a specific implementation, assuming that the req, ack, and data buses are all in an invalid state during initialization, the sending domain first puts data into the buses, and then sends valid req signals to the receiving domain. The receiving domain latches the data bus upon detecting a valid req signal and then sends back a valid ack signal indicating a read completion acknowledge. The sending domain withdraws the current req signal after detecting the valid ack signal, and the receiving domain also withdraws the ack signal correspondingly after detecting the req withdrawal, and at the moment, one normal handshake communication is completed. Thereafter, the sending domain may continue to begin the next handshake communication, looping. This approach requires the addition of some extra control signals and circuitry for crossing from the high frequency clock to the low frequency clock, regardless of the frequency relationship.

The essence of the existing methods is that a synchronous mode is adopted to transmit clock signals, and a clock domain crossing signal transmission technology which adopts an asynchronous mode to widen pulse width is lacked.

Disclosure of Invention

The invention aims to provide a system for realizing cross-clock-domain signal transmission by using a latch, which realizes cross-clock-domain pulse signal transmission and is suitable for high-frequency signals entering a low-frequency clock domain.

In order to achieve the purpose, the technical scheme of the invention is to provide a system for realizing cross-clock domain signal transmission by using a latch, the system is provided with the latch using a first clock domain clock aclk, a signal den to be transmitted is input into the latch to set the latch, a signal den _ latch output by the latch is connected to a three-bit register den _ pipe [2:0], and a signal output by a 1 st bit den _ pipe [1] of the register is used as a clear signal of the latch and is input into the latch to reset the latch.

The latch comprises a set reset latch module, wherein the set reset latch module is provided with a set end lat _ set _ b, a reset end lat _ rst _ b, an output end q and a clock signal input end CK; wherein, the first clock domain clock aclk is input to the clock signal input terminal CK; the output end q serves as the output end of the latch to output a signal den _ latch;

the latch, comprising: a first input end rst1_ b which is actively reset at low level and is input with a signal cfg _ reset _ b triggered by a falling edge; a second input terminal set2, which is set active high and inputs the signal den; a third input end rst3 for high level effective reset, which inputs a zero clearing signal;

the result of negation of the signals of the first input end rst1_ b and the second input end set2 after bit-wise addition is input into the set end lat _ set _ b, and when the signal at the set end lat _ set _ b is at low level, 1 is obtained at the output end q;

and the signal at the third input end rst3 and the inverted signal at the second input end set2 are subjected to bitwise AND calculation to obtain a numerical value, then the numerical value is subjected to bitwise OR calculation to obtain an inverted numerical value of the signal at the first input end rst1_ b, the inverted result of the OR calculation is input to the reset end lat _ rst _ b, and when the signal at the reset end lat _ rst _ b is at a low level, the output end q is 0.

The first input end rst1_ b and the second input end set2 are connected to an input port of a first AND gate respectively, and an output port of the first AND gate is connected to a set end lat _ set _ b of the set-reset latch module through a first NOT gate.

The first input end rst1_ b is connected to one input port of a first OR gate through a second NOT gate, the other input port of the first OR gate is connected with the output port of a second AND gate, a second input end set2 is connected to one input port of the second AND gate through a third NOT gate, and a third input end rst3 is connected with the other input port of the second AND gate; the output port of the first or gate is connected to the reset terminal lat _ rst _ b of the set-reset latch module through a fourth not gate.

And a signal dre _ aclk output at the 1 st bit den _ pipe [1] of the register is connected with one input port of the third AND gate through a fifth NOT gate, a signal output at the 0 th bit den _ pipe [0] of the register is connected with the other input port of the third AND gate, and a signal drdy _ aclk corresponding to the second clock domain clock is obtained at the output port of the third AND gate.

When the signal cfg _ reset _ b input from the first input terminal rst1_ b is at a low level, the register is assigned with a three-bit binary number 000, otherwise, the output signal den _ latch of the latch is spliced with the values den _ pipe [2:1] of the 2 nd bit and the 1 st bit of the register and then registered.

The system for realizing cross-clock domain signal transmission by using the latch has the advantages that the latch with setting and resetting is used for transmitting data, the structure is simple, and the data transmission is independent of clock frequency. In the prior art, latches, particularly latches with setting and resetting functions at the same time, are avoided as much as possible in the cross-clock domain signal transmission design, but the invention utilizes the characteristic that the latches can be reset and set, and utilizes the ports for setting and resetting to transmit signals instead of the traditional method of transmitting data through a clock/data terminal (clock).

Drawings

FIG. 1 is a schematic diagram of a system for implementing cross-clock domain signaling using latches in accordance with the present invention;

fig. 2 is a timing diagram of exemplary signals in the system of the present invention.

Detailed Description

The system of the invention adopts a latch (latch) with asynchronous set (set) and reset (reset) simultaneously to realize the clock domain crossing transmission of signals.

Referring to fig. 1 and fig. 2 and table 1, the system of the present invention is provided with a latch, which includes a set-reset latch module (set-reset latch), the set-reset latch module has a set terminal lat _ set _ b, a reset terminal lat _ rst _ b, an output terminal q, and a clock signal input terminal CK; wherein, the clock signal input terminal CK inputs the clock signal aclk of the slow clock domain; the output q also serves as the output of the overall latch, which outputs a signal den _ latch to a three-bit register den _ pipe [2:0] formed by D flip-flops.

The latch also has a first input end rst1_ b which is reset effectively at low level, and the input end of the first input end rst is a signal cfg _ reset _ b triggered by falling edges; a second input terminal set2, which is set active high and inputs the signal den; and a third input end rst3 which is high-level active reset and is input with a clear signal (clear signal) clr _ den _ latch, and the output signal dre _ aclk at the 1 st bit den _ pipe [1] of the register is used as the clear signal.

When the signal cfg _ reset _ b input to the first input terminal rst1_ b is low, the register is asserted with a three-bit binary number of 000, otherwise the output signal den _ latch of the latch is registered with the value obtained by splicing the 2 nd bit and the 1 st bit den _ pipe [2:1] of the register.

The first input end rst1_ b and the second input end set2 are respectively connected to the input of a first and gate, the output of the first and gate is connected to the set end lat _ set _ b of the set-reset latch module through a first not gate, so that the result of negation of the signals at the input ends set2 and rst1_ b after bit-wise and calculation is input to the set end lat _ set _ b, and when the signal at the set end lat _ set _ b is low, the output end q obtains 1 (high level).

The first input rst1_ b is connected to one input of a first or gate through a second not gate, the other input of the first or gate is connected to the output of a second and gate, the second input set2 is connected to one input of the second and gate through a third not gate, and the third input rst3 is connected to the other input of the second and gate. The output of the first or gate is connected to the reset terminal lat _ rst _ b of the set-reset latch module through a fourth not gate, so that the inverted value of the bit-by-bit or the calculated result of the "inverted value of the signal at the input terminal rst1_ b" and the "bit-by-bit and calculated value of the signal at the input terminal rst3 and inverted set 2" is input to the reset terminal lat _ rst _ b, and when the signal at the reset terminal lat _ rst _ b is low, the output terminal q obtains 0 (low level).

The output signal dre _ aclk at the 1 st bit den _ pipe [1] of the register is connected with one input of a third AND gate through a fifth NOT gate, the output signal at the 0 th bit den _ pipe [0] of the register is connected with the other input of the third AND gate, and the third AND gate outputs a signal drdy _ aclk, so that the result of bit-wise and calculation is carried out on the value inverted by the 1 st bit den _ pipe [1] of the register and the value of the 0 th bit den _ pipe [0] of the register to serve as the output signal drdy _ aclk.

In the system, a signal den needing to be transmitted is input, the latch is set through the second input end set2 of the latch, the output of the latch is 1, so that a pulse signal of the signal den is successfully adopted, then the output signal den _ latch of the latch is adopted by using the clock aclk of a slow clock domain, a clear signal clr _ den _ latch of the latch is generated at the same time, the clear signal is transmitted to the reset end of the latch through the third input end rst3, and the latch is reset to be clear from 0. If a clock cycle of aclk signal is needed, the system of the invention can provide an output signal drdy _ aclk adapted to the clock cycle, so as to realize the clock domain crossing transmission of the signal.

TABLE 1 code examples of system hardware description languages

While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.

Claims (5)

1. A system for implementing clock domain crossing signal transmission using latches,

the system is provided with a latch using a first clock domain clock aclk, a signal den to be transmitted is input into the latch to set the latch, a signal den _ latch output by the latch is connected to a three-position register den _ pipe [2:0], a signal output by a 1 st bit den _ pipe [1] of the register is used as a zero clearing signal of the latch and is input into the latch to reset the latch;

the latch comprises a set reset latch module, wherein the set reset latch module is provided with a set end lat _ set _ b, a reset end lat _ rst _ b, an output end q and a clock signal input end CK; wherein, the first clock domain clock aclk is input to the clock signal input terminal CK; the output end q serves as the output end of the latch to output a signal den _ latch;

the latch, comprising: a first input end rst1_ b which is actively reset at low level and is input with a signal cfg _ reset _ b triggered by a falling edge; a second input terminal set2, which is set active high and inputs the signal den; a third input end rst3 for high level effective reset, which inputs a zero clearing signal;

the result of negation of the signals of the first input end rst1_ b and the second input end set2 after bit-wise addition is input into the set end lat _ set _ b, and when the signal at the set end lat _ set _ b is at low level, 1 is obtained at the output end q;

and the signal at the third input end rst3 and the inverted signal at the second input end set2 are subjected to bitwise AND calculation to obtain a numerical value, then the numerical value is subjected to bitwise OR calculation to obtain an inverted numerical value of the signal at the first input end rst1_ b, the inverted result of the OR calculation is input to the reset end lat _ rst _ b, and when the signal at the reset end lat _ rst _ b is at a low level, the output end q is 0.

2. The system of claim 1,

the first input end rst1_ b and the second input end set2 are connected to an input port of a first AND gate respectively, and an output port of the first AND gate is connected to a set end lat _ set _ b of the set-reset latch module through a first NOT gate.

3. The system of claim 1,

the first input end rst1_ b is connected to one input port of a first OR gate through a second NOT gate, the other input port of the first OR gate is connected with the output port of a second AND gate, a second input end set2 is connected to one input port of the second AND gate through a third NOT gate, and a third input end rst3 is connected with the other input port of the second AND gate; the output port of the first or gate is connected to the reset terminal lat _ rst _ b of the set-reset latch module through a fourth not gate.

4. The system of claim 1,

and a signal dre _ aclk output at the 1 st bit den _ pipe [1] of the register is connected with one input port of the third AND gate through a fifth NOT gate, a signal output at the 0 th bit den _ pipe [0] of the register is connected with the other input port of the third AND gate, and a signal drdy _ aclk corresponding to the second clock domain clock is obtained at the output port of the third AND gate.

5. The system of claim 1,

when the signal cfg _ reset _ b input from the first input terminal rst1_ b is at a low level, the register is assigned with a three-bit binary number 000, otherwise, the output signal den _ latch of the latch is spliced with the values den _ pipe [2:1] of the 2 nd bit and the 1 st bit of the register and then registered.

Images