CN108170616A - The system that cross clock domain signal transmission is realized using latch - Google Patents
The system that cross clock domain signal transmission is realized using latch Download PDFInfo
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- CN108170616A CN108170616A CN201611116237.1A CN201611116237A CN108170616A CN 108170616 A CN108170616 A CN 108170616A CN 201611116237 A CN201611116237 A CN 201611116237A CN 108170616 A CN108170616 A CN 108170616A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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Abstract
The present invention relates to a kind of systems that cross clock domain signal transmission is realized using latch, equipped with the latch for using the first clock domain clock aclk, inputting signal den to be transmitted to the latch makes the latch set, and the signal den_latch of latch output is connected to a three bit register den_pipe [2:0], by reset signal of the signal of the 1st den_pipe [1] output of register as latch, being input to latch makes its reset.The signal dre_aclk exported at the 1st den_pipe [1] of the register passes through NOT gate connection and an input port of door, signal connection and another input port of door exported at the 0th den_pipe [0] of register, signal drdy_aclk corresponding with second clock domain clock is obtained at this with the output port of door.The configuration of the present invention is simple enters the cross clock domain pulse signal transmission of low frequency clock domain suitable for high-frequency signal.
Description
Technical field
The present invention relates to cross clock domain signal transmission technologies, more particularly to a kind of to realize cross clock domain signal using latch
The system of transmission.
Background technology
The processing of existing cross clock domain signal, can be divided into following several method：
1) two bats are played with register：This method is only applicable to signal and crosses high frequency clock from low-frequency clock.
2) it goes to do high-frequency signal into appropriate broadening with a counter, its width is made to be more than a week of low-frequency clock
Phase：The essence of this method is to reduce clock frequency, the signal that high frequency clock generates first has been done the reduction of frequency, be reduced to
It is also lower than original low-frequency clock.This method is only applicable under the premise of knowing mutual frequency relation.
3) using handshake, RAM and fifo：Clock-domain crossing data is handled using Handshake Protocol mode to transmit, it is only necessary to
The handshake (req and ack) of both sides is synchronized respectively using pulse detecting method.In the concrete realization, it is assumed that req,
For ack, data bus in initialization all in invalid state, sending domain first places the data into bus, then sends effective req
Signal gives reception domain.Domain latch data bus after effective req signals are detected is received, then one effective ack of loopback
Signal, which represents to read, completes response.Sending domain cancels current req signals after effective ack signals are detected, receives domain and is examining
Ack signals are also accordingly cancelled after measuring req revocations, complete a subnormal handshake communication at this time.Hereafter, sending domain can continue open
Begin handshake communication next time, so recycles.This method needs to increase some additional control signals and circuit, for from high frequency
Clock crosses low-frequency clock, is indifferent to frequency relation.
The essence of above-mentioned existing method is all to transmit clock signal by the way of synchronous, is lacked using asynchronous system exhibition
The cross clock domain signal transmission technology of wide pulse width.
Invention content
The purpose of the present invention is to provide it is a kind of using latch realize cross clock domain signal transmission system, realize across when
The pulse signal transmission in clock domain enters low frequency clock domain suitable for high-frequency signal.
In order to achieve the above object, the technical scheme is that offer is a kind of to realize cross clock domain signal using latch
The system of transmission, the system are equipped with the latch using the first clock domain clock aclk, are inputted to the latch to be transmitted
Signal den make the latch set, the signal den_latch of latch output is connected to a three bit register den_
pipe[2:0], by reset signal of the signal of the 1st den_pipe [1] output of register as latch, it is input to latch
Make its reset.
The latch includes set-reset latch module, and the set-reset latch module has set end lat_set_
B, reset terminal lat_rst_b, output terminal q, clock signal input terminal CK；Wherein, the first clock domain clock aclk is input to clock
Signal input part CK；The output terminal q carrys out output signal den_latch as the output terminal of latch；
The latch, comprising：The first input end rst1_b of low level active homing, input are failing edge triggering
Signal cfg_reset_b；Second input terminal set2 of the effective set of high level, input are signal den；High level active homing
Third input terminal rst3, input is reset signal；
The signal step-by-step of the first input end rst1_b and the second input terminal set2 carry out the result with being negated after calculating
It inputs the set end lat_set_b, when signal is low level at set end lat_set_b, 1 is obtained in output terminal q；
After signal is carried out and is calculated with signal step-by-step at the second input terminal set2 negated at the third input terminal rst3
Numerical value, then the numerical value step-by-step negated with signal at the first input end rst1_b carries out or calculates, and will or calculate gained and ties
Fruit inputs the reset terminal lat_rst_b after negating, when signal is low level at reset terminal lat_rst_b, obtained in output terminal q
To 0.
The first input end rst1_b, the second input terminal set2 are respectively connected to the input port of first and door, and first
The set end lat_set_b of the set-reset latch module is connected to by the first NOT gate with the output port of door.
The first input end rst1_b is connected to an input port of first or door by the second NOT gate, and first or door
Another input port connect with second with the output port of door, the second input terminal set2 by third NOT gate be connected to this
Two connect with an input port of door, third input terminal rst3 with second with another input port of door；Described first or
The output port of door is connected to the reset terminal lat_rst_b of the set-reset latch module by the 4th NOT gate.
At the 1st den_pipe [1] of the register export signal dre_aclk by the 5th NOT gate connect third with
One input port of door, the signal connection third and another input terminal of door exported at the 0th den_pipe [0] of register
Mouthful, in the third signal drdy_aclk corresponding with second clock domain clock is obtained with the output port of door.
When the signal cfg_reset_b of first input end rst1_b input is low level, register with three two into
Several 000 assignment are made, otherwise by the output signal den_latch of latch and the numerical value den_pipe of the 2nd and the 1st, register
[2:1] it is deposited after splicing.
The system of the present invention that cross clock domain signal transmission is realized using latch the advantage is that and be put using band simultaneously
Position and the latch resetted transmit data, and simple in structure, data transmission is unrelated with clock frequency.The prior art is in cross clock domain
In signal transmission design, it can avoid using latch as possible, especially while the latch with set and reset, and the present invention is just
It is that this latch is utilized to reset but also the characteristics of set, is transmitted signal using the port of set and reset, without
It is to use the conventional method that data are transmitted by clock/data terminal (clock, data).
Description of the drawings
Fig. 1 is the schematic diagram of the system of the present invention that cross clock domain signal transmission is realized using latch；
Fig. 2 is the sequence diagram of example signal in system of the present invention.
Specific embodiment
The present invention system, using simultaneous with asynchronous set (set) and reset (reset) latch (latch) come
Realize the cross clock domain transmission of signal.
Referring to shown in Fig. 1, Fig. 2 and cooperation table 1, a latch is equipped in system of the invention, it includes a set-resets
Latch module (set-reset latch), the set-reset latch module have set end lat_set_b, reset terminal lat_
Rst_b, output terminal q, clock signal input terminal CK；Wherein, clock signal input terminal CK inputs the clock signal of slow clock domain
aclk；Output terminal q also serves as the output terminal of entire latch, and output signal den_latch to one is made of d type flip flop
Three bit register den_pipe [2:0].
The latch also has the first input end rst1_b of low level active homing, and input is failing edge triggering
Signal cfg_reset_b；Second input terminal set2 of the effective set of high level, input are signal den；High level active homing
Third input terminal rst3, input is clear signals (reset signal) clr_den_latch, by the 1st den_ of register
Output signal dre_aclk at pipe [1] is as the clear signals.
Wherein, when the signal cfg_reset_b for inputting first input end rst1_b is low level, register is with three two
000 assignment of system number, otherwise by the output signal den_latch of latch and the 2nd and the 1st den_pipe [2 of register:
1] numerical value obtained by being spliced is deposited.
First input end rst1_b, the second input terminal set2 are respectively connected to the input of first and door, and first is defeated with door
Go out to be connected to the set end lat_set_b of set-reset latch module by the first NOT gate, thus by input terminal set2 and rst1_
Signal step-by-step at b inputs set end lat_set_b with the result negated after calculating, and signal is low at set end lat_set_b
During level, output terminal q obtains 1 (high level).
First input end rst1_b is connected to first or one of door input by the second NOT gate, first or door another
Input is connect with second with the output of door, the second input terminal set2 by third NOT gate be connected to this second with one of door it is defeated
Enter, third input terminal rst3 and second and another input of door connect.Described first or the output of door connected by the 4th NOT gate
Be connected to the reset terminal lat_rst_b of set-reset latch module, so as to by " numerical value that signal negates at input terminal rst1_b " with
And " signal step-by-step and the numerical value after calculating at the input terminal rst3 and set2 negated " carries out step-by-step or calculates taking for acquired results
When signal is low level at converse value input reset terminal lat_rst_b, reset terminal lat_rst_b, output terminal q obtains 0 (low level).
Output signal dre_aclk at the 1st den_pipe [1] of the register by the 5th NOT gate connect third with
One input of door, another input of output signal connection third and door at the 0th den_pipe [0] of register, this
Three and door output signal drdy_aclk, so as to pass through numerical value and the 0th, the register that the 1st den_pipe [1] of register negates
Den_pipe [0] numerical value carries out step-by-step with the result of calculating as output signal drdy_aclk.
In the system of the present invention, the signal den that need to be transmitted is inputted, will be latched via the second input terminal set2 of latch
Device set so that latch output is 1, has thus successfully adopted the pulse signal of signal den, has then utilized slow clock domain
Clock aclk adopt the output signal den_latch of latch, while generate the clear signals clr_den_ of latch
Latch, the clear signals pass to the reset terminal of latch through third input terminal rst3, by latch reset clear 0.If it needs
Want the aclk signals of a clock cycle, then system of the invention can provide output signal drdy_aclk adaptable therewith,
Realize the cross clock domain transmission of signal.
The example code of 1 system hardware description language of table
Although present disclosure is discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for the present invention's
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (6)
1. a kind of system that cross clock domain signal transmission is realized using latch, which is characterized in that
The system is equipped with the latch using the first clock domain clock aclk, and signal to be transmitted is inputted to the latch
Den makes the latch set, and the signal den_latch of latch output is connected to a three bit register den_pipe [2:
0], by reset signal of the signal of the 1st den_pipe [1] output of register as latch, being input to latch makes it multiple
Position.
2. the system as claimed in claim 1, which is characterized in that
The latch includes set-reset latch module, and the set-reset latch module has set end lat_set_b, multiple
Position end lat_rst_b, output terminal q, clock signal input terminal CK；Wherein, the first clock domain clock aclk is input to clock signal
Input terminal CK；The output terminal q carrys out output signal den_latch as the output terminal of latch；
The latch, comprising：The first input end rst1_b of low level active homing, signal of the input for failing edge triggering
cfg_reset_b；Second input terminal set2 of the effective set of high level, input are signal den；The of high level active homing
Three input terminal rst3, input are reset signal；
The signal step-by-step of the first input end rst1_b and the second input terminal set2 inputted with the result negated after calculating
When signal is low level at the set end lat_set_b, set end lat_set_b, 1 is obtained in output terminal q；
Signal carries out and the number after calculating with signal step-by-step at the second input terminal set2 negated at the third input terminal rst3
Value, then the numerical value step-by-step negated with signal at the first input end rst1_b are carried out or are calculated, and will or be calculated acquired results and are taken
When signal is low level at the input reset terminal lat_rst_b after anti-, reset terminal lat_rst_b, 0 is obtained in output terminal q.
3. system as claimed in claim 2, which is characterized in that
The first input end rst1_b, the second input terminal set2 are respectively connected to the input port of first and door, and first and door
Output port be connected to the set end lat_set_b of the set-reset latch module by the first NOT gate.
4. system as claimed in claim 2, which is characterized in that
The first input end rst1_b is connected to an input port of first or door by the second NOT gate, first or door it is another
One input port is connect with second with the output port of door, the second input terminal set2 by third NOT gate be connected to this second with
One input port of door, third input terminal rst3 are connect with second with another input port of door；Described first or door
Output port is connected to the reset terminal lat_rst_b of the set-reset latch module by the 4th NOT gate.
5. system as claimed in claim 1 or 2, which is characterized in that
The signal dre_aclk exported at the 1st den_pipe [1] of the register connects third and door by the 5th NOT gate
One input port, the signal connection third and another input port of door exported at the 0th den_pipe [0] of register,
In the third signal drdy_aclk corresponding with second clock domain clock is obtained with the output port of door.
6. system as claimed in claim 2, which is characterized in that
When the signal cfg_reset_b of the first input end rst1_b inputs is low level, register is with triad number
000 assignment, otherwise by the output signal den_latch of latch and the numerical value den_pipe [2 of the 2nd and the 1st, register:
1] it is deposited after splicing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611116237.1A CN108170616B (en) | 2016-12-07 | 2016-12-07 | System for realizing clock domain crossing signal transmission by using latch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611116237.1A CN108170616B (en) | 2016-12-07 | 2016-12-07 | System for realizing clock domain crossing signal transmission by using latch |
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| Publication Number | Publication Date |
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| CN108170616A true CN108170616A (en) | 2018-06-15 |
| CN108170616B CN108170616B (en) | 2020-03-31 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201611116237.1A Active CN108170616B (en) | 2016-12-07 | 2016-12-07 | System for realizing clock domain crossing signal transmission by using latch |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111985174A (en) * | 2020-09-03 | 2020-11-24 | 中科院微电子研究所南京智能技术研究院 | RT latch and latch method |
| CN113054996A (en) * | 2021-03-18 | 2021-06-29 | 明峰医疗系统股份有限公司 | Circuit and method for low-delay continuous clock domain crossing inside CT control board |
| CN114928413A (en) * | 2021-12-30 | 2022-08-19 | 厦门优迅高速芯片有限公司 | Signal monitoring method and circuit |
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| CN101009487A (en) * | 2007-01-24 | 2007-08-01 | 华为技术有限公司 | Cross-clock domain asynchronous data processing, cross-clock domain method of the asynchronous data, and its device |
| CN101694991A (en) * | 2009-10-22 | 2010-04-14 | 浙江大学 | Circuit for realizing synchronization of asynchronous pulse signals with random pulse width |
| CN102684814A (en) * | 2011-03-09 | 2012-09-19 | 安凯(广州)微电子技术有限公司 | Method, device and system for transmitting signals crossing clock domains |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101009487A (en) * | 2007-01-24 | 2007-08-01 | 华为技术有限公司 | Cross-clock domain asynchronous data processing, cross-clock domain method of the asynchronous data, and its device |
| CN101694991A (en) * | 2009-10-22 | 2010-04-14 | 浙江大学 | Circuit for realizing synchronization of asynchronous pulse signals with random pulse width |
| CN102684814A (en) * | 2011-03-09 | 2012-09-19 | 安凯(广州)微电子技术有限公司 | Method, device and system for transmitting signals crossing clock domains |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111985174A (en) * | 2020-09-03 | 2020-11-24 | 中科院微电子研究所南京智能技术研究院 | RT latch and latch method |
| CN111985174B (en) * | 2020-09-03 | 2023-07-18 | 中科南京智能技术研究院 | RT latch and latching method |
| CN113054996A (en) * | 2021-03-18 | 2021-06-29 | 明峰医疗系统股份有限公司 | Circuit and method for low-delay continuous clock domain crossing inside CT control board |
| CN113054996B (en) * | 2021-03-18 | 2022-05-10 | 明峰医疗系统股份有限公司 | Circuit and method for low-delay continuous clock domain crossing inside CT control board |
| CN114928413A (en) * | 2021-12-30 | 2022-08-19 | 厦门优迅高速芯片有限公司 | Signal monitoring method and circuit |
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| CN108170616B (en) | 2020-03-31 |
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