CN101009487A - Cross-clock domain asynchronous data processing, cross-clock domain method of the asynchronous data, and its device - Google Patents
Cross-clock domain asynchronous data processing, cross-clock domain method of the asynchronous data, and its device Download PDFInfo
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Abstract
The invention provides a across clock domain asynchronous data process method and device, asynchronous data across clock domain method and device, said across clock domain asynchronous data process method includes: Sampling the data signal to obtain the data signal which belongs to the first clock area; said data signal of the first clock area is asynchronously processed to obtain the data signal which belongs to the second clock area; said data signal of the second clock area is transferred to the second clock area in single point; the data signal of the second clock area is combinational logically processed and output the logical result. The technique scheme of the invention decreases the probability of metastable state that when data signal is transferred from one clock area to anther clock area, it resolves the condition that logical output error generated by different time delay, the stability of circuit is greatly improved.
Description
Technical field
The present invention relates to the communications field, especially a kind of cross-clock domain asynchronous data processing method and device, asynchronous data cross clock domain method and device.
Background technology
In the digital circuitry of complexity, whole system often is made up of a plurality of unit or a plurality of printed circuit board (PCB), therefore at application-specific integrated circuit (ASIC) (ASIC, Application Specific Integrated Circuit) and field programmable gate array (FPGA, Field Programmable Gate Array) in the logical design, tend to relate to the mutual of signal between two clock zones or a plurality of clock zone, whether the interaction process of signal is perfect, whether reliable and stable whether the data that are cross clock domain can be stabilized sampling, be one of ASIC and FPGA design key factor.
A kind of processing method of cross-clock domain asynchronous data is arranged at present, see also Fig. 1, clock signal clk 1 is the clock signal that is adopted in first clock zone, the clock signal of clock signal clk 2 for being adopted in the second clock territory.The data-signal D that belongs to first clock zone obtains data-signal Q after trigger 111 latchs, described data-signal Q is sent to combinational logic 112 and combinational logic 113, generate data-signal D1 and D2 respectively, described data-signal D1 and D2 are sent to the trigger 121 and 122 in the second clock territory respectively, generated data-signal Q1 and the Q2 that belongs to the second clock territory by clock signal clk 2 sampling backs, the combinational logic 123 that described data-signal Q1 and Q2 are sent to the second clock territory again carries out the combinational logic processing, generates data-signal D '.Data-signal is not carried out synchronization process in the processing method of described cross clock domain data-signal, data-signal D1 and D2 are sent to described trigger 121 and 122, directly exported to the combinational logic 123 in the second clock territory after clock signal clk 2 samplings, do not pass through clock signal clk 2 synchronization process, this moment, data-signal Q1 and Q2 may be in metastable state, it is unsure state, therefore the data-signal D ' that carries out obtaining after the logical process via combinational logic 123 may be insecure, and insecure data-signal can cause the fault of chip, influences the equipment operate as normal.And, the data-signal D that belongs to first clock zone is respectively through being passed in the second clock territory after two combinational logics 112 and 113 processing again, if combinational logic 112 is different with 113 time-delay, carry out combinational logic by the data-signal Q1 of combinational logic 112 and 113 outputs and Q2 through combinational logic 123 and handle the result of back gained and will produce unusually, thus generation anomaly when causing the data-signal cross clock domain.
Fig. 2 is the data signal waveforms figure of the processing method of employing prior art cross-clock domain asynchronous data.As seen from Figure 2, the data-signal Q1 that does not obtain after by clock signal clk 2 samplings in second clock territory through the data-signal D1 of clock signal clk 2 synchronization process is in the metastable state state.Because combinational logic 112 is different with 113 time-delay, inequality from the sequential of combinational logic 112 and 113 data-signal D1 that export and D2, and because data-signal Q1 is in metastable state, be that data-signal Q1 may sample an improper value, therefore the sequential of data-signal Q1 and Q2 is inequality, different and when being in metastable data-signal Q1 and Q2 input combinational logic 3 when sequential, can cause the data-signal output of combinational logic 3 unreliable, influence the operate as normal of chip.
In sum, adopt the processing method of prior art cross-clock domain asynchronous data, because the asynchronous data signal to cross clock domain does not carry out synchronization process, and the mode that when transmission of data signals, adopts multicast communication, make the data-signal that transfers to another clock zone produce the metastable state phenomenon, even cause the combinational logic output error result of another clock zone, influence the operate as normal of chip.
Summary of the invention
The problem that the embodiment of the invention will solve is to provide a kind of cross-clock domain asynchronous data processing method and device, asynchronous data cross clock domain method and device, produce metastable state with the data-signal of avoiding cross clock domain, and carry out producing output error behind the combinational logic.
For solving the problems of the technologies described above, the objective of the invention is to be achieved through the following technical solutions:
The embodiment of the invention provides a kind of processing method of cross-clock domain asynchronous data, and it comprises:
Data-signal is sampled, obtain belonging to the data-signal of first clock zone;
Data-signal to described first clock zone carries out synchronization process, obtains the data-signal in second clock territory;
The data-signal in described second clock territory is delivered to the second clock territory by single-point;
Data-signal to described second clock territory carries out combinational logic processing, output logic result.
The embodiment of the invention also provides a kind of processing unit of cross-clock domain asynchronous data, and it comprises:
Sampling unit is used for data-signal is sampled, and obtains belonging to the data-signal of first clock zone;
The synchronization process unit is used for the data-signal of described first clock zone is carried out synchronization process, obtains belonging to the data-signal in second clock territory;
Output is used for the data-signal single-point in described second clock territory is passed to the second clock territory;
The combinational logic device is used for data-signal to the described second clock territory that receives and carries out combinational logic and handle, and the output logic result.
The embodiment of the invention also provides a kind of method of asynchronous data cross clock domain, and it comprises:
Data-signal is sampled, obtain belonging to the data-signal of first clock zone;
Data-signal to described first clock zone carries out synchronization process, obtains the data-signal in second clock territory;
The data-signal in described second clock territory is delivered to the second clock territory by single-point.
The embodiment of the invention also provides a kind of device of asynchronous data cross clock domain, and it comprises:
Sampling unit is used for data-signal is sampled, and obtains belonging to the data-signal of first clock zone;
The synchronization process unit is used for the data-signal of described first clock zone is carried out synchronization process, obtains belonging to the data-signal in second clock territory;
Output is used for the data-signal single-point in described second clock territory is passed to the second clock territory.
In sum, the method of the processing method of the cross-clock domain asynchronous data that the embodiment of the invention provides and device, asynchronous data cross clock domain and device, being undertaken after the synchronization process again by the data-signal to cross clock domain, single-point is passed to another clock zone, effectively reduce data-signal when a clock zone is passed to another clock zone, metastable probability appears in signal, solved because of the different situations that cause the output error result of combinatorial logic unit time-delay, greatly improved the stability of circuit.
Description of drawings
Fig. 1 is the structure chart of prior art cross-clock domain asynchronous data processing unit;
Fig. 2 is the data-signal sequential chart of the processing method of employing prior art cross-clock domain asynchronous data;
Fig. 3 is the structure chart of the device preferred embodiment of cross-clock domain asynchronous data processing of the present invention;
Fig. 4 is the flow chart of the processing method preferred embodiment of cross-clock domain asynchronous data of the present invention;
Fig. 5 is the data-signal sequential chart of the processing method of employing cross-clock domain asynchronous data of the present invention.
Embodiment
The embodiment of the invention provides a kind of asynchronous data cross clock domain method and device, cross-clock domain asynchronous data processing method and device.
For making the present invention more cheer and bright, describe the present invention below in conjunction with execution mode and accompanying drawing.
Please refer to Fig. 3, be the structure chart of cross-clock domain asynchronous data processing unit of the present invention preferred embodiment.Described cross-clock domain asynchronous data processing unit comprises asynchronous data cross clock domain device 3, with combinational logic device 4.
Described asynchronous data cross clock domain device 3 comprises sampling unit 30, synchronization process unit 31 and a signal output part 32.
Described sampling unit 30 is used for the data-signal D of input is sampled, and obtains belonging to the data-signal Q of first clock zone after the sampling, and sampled signal is first clock signal clk 1 of first clock zone.Described sampling unit 30 can adopt trigger.
Described synchronization process unit 31 is used for the data-signal Q of first clock zone is carried out synchronization process, it comprises first order trigger 311 and second level trigger 312, described first order trigger 311 is used for latching according to the data-signal Q of latch signal to first clock zone of input, described latch signal is the second clock signal CLK2 in second clock territory, described data-signal Q waits for complete clock cycle of second clock signal CLK2 in first order trigger device 311, the metastable state of data-signal is decayed, obtain data-signal Q1; Described second level trigger 312 is used for according to sampled signal described data-signal Q1 being sampled, and sampling obtains belonging to the data-signal Q2 in second clock territory, and described sampled signal is second clock signal CLK2.
Described signal output part 32 is used for the data-signal Q2 single-point in described second clock territory is passed to described combinational logic device 4.
Described combinational logic device 4 belongs to the second clock territory, and be used for data-signal Q2 to the second clock territory that receives and carry out combinational logic and handle, the output combinational logic result, it comprises combinatorial logic unit 40,41 and 42, trigger 43 and 44.
Described combinatorial logic unit 40,41 is carried out combinational logic calculating to the data-signal in second clock territory respectively, obtains data-signal D1, D2, and exports described data-signal D1, D2 to trigger 43 and 44 respectively.
Described trigger 43 and 44 is respectively applied for data-signal D1, D2 that combinational logic is calculated and samples, obtain data-signal Q3, Q4, described sampled signal is the second clock signal CLK2 in second clock territory, and exports described data-signal Q3, Q4 to combinatorial logic unit 42.
Described combinatorial logic unit 42 is used for that described data-signal Q3, Q4 are carried out combinational logic to be calculated, and the output logic result.
Owing to combinatorial logic unit the 40, the 41st, belong to the combinatorial logic unit in second clock territory, data-signal D1, the D2 of its output satisfies trigger 43 requirement consistent with 44 sequential, therefore the sequential by trigger 43 and 44 data-signal Q3 that export and Q4 is identical, and after the synchronization process through the two-stage trigger, resulting data-signal Q3 and Q4 are effectively stable, so combinational logic 42 receives described data-signal Q3 and Q4 can access correct data-signal D ' through after the logical process.
Please refer to Fig. 4, be the flow chart of the processing method preferred embodiment of cross-clock domain asynchronous data of the present invention.Described method comprises:
Step 401: data-signal is sampled by the clock signal of first clock zone, obtains belonging to the data-signal of first clock zone;
Step 402: the data-signal to described first clock zone carries out synchronization process, obtains the data-signal in second clock territory;
Described synchronization process comprises: latch according to the data-signal of latch signal with described first clock zone, the metastable state of data-signal is decayed, described latch signal is the second clock signal in second clock territory; According to sampled signal the data-signal after the metastable state decay is sampled, obtain one stable, effectively and belong to the data-signal in second clock territory, described sampled signal is the second clock signal in second clock territory.
Step 403: the data-signal in described second clock territory is delivered to the combinational logic device in second clock territory by single-point;
Step 404: described combinational logic device carries out the combinational logic processing to the data-signal in second clock territory, exports reliable and stable logical process result;
Described combinational logic is handled and is comprised: the data-signal in described second clock territory is carried out combinational logic calculating respectively, obtain data-signal; Combinational logic is calculated the data-signal of gained and sample respectively, the back data-signal that obtains sampling, sampled signal is the second clock signal in second clock territory; Data-signal after the sampling is carried out combinational logic calculate, obtain reliable and stable logic output result.
Adopted the two-stage trigger that the data-signal of cross clock domain is carried out synchronization process in the preferred embodiment of the present invention, also can adopt simultaneously multistage triggers such as three grades, level Four to carry out synchronization process, wherein what trigger of front is used for the metastable state of attenuation data signal, data-signal after the afterbody trigger is decayed to metastable state is sampled, and obtains stabilizing effective data-signal.
Please refer to Fig. 5, be the data-signal sequential chart of the processing method that adopts cross-clock domain asynchronous data of the present invention.As we can see from the figure, the data-signal Q2 after two-stage trigger synchronization process according to the clock signal Q2 in second clock territory synchronously and waveform stabilization.And owing to the data-signal of first clock zone is input to after the clock signal synchronization in second clock territory in the combinational logic device in second clock territory earlier again, and each combinatorial logic unit in the combinational logic device of second clock territory is all worked under the clock signal in second clock territory, even therefore the time-delay of two combinatorial logic unit is different, data-signal D1 after combinational logic is handled and the sequential of D2 also meet the demands, and resulting data-signal Q3 is identical with the Q4 sequential along the back of sampling at unified clock.
The cross-clock domain asynchronous data processing method and device, asynchronous data cross clock domain method and the device that provide by the embodiment of the invention, the data-signal of cross clock domain is carried out after the synchronization process single-point again to be passed to another clock zone and to carry out combinational logic and handle, effectively reduce data-signal when a clock zone is passed to another clock zone, metastable probability appears in signal, and solved because of the different situations that cause the logic output error of combinational logic time-delay, greatly improved the stability of circuit.
More than cross-clock domain asynchronous data processing method provided by the present invention and device, asynchronous data cross clock domain method and device are described in detail, used specific case herein principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (12)
1. a cross-clock domain asynchronous data processing method is characterized in that, described method comprises:
Data-signal is sampled, obtain belonging to the data-signal of first clock zone;
Data-signal to described first clock zone carries out synchronization process, obtains the data-signal in second clock territory;
The data-signal in described second clock territory is delivered to the second clock territory by single-point;
Data-signal to described second clock territory carries out combinational logic processing, output logic result.
2. cross-clock domain asynchronous data processing method according to claim 1 is characterized in that, the data-signal of described first clock zone is carried out synchronization process comprise:
Latch according to the data-signal of latch signal with described first clock zone, the metastable state of data-signal is decayed, described latch signal is the second clock signal in second clock territory;
According to sampled signal the data-signal after latching is sampled, obtain belonging to the data-signal in second clock territory, described sampled signal is the second clock signal in second clock territory.
3. cross-clock domain asynchronous data processing method according to claim 1 is characterized in that, the data-signal in second clock territory is carried out combinational logic handle and comprise:
The data-signal in described second clock territory is carried out combinational logic calculating respectively, obtain data-signal;
Combinational logic is calculated the data-signal of gained and sample respectively, the back data-signal that obtains sampling, sampled signal is the second clock signal in second clock territory;
Data-signal after the sampling is carried out combinational logic calculate the output logic result.
4. a cross-clock domain asynchronous data processing unit is characterized in that, described device comprises:
Sampling unit is used for data-signal is sampled, and obtains belonging to the data-signal of first clock zone;
The synchronization process unit is used for the data-signal of described first clock zone is carried out synchronization process, obtains belonging to the data-signal in second clock territory;
Output is used for the data-signal single-point in described second clock territory is passed to the second clock territory;
The combinational logic device is used for data-signal to the described second clock territory that receives and carries out combinational logic and handle, and the output logic result.
5. cross-clock domain asynchronous data processing unit according to claim 4 is characterized in that, described sampling unit is a trigger.
6. cross-clock domain asynchronous data processing unit according to claim 4, it is characterized in that, described synchronization process unit comprises two-stage trigger at least, wherein the one-level trigger is used for according to latch signal data-signal being latched, the metastable state of attenuation data signal, described latch signal is the second clock signal in second clock territory, another grade trigger is used for according to sampled signal the data-signal after latching being sampled, obtain the data-signal in second clock territory, described sampled signal is the second clock signal in second clock territory.
7. cross-clock domain asynchronous data processing unit according to claim 4, it is characterized in that, described combinational logic device comprises combinatorial logic unit and trigger, described combinatorial logic unit is used for the data-signal of input is carried out combinational logic calculating, and described trigger is used for the data-signal that combinational logic calculates is sampled.
8. an asynchronous data cross clock domain method is characterized in that, described method comprises:
Data-signal is sampled, obtain belonging to the data-signal of first clock zone;
Data-signal to described first clock zone carries out synchronization process, obtains the data-signal in second clock territory;
The data-signal in described second clock territory is delivered to the second clock territory by single-point.
9. asynchronous data cross clock domain method according to claim 8 is characterized in that, the data-signal of described first clock zone is carried out synchronization process comprise:
Latch according to the data-signal of latch signal with described first clock zone, the metastable state of data-signal is decayed, described latch signal is the second clock signal in second clock territory;
According to sampled signal the data-signal after latching is sampled, obtain belonging to the data-signal in second clock territory, described sampled signal is the second clock signal in second clock territory.
10. an asynchronous data cross clock domain device is characterized in that, described device comprises:
Sampling unit is used for data-signal is sampled, and obtains belonging to the data-signal of first clock zone;
The synchronization process unit is used for the data-signal of described first clock zone is carried out synchronization process, obtains belonging to the data-signal in second clock territory;
Output is used for the data-signal single-point in described second clock territory is passed to the second clock territory.
11. asynchronous data cross clock domain device according to claim 10 is characterized in that, described sampling unit is a trigger.
12. asynchronous data cross clock domain device according to claim 10, it is characterized in that, described synchronization process unit comprises two-stage trigger at least, wherein the one-level trigger is used for according to latch signal data-signal being latched, the metastable state of attenuation data signal, described latch signal is the second clock signal in second clock territory, another grade trigger is used for according to sampled signal the data-signal after latching being sampled, obtain the data-signal in second clock territory, described sampled signal is the second clock signal in second clock territory.
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| CN102447477A (en) * | 2010-10-15 | 2012-05-09 | 珠海全志科技股份有限公司 | Real-time conversion transmission method and device of parallel-series data stream for cross asynchronous clock domain |
| CN102789262A (en) * | 2012-07-19 | 2012-11-21 | 中国航天科技集团公司第九研究院第七七一研究所 | Clock zone spanning asynchronous signal synchronization circuit |
| CN103376397A (en) * | 2012-04-19 | 2013-10-30 | 安凯(广州)微电子技术有限公司 | Detection system for asynchronous circuit |
| CN103576738A (en) * | 2012-08-01 | 2014-02-12 | 中兴通讯股份有限公司 | Method and device for clock domain crossing processing of asynchronous signals |
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| CN105607689A (en) * | 2015-12-22 | 2016-05-25 | 邓晨曦 | High-speed multiphase clock synchronization method |
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| CN102447477B (en) * | 2010-10-15 | 2014-05-07 | 珠海全志科技股份有限公司 | Real-time conversion transmission method and device of parallel-series data stream for cross asynchronous clock domain |
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| CN102789262A (en) * | 2012-07-19 | 2012-11-21 | 中国航天科技集团公司第九研究院第七七一研究所 | Clock zone spanning asynchronous signal synchronization circuit |
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| CN110572335B (en) * | 2019-08-30 | 2021-07-23 | 中国人民解放军战略支援部队信息工程大学 | Low-delay clock domain structure of switching chip |
| CN112000173A (en) * | 2020-08-20 | 2020-11-27 | 天津飞腾信息技术有限公司 | Method and system for checking multi-bit signal timing violation across clock domains |
| CN112526155A (en) * | 2020-11-16 | 2021-03-19 | 中国航空工业集团公司西安航空计算技术研究所 | Configurable rotating speed signal acquisition method |
| CN112817906A (en) * | 2021-02-05 | 2021-05-18 | 中国电子科技集团公司第五十八研究所 | Clock domain system of interconnected bare cores and management method thereof |
| CN113821075A (en) * | 2021-09-27 | 2021-12-21 | 上海航天计算机技术研究所 | Clock domain crossing processing method and device for asynchronous multi-bit signal |
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