CN101493716B - Signal synchronization method for asynchronous interface, circuit and asynchronous chip - Google Patents
Signal synchronization method for asynchronous interface, circuit and asynchronous chip Download PDFInfo
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- CN101493716B CN101493716B CN2008100566822A CN200810056682A CN101493716B CN 101493716 B CN101493716 B CN 101493716B CN 2008100566822 A CN2008100566822 A CN 2008100566822A CN 200810056682 A CN200810056682 A CN 200810056682A CN 101493716 B CN101493716 B CN 101493716B
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Abstract
The invention discloses a signal synchronous circuit of an asynchronous interface, comprising an external latch module used for adopting an input clock domain to latch a received external input signal so as to generate a first signal, an internal latch module used for adopting an output clock domain to latch the first signal in a multi-level manner so as to get a first input-end signal effectively-latched in the last level, a feedback module used for adopting the input clock domain to latch the first input-end signal in a multi-level manner to generate a feedback signal, and a synchronous signal generating module used for generating a synchronous signal according to the feedback signal. The invention also provides an asynchronous-interface signal synchronizing method and an asynchronous chip with high efficiency for the transmission of state and control signals.
Description
Technical field
The present invention relates to the simultaneous techniques of signal, relate in particular to a kind of signal synchronizing method, circuit and asynchronous chip of asynchronous interface.
Background technology
In chip design, chip interface comprises two kinds of sync cap and asynchronous interfaces, and so-called sync cap is meant the identical clock of inside and outside employing of chip interface, and so-called asynchronous interface is meant the different clock of inside and outside employing of chip interface.Adopt the chip of sync cap, the inner clock that directly uses the interface outside of its interface, chip performance is subjected to the restriction of the outside input clock of interface, and the power consumption of chip can't regulate and control; And because the identical clock of inside and outside employing of chip, but make the signal of chip exterior direct detection or precognition chip internal come into force constantly, illegal person can utilize this point that chip is carried out security attack, thereby causes the security hidden danger of chip.Adopt the chip of asynchronous interface, independently clock source is adopted in its interface inside, can solve the safety issue of above-mentioned sync cap chip, and the power consumption of the flexible configuration of chip, chip is convenient to regulate and the performance of control, chip is improved.Because asynchronous interface has above-mentioned advantage, chip of the prior art more and more adopts the design of asynchronous interface.
There is a kind of employing first in first out (FIFO in the prior art, First In First Out) circuit is realized the method for asynchronous interface data transmission, as shown in Figure 1, fifo circuit is divided into and writes clock zone and read the clock zone two ends, write clock zone and read clock zone and isolate mutually, writing the write operation that clock zone carries out data, carry out the read operation of data reading clock zone, write clock zone and read between the clock zone and communicate by half-full or full up signal, implementation procedure may further comprise the steps:
A, write clock zone by writing the write operation that counter carries out data, the data storage that writes is in storer, write the write state that the sign logical circuit is used for identification data, wherein, it is full up that FULL represents to write data, and it is half-full that HALF_FULL represents to write data, and for example: the storage size of storer is 1000 bytes, then when the data that write reach 500 bytes, be half-full; When the data that write reach 1000 bytes, be full up; Carried out the write operation of data before the data write state reaches HALF_FULL, read clock zone and be in waiting status this moment always, waits for receiving half-full or full up signal;
B, when the data that write reach half-full, write clock zone and produce half-full useful signal and send to and read clock zone, inform that reading clock zone can carry out the read operation of data;
C, read clock zone and carry out the read operation of data, run through up to data by read counter; Read to indicate that logical circuit is used for the reading state of identification data, wherein, EMPTY represents that data are for complete empty in the storer, and HALF_EMPTY represents that data are read the read operation that clock zone carries out data in midair in the storer, reaches EMPTY up to the data read state;
After d, data run through, read clock zone and enter waiting status, up to obtaining next half-full useful signal or full up signal.
Adopt the asynchronous interface of said method only to be suitable for the transmission of data, and are bulk transfer of discontinuity, can't carry out real-time Transmission data and signal to the transmission of data.When sending a small amount of useful signal, for guaranteeing the timely transmission of useful signal, also need to send a large amount of garbage signals and make storer reach half-full or full up state to trigger the transmission of useful signal, caused the waste of resource, transmission efficiency is not high.
In addition, when designing asynchronous chip according to the method described above, need to determine according to the actual requirements the realization door number of storer, storer realizes that the certain chip of door number only is suitable in certain data transmission weight range, and applicability is wideless.When being designed for the chip that carries out data transmission in enormous quantities, just need more storer to realize the door number, cost is higher, and chip area is bigger.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of signal synchronizing method, circuit and asynchronous chip of asynchronous interface, can't carry out signal real-time Transmission, state and the low problem of control signal transfer efficiency to asynchronous interface to solve prior art.
For achieving the above object, technical scheme of the present invention is achieved in that
Embodiments of the invention provide a kind of signal synchronization circuit of asynchronous interface, comprising:
The outer lock storing module is used for latching with the input clock territory by the external input signal that will receive and generates first signal;
The inner lock storage module is used for by described first signal is carried out multistage latching with the output clock zone, and what obtain that afterbody effectively latchs first goes into end signal;
Feedback module is used for carrying out multistage latching with described input clock territory and generating feedback signal by going into end signal with described first;
The synchronizing signal generation module is used for generating synchronizing signal according to described feedback signal, then described synchronizing signal is exported by signal output part after multistage latching.
Described feedback module comprises:
The signal latch submodule is used for going into end signal with described first and carries out multistage latching with described input clock territory, and what obtain that afterbody effectively latchs second goes into end signal and second and go out end signal;
Feedback signal generates submodule, is used for that described second inversion signal and described second that goes out end signal is gone into end signal and carries out logic and operation, and generate described feedback signal according to operation result.
Described synchronizing signal generation module comprises:
The rising edge detection sub-module is used for described synchronizing signal is carried out the detection of rising edge, and testing result is exported;
The negative edge detection sub-module is used for described synchronizing signal is carried out the detection of negative edge, and testing result is exported.
Embodiments of the invention also provide a kind of signal synchronizing method of asynchronous interface, comprising:
The external input signal that receives is latched with the input clock territory and generate first signal;
Described first signal is carried out multistage latching with the output clock zone, and what obtain that afterbody effectively latchs first goes into end signal;
Going into end signal with described first carries out multistage latching and generates feedback signal with described input clock territory;
Generate synchronizing signal according to described feedback signal, then described synchronizing signal is exported by signal output part after multistage latching.
Describedly go into end signal with first and carry out multistage latching with the input clock territory and generate feedback signal being specially:
Go into end signal with described first and carry out multistage latching with described input clock territory, what obtain that afterbody effectively latchs second goes into end signal and second and goes out end signal;
Described second inversion signal and described second that goes out end signal is gone into end signal carry out logic and operation, and generate described feedback signal according to operation result.
After described generation synchronizing signal, this method also comprises: described synchronizing signal is carried out the multistage back of latching with described output clock zone exported by signal output part.
After described generation synchronizing signal, this method also comprises: described synchronizing signal is carried out the detection of rising edge and negative edge, and testing result is exported.
The described detection that synchronizing signal is carried out rising edge and negative edge is specially: described synchronizing signal is carried out multistage latching with described output clock zone, what obtain that afterbody effectively latchs the 3rd goes into end signal and the 3rd and goes out end signal, the described the 3rd reverse signal and the described the 3rd that goes out end signal is gone into end signal carry out the rising edge that logic and operation detects described synchronizing signal; The described the 3rd reverse signal and the described the 3rd of going into end signal is gone out end signal carry out the negative edge that logic and operation detects described synchronizing signal.
Embodiments of the invention also provide a kind of asynchronous chip, comprise at least one asynchronous interface, and described asynchronous interface adopts signal synchronization circuit, and described signal synchronization circuit comprises:
The outer lock storing module is used for latching with the input clock territory by the external input signal that will receive and generates first signal;
The inner lock storage module is used for by described first signal is carried out multistage latching with the output clock zone, and what obtain that afterbody effectively latchs first goes into end signal;
Feedback module is used for carrying out multistage latching with described input clock territory and generating feedback signal by going into end signal with described first;
The synchronizing signal generation module is used for generating synchronizing signal according to described feedback signal, then described synchronizing signal is exported by signal output part after multistage latching.
Described feedback module comprises:
The signal latch submodule is used for going into end signal with described first and carries out multistage latching with described input clock territory, and what obtain that afterbody effectively latchs second goes into end signal and second and go out end signal;
Feedback signal generates submodule, is used for that described second inversion signal and described second that goes out end signal is gone into end signal and carries out logic and operation, and generate described feedback signal according to operation result.
Described synchronizing signal generation module comprises:
The rising edge detection sub-module is used for described synchronizing signal is carried out the detection of rising edge, and testing result is exported;
The negative edge detection sub-module is used for described synchronizing signal is carried out the detection of negative edge, and testing result is exported.
Signal synchronizing method that embodiments of the invention provide and circuit, adopt multistage latch with external input signal by input clock territory synchronous transmission to output clock zone, higher to the transfer efficiency of state and control signal; And generate feedback signal by feedback circuit and in time feed back, guarantee that output signal reaches consistent with input signal, thereby avoid the appearance of not stationary state.Embodiments of the invention are applied in the chip design, make that the design for Measurability (DFT, Design For Test) of chip is simple, and the detecting operation of chip is easier, has also reduced the detection cost, has improved detection efficiency; And the inner structure of the signal synchronization circuit that embodiments of the invention provided is simple, adopts circuit component less, thereby makes production cost lower.
Description of drawings
Fig. 1 is the Synchronization Design synoptic diagram of asynchronous interface in the prior art;
Fig. 2 is that the signal synchronization circuit of a kind of asynchronous interface of embodiments of the invention is formed structural representation;
Fig. 3 is the signal synchronizing method process flow diagram of a kind of asynchronous interface of embodiments of the invention;
Fig. 4 is the signal synchronization circuit synoptic diagram of a kind of asynchronous interface of embodiments of the invention.
Embodiment
The technical solution of the present invention is further elaborated below in conjunction with the drawings and specific embodiments.
The signal synchronizing method of the embodiment of the invention is a signalization synchronizing circuit on asynchronous interface, by this signal synchronization circuit with external input signal by input clock territory synchronous transmission to output clock zone.The composition structure of the signal synchronization circuit of embodiments of the invention as shown in Figure 2, this circuit comprises: outer lock storing module 100, inner lock storage module 200, feedback module 300 and synchronizing signal generation module 400.Wherein, outer lock storing module 100 connects signal input part 500, adopts the input clock territory, is used for the external input signal from signal input end 500 latched with the input clock territory and generates first signal and offer inner lock storage module 200; Inner lock storage module 200, connect outer lock storing module 100 and signal output part 600, inner lock storage module 200 is made up of multistage latch, multistage latch adopts the output clock zone, be used for first signal is carried out multistage latching with the output clock zone, what obtain that afterbody effectively latchs first goes into end signal and offers feedback module 300; Feedback module 300, connect inner lock storage module 200, be made up of multistage latch and logic gates, multistage latch adopts the input clock territory, is used for going into end signal with first and latchs the back with the input clock territory and offer synchronizing signal generation module 400 by logic gates computing generation feedback signal; Synchronizing signal generation module 400 connects feedback module 300 and inner lock storage module 200, and the feedback signal generation synchronizing signal that is used for providing according to feedback module 300 offers inner lock storage module 200 and carries out the multistage back of latching by signal output part 600 outputs.
Synchronizing signal generation module 400 further comprises: rising edge detection sub-module 410 and negative edge detection sub-module 420; Wherein, rising edge detection sub-module 410 is used for that synchronizing signal is carried out rising edge and detects, and testing result is exported; Negative edge detection sub-module 420 is used for that synchronizing signal is carried out negative edge and detects, and testing result is exported.
Embodiments of the invention also provide a kind of asynchronous chip, and this asynchronous chip comprises at least one asynchronous interface, and its asynchronous interface adopts signal synchronization circuit shown in Figure 2.
Signal Synchronization flow process by above-mentioned signal synchronization circuit shown in Figure 2 is carried out as shown in Figure 3, mainly may further comprise the steps:
During external input signal entering signal synchronizing circuit, adopt input clock territory that external input signal is latched and generate first signal by this signal synchronization circuit.
First signal that is latched the back generation by the input clock territory adopts the output clock zone to carry out multistage latching by multistage latch again, what obtain that afterbody effectively latchs first goes into end signal, adopt multistage latch to carry out the multistage accurate transmission that can guarantee signal of latching, avoid producing the signal of not stationary state and cause the situation of circuit malfunction to occur.In actual applications, adopt three grades of latchs can realize the accurate transmission of signal preferably.
Step 303 is gone into end signal with first and is carried out multistage latching and generate feedback signal through the input clock territory.
Go into end signal with first and carry out multistage latching with the input clock territory, what obtain that afterbody effectively latchs second goes into end signal and second and goes out end signal, then second inversion signal and second that goes out end signal is gone into end signal and carry out logic and operation, and generate feedback signal according to operation result.
Step 304 generates synchronizing signal according to feedback signal.
According to the feedback signal that generates, generate synchronizing signal by signal selector, this synchronizing signal is exported by signal output part after the output clock zone carries out multistage latching.
Signal synchronization circuit synoptic diagram below in conjunction with a kind of asynchronous interface of embodiments of the invention shown in Figure 4 further elaborates.Adopt three grades of latchs among Fig. 4, Clk_in represents the input clock territory, and Clk_out represents to export clock zone, and Reset represents asynchronous reset signal.External input signal Sync_in handles the process that obtains synchronizing signal through this signal synchronization circuit and mainly may further comprise the steps:
Step 401, external input signal Sync_in are latched as Sync_in_reg1 by input clock territory latch InReg.
External input signal Sync_in at first passes through latch InReg by IN end entering signal synchronizing circuit, and latch InReg adopts the input clock territory that Sync_in is latched, and the output signal that obtains latch InReg is Sync_in_reg1.
Step 402, signal Sync_in_reg1 are latched as Sync_in_reg2 by input clock territory latch InLckReg after the signal selector Mux2 of alternative output.
Signal sync_in_reg1 via a logic sum gate OR2_1 after output signal be OR2_1_out; OR2_1_out is transferred to signal selector Mux2 again, and the output signal of process signal selector Mux2 is Sync_in_d2; Sync_in_d2 enters latch InLckReg, adopts the input clock territory that sync_in_d2 is latched by latch InLckReg, and the output signal that obtains latch InLckReg is Sync_in_reg2.
Step 403, signal Sync_in_reg2 are latched as Sync0_out via first order output clock zone latch Sync0.
Signal Sync_in_reg2 enters latch Sync0, and latch Sync0 adopts the output clock zone that Sync_in_reg2 is latched, and the output signal that obtains latch Sync0 is Sync0_out.In addition, by shown in Figure 4, signal Sync_in_reg2 also need turn back to logic sum gate OR2_1, carries out the logical OR computing as input and the signal sync_in_reg1 of logic sum gate OR2_1, and the signal that generates after the logical OR computing offers signal selector Mux2.
Step 404, signal Sync0_out are latched as Sync1_out via second level output clock zone latch Sync1.
Signal Sync0_out enters latch Sync1, and latch Sync1 adopts the output clock zone that Sync0_out is latched, and the output signal that obtains latch Sync1 is Sync1_out.
Step 405, signal Sync1_out are latched as Sync2_out via third level output clock zone latch Sync2.
Signal Sync1_out enters latch Sync2, and latch Sync2 adopts the output clock zone that Sync1_out is latched, and the output signal that obtains latch Sync2 is Sync2_out.
Step 406, signal Sync1_out are latched as FbSync0_out via first order input clock territory latch FbSync0.
Signal Sync1_out enters latch FbSync0, and latch FbSync0 adopts the input clock territory that Sync1_out is latched, and the output signal that obtains latch FbSync0 is FbSync0_out.
Step 407, signal FbSync0_out are latched as FbSync1_out via input clock territory, second level latch FbSync1.
Signal FbSync0_out enters latch FbSync1, and latch FbSync1 adopts the input clock territory that FbSync0_out is latched, and the output signal that obtains latch FbSync1 is FbSync1_out.
Step 408, signal FbSync1_out are latched as FbSync2_out via third level input clock territory latch FbSync2.
Signal FbSync1_out enters latch FbSync2, and latch FbSync2 adopts the input clock territory that FbSync1_out is latched, and the output signal that obtains latch FbSync2 is FbSync2_out.
Step 409, signal FbSync1_out and FbSync2_out carry out logical operation through a logical AND gate Nand2 who has the reverse input of an end, generate feedback signal Sync_in_d2_se and feed back to signal selector Mux2.
The reverse signal of signal FbSync1_out and signal FbSync2_out carries out logic and operation generation feedback signal Sync_in_d2_se and feeds back to signal selector Mux2.
If feedback signal Sync_in_d2_se is 1, then the synchronizing signal Sync_in_d2 of Sheng Chenging is 0; If feedback signal Sync_in_d2_se is 0, then to be signal Sync_in_reg1 and Sync_in_reg2 carry out output result after the logical OR computing via logic sum gate OR2_1 to the synchronizing signal Sync_in_d2 of Sheng Chenging.
Step 411, synchronizing signal Sync_in_d2 are via the output of OUT end.
Be latched as the Sync_in_reg2 in the new moment through latch InLckReg by the synchronizing signal Sync_in_d2 of signal selector Mux2 generation, be latched as the Sync0_out in the new moment again through latch Sync0, be latched as the Sync1_out in the new moment then through latch Sync1, signal Sync1_out is the final Sync_out_reg2 as a result that exports synchronously of synchronizing circuit from the output of OUT end.
Step 412, synchronizing signal is carried out the detection of rising edge and negative edge, and testing result is exported.
Shown in circuit among Fig. 4, the reverse signal of signal Sync1_out and signal Sync2_out is carried out logic and operation, can detect rising edge signal Sync_out_p1, because as can be known by logical operation, having only the signal Sync1_out of working as is 1, signal Sync2_out is 0 o'clock, logic operation result sync_out_p1 just is effective output of 1, yet it is last from the time of signal transmission, signal Sync2_out is than the first arrival of signal Sync1_out signal output part, can think that for continuous signal signal is to have jumped to 1 by 0, signal jumps to the signal that promptly had rising edge at 1 o'clock by 0.
Reverse signal and the signal Sync2_out of signal Sync1_out are carried out logic and operation, can detect negative edge signal Sync_out_p2, because as can be known by logical operation, having only the signal Sync1_out of working as is 0, signal Sync2_out is 1 o'clock, logic operation result Sync_out_p1 just is effective output of 1, yet it is last from the time of signal transmission, signal Sync2_out is than the first arrival of signal Sync1_out signal output part, can think that for continuous signal signal is to have jumped to 0 by 1, signal jumps to the signal that promptly had negative edge at 0 o'clock by 1.Rising edge is exported the testing result on edge with following by signal output part, can be used as the control signal of subsequent conditioning circuit, uses for subsequent conditioning circuit.
The output clock zone and the input clock territory of the embodiment of the invention are separate, the frequency of output clock zone can dynamically be adjusted, therefore the embodiment of the invention both can realize the signal Synchronization transmission of input clock territory frequency greater than output clock zone frequency, also can realize the signal Synchronization transmission of input clock territory frequency less than output clock zone frequency.As shown in table 1 below, table 1 is 20MHz for input clock territory frequency, and output clock zone frequency is the signal Synchronization embodiment of 10MHz.
| Clk_in(20MHz) | n-1 | n | n+1 | n+2 | n+3 | n+4 | n+5 | n+6 | n+7 | n+8 | n+9 | n+10 | n+11 | n+12 | n+13 | n+14 |
| |
0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| |
0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| |
0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| |
0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| |
0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
| Sync_in_d2_se | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| ? | ? | ? | ? | ? | ? | ? | ? | ? | ? | ? | ? | ? | ? | ? | ? | ? |
| Clk_out(10MHz) | m | m+1 | m+2 | m+3 | m+4 | m+5 | m+6 | m+7 | ? | ? | ? | ? | ? | ? | ? | ? |
| |
0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | ? | ? | ? | ? | ? | ? | ? | ? |
| |
0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | ? | ? | ? | ? | ? | ? | ? | ? |
| |
0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | ? | ? | ? | ? | ? | ? | ? | ? |
| |
0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | ? | ? | ? | ? | ? | ? | ? | ? |
| |
0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | ? | ? | ? | ? | ? | ? | ? | ? |
| |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ? | ? | ? | ? | ? | ? | ? | ? |
Table 1
Because input clock territory frequency is greater than output clock zone frequency, be 2 times of output clock zone frequency, because of 1 this input clock territory cycle less than the output clock zone cycle, for exporting half of clock zone cycle.N-1, n...n+14 represent the clock umber of beats in input clock territory, and m, m+1...m+7 represent to export the clock umber of beats of clock zone.Because input clock cycle is the output clock zone cycle half, therefore the clock umber of beats in two input clock territories is equivalent to the clock umber of beats of an output clock zone.
The output situation of different each signals of the moment has been shown in the above-mentioned table 1, as shown in Table 1, in the n moment in input clock territory cycle, the rising edge of external input signal Sync_in enters synchronizing circuit, and signal transmits in synchronizing circuit, in the m+3 moment in output clock zone cycle, rising edge arrives synchronous signal output end, begins to have synchronizing signal output, and can detect the rising edge signal this moment, Sync_out_p1 is output as 1, shows in the m+3 in output clock zone cycle moment signal Synchronization to begin.
At the n+1 in input clock territory cycle to n+7 constantly, feedback signal Sync_in_d2_se is output as 0, and signal selector Mux2 latchs the signal that is received, and output Sync_in_d2 is 1.
In the n+8 moment in input clock territory cycle, feedback signal Sync_in_d2_se is output as 1, shows that feedback circuit detects synchronizing signal, and Mux2 output signal Sync_in_d2 becomes 0, and synchronizing signal is pinned.
From the n+9 in input clock territory cycle constantly, feedback signal Sync_in_d2_se output becomes 0, Mux2 discharges signal, and the output signal Sync_in_d2 of Mux2 becomes signal Sync_in_reg1 and the output result of Sync_in_reg2 after logic sum gate OR2_1 carries out the logical OR computing; In the m+7 moment in output clock zone cycle, negative edge arrives synchronous signal output end, and can detect the negative edge signal this moment, and Sync_out_p2 is output as 1, shows the signal Synchronization end constantly at the m+7 in output clock zone cycle.Sync_out_reg2 in the table 1 is external input signal Sync_in is carried out synchronous output terminal result.
Above table 1 is depicted as the signal Synchronization transmission embodiment of input clock territory greater than the output clock zone, and is similar with the signals transmission shown in the table 1 for the signal Synchronization transmission of input clock territory less than the output clock zone, is not going to repeat.
In sum, the signal synchronizing method of embodiments of the invention, circuit and asynchronous chip have improved effectiveness, the frequency of output clock zone can dynamically be adjusted, and is higher than input clock territory frequency by interface output clock zone frequency is set, and can realize the lifting of chip interface performance; Be lower than output clock zone frequency by interface output clock zone frequency is set, can realize the control of system power dissipation.Embodiments of the invention are applicable to the synchronous processing of pulse signals etc.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.
Claims (9)
1. the signal synchronization circuit of an asynchronous interface is characterized in that, comprising:
Outer lock storing module, the external input signal that is used for receiving latch with the input clock territory and generate first signal; Successively through the signal selector of a logic sum gate and an alternative, described signal selector generates synchronizing signal according to feedback signal with described first signal;
The inner lock storage module is used for described synchronizing signal is latched with the input clock territory, and then carries out multistage latching with the output clock zone, and that is effectively latched first goes into end signal (Sync1_out) and second synchronization output signal (Sync2_out);
Feedback module is used for going into end signal with described first and carries out multistage latching and generate described feedback signal with described input clock territory;
Rising edge and negative edge detection module are used for going into described first that end signal (Sync1_out) and second synchronization output signal (Sync2_out) carry out rising edge and negative edge detects, and testing result is exported.
2. according to the signal synchronization circuit of the described asynchronous interface of claim 1, it is characterized in that described feedback module comprises:
The signal latch submodule is used for going into end signal with described first and carries out multistage latching with described input clock territory, and that is effectively latched second goes into end signal and second and go out end signal;
Feedback signal generates submodule, is used for that described second inversion signal and described second that goes out end signal is gone into end signal and carries out logic and operation, and generate described feedback signal according to operation result.
3. according to the signal synchronization circuit of claim 1 or 2 described asynchronous interfaces, it is characterized in that described rising edge and negative edge detection module comprise:
The rising edge detection sub-module is used for going into end signal (Sync1_out) and second synchronization output signal (Sync2_out) carries out the detection of rising edge to described first, and testing result is exported;
The negative edge detection sub-module is used for going into end signal (Sync1_out) and second synchronization output signal (Sync2_out) carries out the detection of negative edge to described first, and testing result is exported.
4. the signal synchronizing method of an asynchronous interface is characterized in that, comprising:
The external input signal that receives is latched with the input clock territory and generate first signal; Successively through the signal selector of a logic sum gate and an alternative, described signal selector generates synchronizing signal according to feedback signal with described first signal;
Described synchronizing signal is latched with the input clock territory, and then carry out multistage latching with the output clock zone, that is effectively latched first goes into end signal (Sync1_out) and second synchronization output signal (Sync2_out);
Going into end signal with described first carries out multistage latching and generates described feedback signal with described input clock territory;
Go into to described first that end signal (Sync1_out) and second synchronization output signal (Sync2_out) carry out rising edge and negative edge detects, and testing result is exported.
5. according to the signal synchronizing method of the described asynchronous interface of claim 4, it is characterized in that, describedly go into end signal with first and carry out multistage latching with the input clock territory and generate feedback signal being specially:
Go into end signal with described first and carry out multistage latching with described input clock territory, that is effectively latched second goes into end signal and second and goes out end signal;
Described second inversion signal and described second that goes out end signal is gone into end signal carry out logic and operation, and generate described feedback signal according to operation result.
6. according to the signal synchronizing method of the described asynchronous interface of claim 5, it is characterized in that, describedly go into the detection that end signal (Sync1_out) and second synchronization output signal (Sync2_out) carry out rising edge and negative edge to described first and be specially: first reverse signal of going into end signal (Sync1_out) and second synchronization output signal (Sync2_out) is carried out logic and operation, detect rising edge signal (Sync_out_p1); First reverse signal and second synchronization output signal (Sync2_out) of going into end signal (Sync1_out) carried out logic and operation, detect negative edge signal (Sync_out_p2).
7. an asynchronous chip comprises at least one asynchronous interface, it is characterized in that, described asynchronous interface adopts signal synchronization circuit, and described signal synchronization circuit comprises:
Outer lock storing module, the external input signal that is used for receiving latch with the input clock territory and generate first signal; Successively through the signal selector of a logic sum gate and an alternative, described signal selector generates synchronizing signal according to feedback signal with described first signal;
The inner lock storage module is used for described synchronizing signal is latched with the input clock territory, and then carries out multistage latching with the output clock zone, and that is effectively latched first goes into end signal (Sync1_out) and second synchronization output signal (Sync2_out);
Feedback module is used for going into end signal with described first and carries out multistage latching and generate described feedback signal with described input clock territory;
Rising edge and negative edge detection module are used for going into described first that end signal (Sync1_out) and second synchronization output signal (Sync2_out) carry out rising edge and negative edge detects, and testing result is exported.
8. as asynchronous chip as described in the claim 7, it is characterized in that described feedback module comprises:
The signal latch submodule is used for going into end signal with described first and carries out multistage latching with described input clock territory, and that is effectively latched second goes into end signal and second and go out end signal;
Feedback signal generates submodule, is used for that described second inversion signal and described second that goes out end signal is gone into end signal and carries out logic and operation, and generate described feedback signal according to operation result.
9. as asynchronous chip as described in claim 7 or 8, it is characterized in that described rising edge and negative edge detection module comprise:
The rising edge detection sub-module is used for going into end signal (Sync1_out) and second synchronization output signal (Sync2_out) carries out the detection of rising edge to described first, and testing result is exported;
The negative edge detection sub-module is used for going into end signal (Sync1_out) and second synchronization output signal (Sync2_out) carries out the detection of negative edge to described first, and testing result is exported.
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| CN103576738A (en) * | 2012-08-01 | 2014-02-12 | 中兴通讯股份有限公司 | Method and device for clock domain crossing processing of asynchronous signals |
| CN105988959B (en) * | 2015-02-13 | 2021-06-01 | 中兴通讯股份有限公司 | Asynchronous data transmission method and system |
| CN114117972B (en) * | 2022-01-26 | 2022-06-10 | 之江实验室 | Synchronous device and method of asynchronous circuit |
| CN114785940B (en) * | 2022-03-29 | 2024-04-05 | 海信视像科技股份有限公司 | Image acquisition equipment and synchronous acquisition control method |
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