CN101446843A - High-frequency clock generator, clock frequency conversion method, and chip - Google Patents
High-frequency clock generator, clock frequency conversion method, and chip Download PDFInfo
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- CN101446843A CN101446843A CNA2008102475705A CN200810247570A CN101446843A CN 101446843 A CN101446843 A CN 101446843A CN A2008102475705 A CNA2008102475705 A CN A2008102475705A CN 200810247570 A CN200810247570 A CN 200810247570A CN 101446843 A CN101446843 A CN 101446843A
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Abstract
The invention provides a high-frequency clock generator, a clock frequency conversion method and a chip. The high-frequency clock generator comprises a receiving unit for receiving a low-frequency clock signal; a time-delaying unit for delaying the low-frequency clock signal; a logical gate unit for logical combination of the low-frequency clock signal and the delayed low-frequency clock signal to obtain a high-frequency clock signal; and an output unit for outputting the high-frequency clock signal. The high-frequency clock generator obtains the high-frequency clock signal by combining the time-delaying unit with a logical gate circuit, and has small area and low cost, thereby reducing the cost and the power consumption of the high-frequency clock signal.
Description
Technical field
The present invention relates to the clock technology field, particularly a kind of high frequency clock generator, clock frequency conversion method and a kind of chip.
Background technology
In the application of present clock technology, phaselocked loop (PLL commonly used; Phase Lock Loop) carries out low frequency signal conversion high-frequency signal, thereby realize the demand of different frequency range clock signal.The main range of application of phaselocked loop is generally: sender, receiver, signal generator, frequency synthesizer, function generator, chip interface, digital circuit etc.
The closed loop circuit that existing phaselocked loop mainly is made up of field effect transistor, transistor oscillator, wave filter etc. can make low-frequency clock generate high frequency clock, and tens times of frequencys multiplication are used for digital circuitry.
Yet, in the application of some simple digital circuitry, as in sensor interface (sensing interface), USB, audio interface circuit such as (audio interface), less demanding to clock frequency, promptly low-frequency clock just can satisfy its demand through after several times of frequencys multiplication.Therefore, if use phaselocked loop in these digital circuits, just than higher, power consumption is big for cost so, and area occupied is big, thereby has caused the expensive of digital circuit.
In a word, need the urgent technical matters that solves of those skilled in the art to be exactly at present: in simple digital circuitry, how to reduce the cost and the power consumption that generate high frequency clock.
Summary of the invention
Technical matters to be solved by this invention provides a kind of high frequency clock generator, clock frequency conversion method and a kind of chip, to reduce cost and the power consumption that generates high frequency clock.
In order to address the above problem, the invention discloses a kind of high frequency clock generator, this high frequency clock generator can comprise:
Receiving element is used to receive low-frequency clock signal;
Delay unit is used for described low-frequency clock signal time-delay;
The logic gate unit is used for the low-frequency clock signal of described low-frequency clock signal and described time-delay is carried out logical combination, obtains high frequency clock signal;
Output unit is used to export described high frequency clock signal.
Concrete, described delay unit is a plurality of chronotrons.
Preferably, described chronotron is 2
-nThe chronotron in cycle, n are positive integer.
Preferably, described logic gate unit comprises: first with door, be used for the low-frequency clock signal that described low-frequency clock signal and described delay unit are delayed time is carried out logical combination; Phase inverter is used for described low-frequency clock signal anti-phase; Second with the door, be used for the anti-phase low-frequency clock signal of described anti-phase low-frequency clock signal and described time-delay is carried out logical combination; Or door, be used for carrying out logical combination with the output signal and described second of door with the output signal of door with described first, obtain described high frequency clock signal.
Preferably, described logic gate unit comprises: XOR gate is used for the low-frequency clock signal of described low-frequency clock signal and the time-delay of described delay unit is carried out logical combination; Or door, be used for the output signal of the XOR gate of the output signal of described XOR gate and described time-delay is carried out logical combination, obtain described high frequency clock signal.
The invention also discloses a kind of chip, this chip comprises the high frequency clock generator, and described high frequency clock generator comprises: receiving element is used to receive low-frequency clock signal; Delay unit is used for described low-frequency clock signal time-delay; Logic gates is used for the low-frequency clock signal of described low-frequency clock signal and described time-delay is carried out logical combination, obtains high frequency clock signal; Output unit is used to export described high frequency clock signal.
In order to address the above problem, the invention also discloses a kind of clock frequency conversion method, this method comprises:
Receive low-frequency clock signal; The delay unit described low-frequency clock signal of delaying time; Via the logic gate unit low-frequency clock signal of described low-frequency clock signal and described time-delay is carried out logical combination, obtain high frequency clock signal; Export described high frequency clock signal.
Preferably, the logic gate unit comprises described in the described method: first with the door, second with the door, phase inverter and or; Describedly the process that low-frequency clock signal carries out logical combination is comprised via the logic gate unit:
Described first with gate logic make up the low-frequency clock signal of described low-frequency clock signal and described time-delay, and export to described or first input end; And described low-frequency clock signal is anti-phase via described phase inverter; Described second with gate logic make up described anti-phase low-frequency clock signal and the anti-phase low-frequency clock signal of described time-delay, and export to described or second input end; Described or gate logic makes up the signal of described input, obtains described high frequency clock signal.
Preferably, logic gate unit described in the described method comprises XOR gate or door; Describedly the process that low-frequency clock signal carries out logical combination is comprised via the logic gate unit:
The low-frequency clock signal of described low-frequency clock signal of described XOR gate logical combination and described time-delay, and export first input end described or door to; And the output signal of described XOR gate is delayed time via delay unit, and exports second input end described or door to; Described or gate logic makes up the signal of described input, obtains described high frequency clock signal.
Further, described delay unit is a plurality of chronotrons.
Compared with prior art, the present invention has the following advantages:
High frequency clock generator of the present invention obtains high frequency clock signal by using the combination of delay unit and logic gates, and this high frequency clock generator area is little, dutycycle can be controlled flexibly; The output frequency of this high frequency clock generator can be controlled by delay unit in addition, and promptly high frequency clock as required can be provided with different delay units; In some ball bearing made using, can use high frequency clock generating apparatus of the present invention, the system that makes generates the clock higher than input clock frequency, thereby can well reduce the cost of system, and high frequency clock generator of the present invention can be saved more space in digital circuit or chip.
Description of drawings
Fig. 1 is the structured flowchart of a kind of high frequency clock generator of the present invention;
Fig. 2 is the structural representation of a kind of high frequency clock generator embodiment 1 of the present invention;
Fig. 3 is the pulse change graph of a relation of a kind of high frequency clock generator embodiment 1 of the present invention;
Fig. 4 is the structural representation of a kind of high frequency clock generator embodiment 2 of the present invention;
Fig. 5 is the pulse change graph of a relation of a kind of high frequency clock generator embodiment 2 of the present invention;
Fig. 6 is the structural representation of a kind of high frequency clock generator embodiment 3 of the present invention;
Fig. 7 is the pulse change graph of a relation of a kind of high frequency clock generator embodiment 3 of the present invention;
Fig. 8 is the schematic flow sheet of a kind of clock frequency conversion method embodiment of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
Core idea of the present invention is, uses logic gates and chronotron to be combined into the high frequency clock generator and substitutes phaselocked loop, obtains the clock higher than input clock frequency; High frequency clock generator of the present invention can regulate dutycycle and area occupied is few, is applied in the digital circuit to can be good at reducing cost.
With reference to Fig. 1, show the structured flowchart of a kind of high frequency clock generator of the present invention, described high frequency clock generator comprises with lower unit:
Receiving element 101 is used to receive low-frequency clock signal;
When receiving element 101 receives low frequency signal, described delay unit 102 is with this low frequency signal time-delay, via logic gates 103 low-frequency clock signal of described low-frequency clock signal and described time-delay is carried out logical combination then, obtain high frequency clock signal, and by output unit 104 outputs.
Wherein, described delay unit 102 can be a plurality of chronotrons in different delayed time cycle, and the connected mode of its described chronotron can be for multiple, and described chronotron is 2
-nThe chronotron in cycle, n are positive integer.
In the specific implementation process, it all is feasible that the present invention adopts any logic gates that can produce high frequency clock signal to be connected with chronotron, and the present invention does not need it is limited, and wherein chronotron can determine the cycle of the high frequency clock signal exported.
A preferred embodiment of the present invention is referring to Fig. 2, and Fig. 2 is the structural representation of a kind of high frequency clock generator embodiment 1 of the present invention; Wherein import a low-frequency clock signal 200, via logic gates output high frequency clock signal.
Described logic gates comprises: phase inverter 207, first XOR gate 202 and second XOR gate 205 or door 204;
The low frequency signal that described first XOR gate 202 receives low frequency signal 200 and delays time via delay unit 201, the logical groups merging exports second delay unit 203 to;
Described phase inverter 207 receives the low-frequency clock signal 200 of described input, and this low-frequency clock signal 200 oppositely exported, the anti-phase low frequency signal that described second XOR gate 205 receives described anti-phase low frequency signal and delays time via delay unit 206, logical groups merges output;
Described or door 204 receives the output signal of delay unit 203 and the output signal of second XOR gate 205, and logical combination is exported described high frequency clock signal.
Need to prove, in the present invention, according to the needs of different logic gates, with the low-frequency clock signal that receives, the clock signal that demultiplexing is identical; With method of the present invention the identical clock signal of described multichannel is handled then, and then obtained high frequency clock signal.
The pulse relation that is produced as shown in Figure 3, the pulse change graph of a relation of a kind of high frequency clock generator embodiment 1 of the present invention, wherein, a1 is the low frequency pulse signal of input, via the pulse signal shown in the time-delay chronotron 201 acquisition a2 of eight/one-period, described pulse signal a1 and a2 carry out logical combination via first XOR gate 202, obtain pulse signal a3, and described pulse signal a3 obtains pulse signal a4 by the chronotron 203 of two/one-period of time-delay;
Simultaneously, described low-frequency input signal a1 obtains pulse signal a5 through phase inverter 207, this pulse signal a5 obtains a6 via the chronotron 206 of eight/one-period of time-delay, and described pulse signal a5 and pulse signal a6 are carried out logical combination by second XOR gate 205, obtains pulse signal a7;
Described pulse signal a4 and pulse signal a7 or the door 204 in logical combination, obtain needed high frequency clock signal a8, and export this high frequency clock signal a8.
Certainly, aforesaid way is only as example, and in specific implementation, it also is feasible that described logic gates adopts other gate device combinations; The present invention can not have under the situation of phaselocked loop, low-frequency clock is carried out frequency multiplication, make and in some ball bearing made using, can pass through simple digital circuit, make clock generation system generate the clock higher than input clock frequency, thereby can area occupied few, and can reduce the cost that generates high frequency clock signal.
As another kind of the present invention preferred embodiment 2 more, as shown in Figure 4, described delay unit is the chronotron of eight/one-period, and wherein, described logical circuit can comprise:
First with door 402, be used for the low-frequency clock signal 400 of described low-frequency clock signal 400 and described delay unit 401 time-delays is carried out logical combination;
Second with door 404, be used for the anti-phase low-frequency clock signal that described anti-phase low-frequency clock signal and described delay unit 405 delayed time is carried out logical combination;
Or door 403, be used for carrying out logical combination with the output signal and described second of door 402 with the output signal of door 404 with described first, obtain described high frequency clock signal.
The pulse graph of a relation of this embodiment correspondence as shown in Figure 5, the high frequency clock frequency of described output is the twice of low-frequency clock frequency of input.
Wherein, b1 is the low-frequency clock signal of input, and b2 is via the time-delay pulse signal that obtains of delay unit 401 of eight/one-period, b3 be pulse signal b1 and pulse signal b2 via first with door 402 logical combinations after pulse signal;
B4 for the low frequency pulse signal b1 of input via phase inverter 406 pulse signal after anti-phase, b5 is the anti-phase low frequency pulse signal pulse signal after via time-delay delay unit 405 time-delays of eight/one-period, b6 be pulse signal b4 and pulse signal b5 through second with door 404 logical combinations after the pulse signal that obtains;
Accordingly, described or door 403 received pulse signal b3 and pulse signal b6, and carry out logical combination, and obtain pulse signal b7, be needed high frequency clock signal.The dutycycle of this high frequency clock signal can not be 1 to 1, is not that has enough used very high digital circuit application scenario much dutycycle being required still.
Certainly, those skilled in the art adopt any logical circuit, all are feasible to make low frequency signal produce high frequency clock by output logic relation, for example or door, with the logical circuit that door and phase inverter are formed, the present invention need not this to be limited.
For making those skilled in the art understand the present invention better,, the delay unit among the embodiment 3 of high frequency clock generator of the present invention, a kind of logic gates unit and corresponding pulse graph of a relation are further specified below in conjunction with Fig. 6 and Fig. 7.Shown the annexation between each gate circuit assembly among Fig. 6, described gate circuit comprises: XOR gate 602 or door 604;
The low-frequency clock signal that described XOR gate 602 receives described low-frequency clock signal 600 and delays time via first delay unit 601, logical groups merging export second delay unit 603 and described or door 604 to;
Described or door 604 receives the output signal of second delay unit 603 and via the output signal of XOR gate 602, logical combination is exported described high frequency clock signal.
Fig. 7 is these embodiment 3 pairing high-frequency signal pulse graphs of a relation, c1 is the low-frequency clock pulse signal of input, the pulse signal that c2 obtains for the delay unit 601 via the eight/one-period of delaying time, c3 is the pulse signal signal c1 and signal c2 carry out logical combination in XOR gate 602 after, c4 carries out the pulse signal that 1/2nd time-delays obtain via delay unit 603 pulse signals c3, c5 is process or door 604 logical combination pulse signal c3 and pulse signal c4, the high frequency clock signal of acquisition; The high frequency clock frequency of described output is four times of low-frequency clock frequency of input, and dutycycle can be regulated.
In addition, the invention provides a kind of chip, this chip comprises the communicator of a high frequency clock generator, and this device comprises:
Receiving element is used to receive low-frequency clock signal;
Delay unit is used for described low-frequency clock signal time-delay; Wherein, described delay unit can be a plurality of chronotrons, and described chronotron is 2
-nThe chronotron in cycle, n are positive integer;
Logic gates is used for a plurality of low-frequency clock signals are carried out logical combination, obtains high frequency clock signal;
Output unit is used to export described high frequency clock signal.
Because the front is described in detail the constructional device of concrete high frequency clock generator, therefore do not repeat them here.
Below high frequency clock generator of the present invention is carried out clock frequency conversion method describe in detail.
With reference to Fig. 8, show the schematic flow sheet of a kind of clock frequency conversion method of the present invention embodiment, as can be seen from the figure, receive low-frequency clock signal, trigger high frequency clock generator 801 and produce high frequency clock signal, and with described high frequency clock signal output.
Wherein said high frequency clock generator 801 comprises delay unit and logic gate unit, and described delay unit is delayed time to low-frequency clock signal, via the logic gate combination, thereby obtains high frequency clock signal.
Wherein, described logic gate unit comprise phase inverter, first and door, second with door or;
Described first with gate logic make up the low-frequency clock signal of described low-frequency clock signal and described time-delay, and export to described or first input end;
And described low-frequency clock signal is anti-phase via described phase inverter;
Described second with gate logic make up described anti-phase low-frequency clock signal and the anti-phase low-frequency clock signal of time-delay, and export to or second input end;
Described or gate logic makes up the signal of described input, obtains described high frequency clock signal.
A kind of preferred implementation, described logic gate unit further by XOR gate and or the door form;
The low-frequency clock signal of described low-frequency clock signal of described XOR gate logical combination and described time-delay, and export first input end described or door to;
And the output signal of described XOR gate is delayed time via delay unit, and exports second input end described or door to;
Described or gate logic makes up the signal of described input, obtains described high frequency clock signal.
Delay unit in this conversion method can be a plurality of chronotrons.
More than the high frequency clock generator in the embodiment of the invention is carried out clock frequency conversion method carried out simple description; So it all is expressed as a series of combination of actions, but those skilled in the art should know that the present invention is not subjected to the restriction of described sequence of movement, because according to the present invention, some step can adopt other orders or carry out simultaneously.
Those skilled in the art also should know, the embodiment described in the instructions all belongs to preferred embodiment, and related action and module might not be that the present invention is necessary.Each embodiment in this instructions all adopts the mode of going forward one by one to describe, and what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.
More than a kind of high frequency clock generator provided by the present invention, clock frequency conversion method and a kind of chip are described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1, a kind of high frequency clock generator is characterized in that, comprising:
Receiving element is used to receive low-frequency clock signal;
Delay unit is used for described low-frequency clock signal time-delay;
The logic gate unit is used for the low-frequency clock signal of described low-frequency clock signal and described time-delay is carried out logical combination, obtains high frequency clock signal;
Output unit is used to export described high frequency clock signal.
2, high frequency clock generator according to claim 1 is characterized in that described delay unit is a plurality of chronotrons.
3, as high frequency clock generator as described in the claim 2, it is characterized in that described chronotron is 2
-nThe chronotron in cycle, n are positive integer.
4, high frequency clock generator according to claim 1 is characterized in that described logic gate unit comprises:
First with door, be used for the low-frequency clock signal that described low-frequency clock signal and described delay unit are delayed time is carried out logical combination;
Phase inverter is used for described low-frequency clock signal anti-phase;
Second with the door, be used for the anti-phase low-frequency clock signal of described anti-phase low-frequency clock signal and described time-delay is carried out logical combination;
Or door, be used for carrying out logical combination with the output signal and described second of door with the output signal of door with described first, obtain described high frequency clock signal.
5, high frequency clock generator according to claim 1 is characterized in that described logic gate unit comprises:
XOR gate is used for the low-frequency clock signal of described low-frequency clock signal and the time-delay of described delay unit is carried out logical combination;
Or door, be used for the output signal of the XOR gate of the output signal of described XOR gate and described time-delay is carried out logical combination, obtain described high frequency clock signal.
6, a kind of chip is characterized in that, this chip comprises the high frequency clock generator, and described high frequency clock generator comprises:
Receiving element is used to receive low-frequency clock signal;
Delay unit is used for described low-frequency clock signal time-delay;
Logic gates is used for the low-frequency clock signal of described low-frequency clock signal and described time-delay is carried out logical combination, obtains high frequency clock signal;
Output unit is used to export described high frequency clock signal.
7, a kind of clock frequency conversion method is characterized in that, comprising:
Receive low-frequency clock signal;
The delay unit described low-frequency clock signal of delaying time;
Via the logic gate unit low-frequency clock signal of described low-frequency clock signal and described time-delay is carried out logical combination, obtain high frequency clock signal;
Export described high frequency clock signal.
8, method as claimed in claim 7 is characterized in that, described logic gate unit comprises: first with door, second with door, phase inverter and or, describedly the process that low-frequency clock signal carries out logical combination is comprised via the logic gate unit:
Described first with gate logic make up the low-frequency clock signal of described low-frequency clock signal and described time-delay, and export to described or first input end;
And described low-frequency clock signal is anti-phase via described phase inverter;
Described second with gate logic make up described anti-phase low-frequency clock signal and the anti-phase low-frequency clock signal of described time-delay, and export to described or second input end;
Described or gate logic makes up the signal of described input, obtains described high frequency clock signal.
9, method as claimed in claim 7 is characterized in that, described logic gate unit comprises XOR gate or door, describedly via the logic gate unit process that low-frequency clock signal carries out logical combination is comprised:
The low-frequency clock signal of described low-frequency clock signal of described XOR gate logical combination and described time-delay, and export first input end described or door to;
And the output signal of described XOR gate is delayed time via delay unit, and exports second input end described or door to;
Described or gate logic makes up the signal of described input, obtains described high frequency clock signal.
10, method as claimed in claim 7 is characterized in that, described delay unit is a plurality of chronotrons.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2008102475705A CN101446843A (en) | 2008-12-30 | 2008-12-30 | High-frequency clock generator, clock frequency conversion method, and chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2008102475705A CN101446843A (en) | 2008-12-30 | 2008-12-30 | High-frequency clock generator, clock frequency conversion method, and chip |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102231627A (en) * | 2011-04-06 | 2011-11-02 | 中国科学院西安光学精密机械研究所 | Method and device for realizing short-time pulse signal |
| CN102466777A (en) * | 2010-11-12 | 2012-05-23 | 瑞鼎科技股份有限公司 | Integrated circuit testing device |
| CN104536239A (en) * | 2014-12-19 | 2015-04-22 | 欧阳征标 | Optical clock generator |
| CN108900181A (en) * | 2018-07-02 | 2018-11-27 | 天津芯海创科技有限公司 | Clock delay regulating device and clock delay regulating system |
| CN108957300A (en) * | 2018-09-03 | 2018-12-07 | 长鑫存储技术有限公司 | Wafer test apparatus and test method |
| CN109300740A (en) * | 2018-11-16 | 2019-02-01 | 广州科伺智能科技有限公司 | A kind of control circuit and its control method of relay and solenoid valve |
| CN110113009A (en) * | 2018-02-01 | 2019-08-09 | 长鑫存储技术有限公司 | Frequency multiplier circuit and frequency multiplier |
| CN113608575A (en) * | 2021-10-09 | 2021-11-05 | 深圳比特微电子科技有限公司 | Assembly line clock drive circuit, calculating chip, force calculating board and calculating equipment |
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| CN1144926A (en) * | 1995-09-06 | 1997-03-12 | 三菱电机株式会社 | Clock generating circuit, PLL circuit, semiconductor device and designing method |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1144926A (en) * | 1995-09-06 | 1997-03-12 | 三菱电机株式会社 | Clock generating circuit, PLL circuit, semiconductor device and designing method |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102466777A (en) * | 2010-11-12 | 2012-05-23 | 瑞鼎科技股份有限公司 | Integrated circuit testing device |
| CN102231627B (en) * | 2011-04-06 | 2014-03-12 | 中国科学院西安光学精密机械研究所 | Method for realizing short-time pulse signal |
| CN102231627A (en) * | 2011-04-06 | 2011-11-02 | 中国科学院西安光学精密机械研究所 | Method and device for realizing short-time pulse signal |
| US10338454B2 (en) | 2014-12-19 | 2019-07-02 | Zhengbiao OUYANG | Optical clock generator |
| CN104536239A (en) * | 2014-12-19 | 2015-04-22 | 欧阳征标 | Optical clock generator |
| CN104536239B (en) * | 2014-12-19 | 2018-03-16 | 深圳市至佳生活网络科技有限公司 | Optical clock generator |
| CN110113009A (en) * | 2018-02-01 | 2019-08-09 | 长鑫存储技术有限公司 | Frequency multiplier circuit and frequency multiplier |
| CN108900181A (en) * | 2018-07-02 | 2018-11-27 | 天津芯海创科技有限公司 | Clock delay regulating device and clock delay regulating system |
| CN108900181B (en) * | 2018-07-02 | 2022-07-29 | 天津芯海创科技有限公司 | Clock delay adjusting device and clock delay adjusting system |
| CN108957300A (en) * | 2018-09-03 | 2018-12-07 | 长鑫存储技术有限公司 | Wafer test apparatus and test method |
| CN109300740A (en) * | 2018-11-16 | 2019-02-01 | 广州科伺智能科技有限公司 | A kind of control circuit and its control method of relay and solenoid valve |
| CN113608575A (en) * | 2021-10-09 | 2021-11-05 | 深圳比特微电子科技有限公司 | Assembly line clock drive circuit, calculating chip, force calculating board and calculating equipment |
| CN113608575B (en) * | 2021-10-09 | 2022-02-08 | 深圳比特微电子科技有限公司 | Assembly line clock drive circuit, calculating chip, force calculating board and calculating equipment |
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Application publication date: 20090603 |