CN114117972B - Synchronous device and method of asynchronous circuit - Google Patents
Synchronous device and method of asynchronous circuit Download PDFInfo
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- CN114117972B CN114117972B CN202210090997.9A CN202210090997A CN114117972B CN 114117972 B CN114117972 B CN 114117972B CN 202210090997 A CN202210090997 A CN 202210090997A CN 114117972 B CN114117972 B CN 114117972B
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Abstract
The invention relates to the technical field of signal synchronization among asynchronous circuits, in particular to a synchronization device and a synchronization method for asynchronous circuits, wherein the device comprises a sending module, an asynchronous transmission module, a receiving module, a sending end clock and a receiving end clock, wherein the sending module is driven by the sending end clock, generates and updates sending requests and data, and synchronously sends response signals in a register beating mode; the asynchronous transmission module asynchronously transmits the request and the data from the sending module to the receiving module and generates a sending response signal; the receiving module is driven by a receiving end clock, synchronously receives the request signal in a register beating mode, collects effective data when the edge of the synchronous request signal jumps, and simultaneously generates a receiving response signal. The invention improves the data transmission efficiency on the premise of avoiding the metastable state influence of cross-clock domain data transmission, and provides a good solution for large-scale integration of the artificial intelligent chip.
Description
Technical Field
The invention relates to the technical field of signal synchronization between asynchronous circuits, in particular to a synchronous transposition method of an asynchronous circuit.
Background
The method comprises the steps that two methods of synchronous design and asynchronous design exist in the field of digital circuit design, a synchronous circuit is driven to work by clocks with the same or fixed multiples or phase relations, an EDA tool can fully analyze the time sequence characteristics of the circuit to ensure that the circuit can stably run, and therefore the method is widely applied to the design of the ultra-large scale integrated circuit, but the scale of the chip is continuously increased along with the continuous enhancement of the calculation force demand of an artificial intelligent chip, the further improvement of the semiconductor process is very difficult, and the improvement of the performance of the synchronous circuit is close to the limit at present; the asynchronous circuit has obvious advantages in the aspects of low power consumption, low noise, interference resistance, no clock offset and the like, but the asynchronous design has main obstacles of no mature EDA tool support, difficult test and the like, so that the asynchronous circuit is difficult to be directly applied to the design of the ultra-large scale integrated circuit. Global Asynchronous Local Synchronous (GALS) design methods that integrate the advantages of synchronous and asynchronous systems, respectively, are gaining increasing attention and development. In the GALS design, because a plurality of independent clock domains exist, a data transmission scenario crossing the clock domains inevitably occurs, and data needs to interact in two or more clock domains. Because the phase relationship of clock edges between different clock domains is uncertain, data can be metastable when being transmitted from one clock domain to another clock domain to cause the operation of the whole system to be wrong, and a reliable and efficient data synchronization method between asynchronous circuits must be established.
In the data transmission process, the synchronous interface of the existing asynchronous circuit needs to respectively consume two clock cycles synchronously for two beats for a receiving end to request signals and a sending end to response signals in order to eliminate the influence of a metastable state, and the response signals of the sending end depend on the request signals after the receiving end is synchronous, so that the original independent sending and receiving ends work in series, and the transmission performance is low.
As shown in fig. 1, in order to avoid or eliminate the influence of the metastable state, it is proposed to provide a data read/write synchronization circuit and a data read/write method. Setting the REQ _ T pulse signal high for one TCLK clock signal period to make the fifth D trigger output high level signal; the high level signal outputs a REQ _ R signal after being synchronized by a clock domain of an RCLK clock signal; the REQ _ R signal is raised, and the clock domain of the RCLK clock signal reads data; after the clock domain of the RCLK clock signal finishes reading data, enabling the ACK _ R pulse signal to be set high; and the signal in the fifth D trigger is cleared, the ACK _ T signal is changed into low level, and the data reading and writing are finished. According to the method, the control signal in the data read-write synchronization circuit is latched by the D trigger and the reset register, the data sending end sends a request, and the receiving end clears the request, so that error data can be avoided, and reliable transmission of the data is guaranteed. However, the response signal ACK _ T received by the transmitting end depends on the request signal REQ _ R received by the receiving end, and the ACK _ T must be pulled down only after the REQ _ R is raised, so that the whole data transmission process at least needs 3 transmitting end clock cycles and 3 receiving end clock cycles, the transmitting end and the receiving end depend on each other, and the data transmission efficiency is low.
As shown in fig. 2, in order to solve the problems of real-time signal transmission, status and control signal transmission efficiency of the asynchronous interface, a signal synchronization method, a circuit and an asynchronous chip of the asynchronous interface are proposed. The method uses three stages of flip-flops, CLKA represents the input clock domain, CLKB represents the output clock domain, and Reset represents the asynchronous Reset signal. The process of obtaining the synchronous signal by the external input signal Sync _ in through the processing of the signal synchronization circuit mainly comprises the following steps that the external input signal Sync _ in is latched into Sync _ in reg by an input clock domain latch InReg; the signal Sync _ in _ regl is latched into Sync in reg2 by an input clock domain latch InLckReg after being output by an alternative signal selector Mux 2; the signal Sync _ in _ reg2 is latched as SyncO out via the first stage output clock domain latch SyncO; the signal SyncO out is latched as Syncl out via the second stage output clock domain latch Sync 1; signal Sync1 out is latched as Sync2 out via third stage output clock domain latch Sync 2; the signal Syncl _ out is latched as FbSync0_ out via a first stage input clock domain latch FbSyncO; the signal FbSyncO out is latched as FbSyncl _ out via the second stage input clock domain latch FbSync 1; the signal FbSync _ out is latched as FbSync2_ out via a third stage input clock domain latch FbSync 2; the signals FbSyncl out and FbSync2 out are subjected to logic operation through a logic AND gate Nand2 with one end reversely input, and feedback signals Sync _ in _ d2_ se are generated and fed back to the signal selector Mux 2; the signal selector Mux2 generates a synchronization signal Sync _ in _ d2 according to the feedback signal Sync _ in _ d2_ se; the Sync signal Sync _ in _ d2 is output through the OUT terminal, i.e. the final Sync output result Sync _ OUT _ reg2 of the synchronization circuit. The sending end and the receiving end of the method both carry out two-beat synchronous processing, the metastable state problem can be effectively avoided, and simultaneously, the synchronous request signal Sync1_ out of the receiving end is immediately returned as a sending response signal, so that the efficiency of the receiving end is improved, but the response signal received by the sending end still depends on the request signal received by the receiving end, the whole data transmission process at least needs 3 clock cycles of the sending end and2 clock cycles of the receiving end, and the data transmission efficiency is still lower.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention provides a synchronization method, a synchronization device and a synchronization method for an asynchronous circuit, and the specific technical scheme is as follows:
a synchronous device of an asynchronous circuit comprises a sending module, an asynchronous transmission module, a receiving module, a sending end clock TXCLK and a receiving end clock RXCLK, wherein the sending module is driven by the sending end clock TXCLK to generate and update sending requests and data and synchronously send response signals in a register beating mode; the asynchronous transmission module asynchronously transmits the request and the data from the sending module to the receiving module and simultaneously generates a sending response signal; the receiving module is driven by a receiving end clock RXCLK, synchronously receives the request signals in a register beating mode, collects effective data when the synchronous request signals generate edge jump, and generates receiving response signals at the same time.
Further, the sending module transmits the sent DATA Tx _ DATA to the asynchronous transmission module, and the sending module specifically includes: the circuit comprises a first overturning register, a second overturning register, a first synchronous response register, a second synchronous response register, a third synchronous response register and an edge detection circuit, wherein the edge detection circuit consists of two NAND gates and one OR gate; the first flip register performs first data transmission when a first data signal first _ data is pulled high, and outputs a high level to enable a Latch enable signal Latch _ En to be in a high level state; the second inversion register inverts the transmission request signal Tx _ Req when the transmission response Valid signal Tx _ Ack _ Valid is detected for the first data transmission or internally; the first synchronous response register and the second synchronous response register synchronously transmit a response signal Tx _ Ack; the third synchronous response register, the edge detection circuit and the or gate are connected in sequence to detect whether the transmission response signal Tx _ Ack is effectively inverted, if the transmission response signal Tx _ Ack _ Valid is inverted, a transmission response effective signal Tx _ Ack _ Valid is generated through the or gate, the first data signal first _ data and the transmission response effective signal Tx _ Ack _ Valid obtain a high-level signal through the or gate, namely, a transmission request effective signal Tx _ Req _ Valid is obtained, the Tx _ Req _ Valid is connected to the En end of the second inversion register, the Q end of the second inversion register is inverted to obtain a transmission request signal Tx _ Req, and the transmission request signal Tx _ Req is pulled to be in a high-level state and is connected to the asynchronous transmission module.
Further, the asynchronous transmission module receives and transmits the request Tx _ Req and the DATA Tx _ DATA, and includes: the DATA transmission device comprises a latch, a latch group, a rising edge response register and a falling edge response register, wherein the latch receives a transmission request signal Tx _ Req, the latch group receives DATA Tx _ DATA, and when the latch and the latch group generate a receiving response signal Rx _ Ack in a first DATA transmission or asynchronous transmission module, the Tx _ Req and the Tx _ DATA are transmitted to respective output ends to become a request signal Rx _ Req and receiving DATA Rx _ DATA accessing a receiving module; the request signal Rx _ Req is also used as a transmission response signal Tx _ Ack fed back to the transmission module; the rising edge response register and the falling edge response register control a reception response signal Rx _ Ack, which is equivalent to a Latc _ En signal after the first data transmission is completed, to be changed into a high level or a low level state according to the states of the Tx _ Ack signal and the reception response Valid signal Rx _ Ack _ Valid signal.
Further, the Latch enable signal Latch _ En is specifically: the first _ data signal is delayed by one clock cycle to become a first _ data _ d signal, and kept as long as the time when the Tx _ Req signal is generated, the first _ data _ d signal and the Rx _ Ack signal pass through an or gate to obtain a Latch enable signal Latch _ En.
Furthermore, the receiving module receives and collects Valid DATA, so that the receiving end DATA RX _ DATA completes updating, the receiving module includes a first synchronization request register, a second synchronization request register, a third synchronization request register, two nand gates, and an edge detection circuit formed by an or gate, which are connected in sequence, the first synchronization request register and the second synchronization request register synchronously receive a request signal RX _ Req to the third synchronization request register, the two nand gates, and the edge detection circuit formed by the or gate detect whether RX _ Req is effectively inverted, when a synchronization request signal output by the second synchronization request register is inverted, the or gate generates a pulse signal, which is a reception request Valid signal RX _ Req _ Valid signal and a reception response Valid signal RX _ Ack _ Valid signal.
A method of synchronizing an asynchronous circuit, comprising the steps of:
step one, when data generated by the front end of a sending module needs to be sent to a receiving module, the sending module enters a sending state and starts to send first data;
step two, the asynchronous transmission module transmits the request signal and the data generated by the sending module to the receiving module and generates a sending response signal at the same time;
and step three, the receiving module starts to receive data and generates a receiving response effective signal after the asynchronous transmission module updates the request signal.
Further, the first step specifically includes:
and 3, turning over the sending request signal and accessing the sending request signal into the abnormal transmission module.
Further, the second step specifically includes:
step 4, pulling up the enabling signals of the latch and the latch group of the asynchronous transmission module, and opening a transmission channel;
step 5, receiving the sending request signal, generating a receiving request signal, transmitting the data output by the sending module to the input end of the receiving module, and feeding back the receiving request signal as a sending response signal to the sending module;
and 6, pulling down the enable signals of the latch and the latch group, and closing the transmission channel.
Further, the third step specifically includes:
and 7, carrying out synchronous beating operation on the receiving request signal, registering effective data, and generating a receiving response effective signal and feeding back the effective signal to the asynchronous transmission module.
The invention has the advantages that:
the invention fully utilizes the upper and lower edges of the request signal, ensures that the sending end and the receiving end are respectively independent and parallel, improves the data transmission efficiency to the maximum extent on the premise of avoiding the influence of the metastable state of data transmission across clock domains, obviously improves the performance compared with the prior method, and provides a good solution for the large-scale integration of the artificial intelligent chip.
Drawings
FIG. 1 is a data read/write synchronization circuit of the type mentioned in the background;
FIG. 2 is a signal synchronization method and circuit for an asynchronous interface as mentioned in the background;
FIG. 3 is a circuit arrangement embodiment of the method of the present invention;
FIG. 4 is a timing diagram of data transmission when the TXCLK frequency is greater than the RXCLK frequency according to the method of the present invention;
FIG. 5 is a timing sequence for data transmission when the TXCLK frequency is less than the RXCLK frequency according to the method of the present invention;
in the figure, a first flip register 101, a second flip register 102, a latch 201, a latch group 202, a first synchronization request register 301, a second synchronization request register 302, a third synchronization request register 303, a rising edge response register 401, a falling edge response register 402, a first synchronization response register 501, a second synchronization response register 502, and a third synchronization response register 503 are shown.
Detailed Description
In order to make the objects, technical solutions and technical effects of the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and examples.
As shown in fig. 3, a synchronization apparatus for an asynchronous circuit according to an embodiment of the present invention includes a transmitting module, an asynchronous transmission module, and a receiving module, where TXCLK represents a transmitting end clock, RXCLK represents a receiving end clock, RESET represents a global RESET signal, and a low level is active, where the transmitting module is driven by the transmitting end clock TXCLK, and is responsible for generating and updating a transmission request and data, and synchronously inputs a transmission response signal in a register beating manner to avoid an influence caused by a metastable state; the asynchronous transmission module is responsible for asynchronously transmitting the request and the data from the sending module to the receiving module and simultaneously generating a sending response signal, and the opening and the closing of a transmission channel are not driven by a clock and completely work asynchronously; the receiving module is driven by a receiving end clock RXCLK, synchronously inputs request signals in a register beating mode to avoid influence caused by a metastable state, collects effective data when the sending edge of the synchronized request signals jumps, and generates receiving response signals at the same time.
Specifically, the sending module specifically includes: a first inversion register 101 for performing a first data transfer, when the first data transfer occurs, the first inversion register 101 outputs a high level so that the Latch enable signal Latch _ En becomes a high level state; a second inversion register 102 for generating a transmission request signal Tx _ Req, wherein when a first data transmission occurs or a transmission response Valid signal Tx _ Ack _ Valid is internally detected, the output of the second inversion register 102 is inverted, i.e. a Valid request is generated; a first synchronous response register 501 and a second synchronous response register 502 for synchronously sending response signals Tx _ Ack, so as to avoid the influence caused by metastable state; the third synchronous response register 503 for detecting whether Tx _ Ack is Valid and the edge detection circuit composed of two nand gates and one or gate will generate a pulse when the synchronous response signal outputted from the second synchronous response register 502 is inverted, i.e. the Tx _ Ack _ Valid signal forms a Valid pulse.
The asynchronous transmission module specifically comprises a latch 201 and a latch group 202 for transmitting Tx _ Req and Tx _ DATA, when a transmitting end transmits a first batch of DATA or a receiving response signal Rx _ Ack is generated inside the asynchronous transmission module, the latch 201 and the latch group 202 are opened, Tx _ Req and Tx _ DATA are transmitted to the output end of the latch and become a request signal Rx _ Req and receiving DATA Rx _ DATA of the receiving module; the output of the latch 201 is used as both a request signal Rx _ Req for accessing the receiving module and a transmission response signal Tx _ Ack fed back to the transmitting module, so that the receiving module and the transmitting module can continue to operate at the same time, and the high-performance operation of the whole circuit structure is ensured; a rising edge response register 401 and a falling edge response register 402 for controlling an Rx _ Ack signal, which is equivalent to a Latc _ En signal after the first batch of DATA is completely transmitted, to be changed into a high level or a low level state according to the states of the Tx _ Ack signal and the reception response Valid signal Rx _ Ack _ Valid, thereby controlling the opening or closing of the 2-latch 201, the latch group 202, and the transmission of Tx _ Req and Tx _ DATA.
The receiving module specifically comprises a first synchronous request register 301 and a second synchronous request register 302 for synchronizing Rx _ Req, so as to avoid the influence caused by a metastable state; when the synchronization request signal output from the second synchronization request register 302 is inverted, the or gate will generate a pulse, which is the reception request Valid signal Rx _ Req _ Valid and the reception response Valid signal Rx _ Ack _ Valid.
A synchronization method of an asynchronous circuit comprises the following specific steps:
step one, when the front end of the sending module generates data to be sent to the receiving module, the sending module enters a sending state and starts to send first data:
Step 3, turning over and accessing the sending request signal to the asynchronous transmission module, specifically: when the edge of the second TXCLK clock cycle arrives, the Q terminal of the second flip-flop register 102 will flip due to the Tx request Valid signal Tx _ Req _ Valid, i.e., the En terminal of the second flip-flop register 102, being pulled high and connected to the D terminal of the latch 201; since the Tx _ Ack signal is the Rx request signal Rx _ Req, the Tx _ Ack signal is not inverted before the request signal is transferred to the Q terminal of the latch 201, which ensures efficient transfer of the transmission request.
Step two, the asynchronous transmission module is responsible for transmitting the request signal and the data generated by the sending module to the receiving module, and simultaneously generating a sending response signal:
step 4, pulling up the enable signals of the latch 201 and the latch group 202 of the asynchronous transmission module, and opening a transmission channel, specifically: for the case of transmitting the first data, the first _ data _ d is a signal that the first _ data delays by one transmit-end clock cycle, and the signal is pulled up by one transmit-end clock cycle; for the case of transmitting other data, since the Rx response Valid signal Rx _ Ack _ Valid is coupled to the CLK terminals of the rising edge response register 401 and the falling edge response register 402, if the Rx _ Req signal is in a high state, the rising edge response register 401 outputs a high level when the Rx _ Ack _ Valid is pulled up, and pulls up the Latch _ En signal; if the Rx _ Req signal is in a low state, the falling edge response register 402 outputs a high level when the Rx _ Ack _ Valid is pulled high, pulling up the Latch _ En signal; the fisrt _ data _ d and Rx _ Ack signals pass through an OR gate to obtain a Latch enable signal Latch _ En, and the Latch _ En signals are simultaneously accessed to the CLK ends of the Latch 201 and the Latch group 202; the first data signal, first _ data, needs one clock to drive and generate Tx _ Req, so that the first _ data is actively delayed by one clock cycle to become first _ data _ d, and the time of Tx _ Req generation is kept.
Step 5, receiving the sending request signal, generating a receiving request signal, transmitting the data output by the sending module to the input end of the receiving module, and feeding back the receiving request signal as a sending response signal to the sending module, specifically: since the Latch _ En signal is in a high state, the D-side DATA signal Tx _ Req of the Latch 201 is immediately output to the Q-side so that the Rx request signal Rx _ Req is inverted to a high state and is accessed to the first synchronization request register 301 of the receiving end, and the signal is also accessed to the D-side of the first synchronization request register 501 as the Tx response signal Tx _ Ack and fed back to the transmitting module, and meanwhile, the Tx DATA Tx _ DATA of the Latch group 202 is immediately transmitted to the Q-side so that the Rx DATA Rx _ DATA of the receiving end is updated.
Step 6, pulling down the enable signals of the latch 201 and the latch group 202, and closing the transmission channel, specifically: the Rx _ Req signal is in a high state, Rx _ Req is connected to the CLR terminals of the rising edge response register 401 and the falling edge response register 402, no influence is generated on the outputs of the rising edge response register 401 and the falling edge response register 402, and Rx _ Ack is still in an initial low state; wait until the end of the second TXCLK clock cycle when fisrt _ data _ d goes low, at which time Latch _ En also goes low, so that the data at the inputs of Latch 201 and Latch set 202 is no longer loaded to the output.
Step three, the receiving module starts to receive data and generates a receiving response effective signal after the asynchronous transmission module updates the Rx _ Req signal:
step 7, carrying out synchronous beating operation on the receiving request signal, registering effective data, generating a receiving response effective signal and feeding back the effective signal to the asynchronous transmission module, specifically: an Rx _ Req signal is synchronized by RXCLK after passing through a first synchronization request register 301 and a second synchronization request register 302, so that the influence of a metastable state possibly caused when the Rx _ Req enters an RXCLK clock domain is eliminated, and then the Rx _ Req signal and the output of the Rx _ Req signal after passing through a third synchronization request register 303 are processed by an edge detection circuit to obtain a receiving end effective signal Rx _ Req _ Valid which is a pulse generated by a rising edge; the receiving end may register Rx _ DATA when Rx _ Req _ Valid is high to ensure Valid reception of DATA from the transmitting end, and the Rx _ Req _ Valid signal simultaneously serves as a reception response Valid signal Rx _ Ack _ Valid.
Since the Rx _ Req _ Valid signal is connected to the CLK terminals of the rising edge response register 401 and the falling edge response register 402, a data loading operation will occur in the rising edge response register 401 and the falling edge response register 402; for the rising edge response register 401, since the Rx _ Req and the RESET signals are both in a high state, and both the zero clearing and the RESET are invalid, the "1" at the D terminal is in a high state and is loaded to the Q terminal; for the falling edge response register 402, since Rx _ Req is in a high state, it is in a clear state, and the Q terminal still maintains a low state; to sum up, Rx _ Ack becomes a high state and thus Latch _ En signal becomes a high state, so that the input data of the Latch 201 and the Latch set 202 can be loaded to the output.
So far, the first batch of data is transmitted, and the principle of the transmission process of the subsequent data is consistent, which is as follows:
the asynchronous transmission module generates a sending response signal, feeds the sending response signal back to the sending module, and generates a sending response effective signal:
step 8, the Q terminal of the latch 201 is simultaneously connected to the D terminal of the first synchronous response register 501 as a Tx response signal Tx _ Ack signal, the Tx _ Ack signal is synchronized by TXCLK after passing through the first synchronous response register 501 and the second synchronous response register 502, the influence of metastable state possibly caused when the Tx _ Ack enters the TXCLK clock domain is eliminated, and the Tx _ Ack signal and the output after passing through the third synchronous response register 503 are processed by the edge detection circuit to obtain the transmitting terminal Valid signal Tx _ Ack _ Valid.
Sending a response effective signal to drive and generate a sending request signal, then accessing the sending request signal into an asynchronous transmission module, and simultaneously pulling down the request signal accessed into a receiving module:
in step 9, under the Tx _ Ack _ Valid driving, Tx _ Req _ Valid is changed to the high state again to drive the second flip register 102 to flip, the Tx _ Req signal is pulled to the low state and enters the D terminal of the latch 201, and accordingly, the data at the input terminal of the latch group 202 is also updated.
In step 10, since the Rx _ Req signal, i.e., the Tx _ Ack signal, enters the first synchronous request register 301 and the first synchronous response register 501 at the same time point, and TXCLK and RXCLK are independent from each other, the occurrence time of step 7 and step 9 may be consecutive to each other. The following is described separately for these two cases:
for the case that the step 7 occurs first, since the step 9 does not occur when the Latch _ En signal changes to the high state, and the DATA of the input end D and the output end Q of the Latch 201 and the Latch group 202 does not change, a new Rx _ Req _ Valid signal is not generated, the Rx _ Ack signal keeps the high state, that is, the DATA of the input end of the Latch 201 and the Latch group 202 can be loaded to the output end at any time, and then the Rx _ Req changes to the low state once the corresponding Tx _ Req and Tx _ DATA occur in the step 9, namely, the DATA is loaded to the output end;
for the case that step 9 occurs first, since the Rx _ Ack signal is in a low state, that is, the DATA at the input terminals of the latch 201 and the latch group 202 cannot be loaded to the output terminal, the whole circuit is maintained in the current state, and thereafter, in step 7, once the corresponding Tx _ Req and Tx _ DATA are loaded to the output terminal, Rx _ Req goes into a low state.
In step 11, when Rx _ Req goes low, the rising edge response register 401 is cleared, so that Latch _ En signal goes low, so that the data at the input terminals of the Latch 201 and the Latch group 202 is no longer loaded to the output terminal.
The receiving module starts receiving data and generates a reception response valid signal after the asynchronous transfer module updates the Rx _ Req signal:
step 12, Rx _ Req signals are synchronized by RXCLK after passing through the first synchronization request register 301 and the second synchronization request register 302, so that the influence of a metastable state possibly caused when Rx _ Req enters an RXCLK clock domain is eliminated, and then the Rx _ Req signals and output after passing through the third synchronization request register 303 are passed through an edge detection circuit together to obtain a receiving end effective signal Rx _ Req _ Valid which is a pulse generated by a falling edge; the receiving end may register Rx _ DATA when Rx _ Req _ Valid is high to ensure efficient reception of DATA from the transmitting end.
Step 13, since the Rx _ Req _ Valid signal is connected to the CLK terminals of the rising edge response register 401 and the falling edge response register 402, a data loading operation will occur in the rising edge response register 401 and the falling edge response register 402 at this time; for the rising edge response register 401, since the Rx _ Req signal is in a low level state, it is in a clear state, and the Q terminal still maintains the low level state; for the falling edge response register 402, because Rx _ Req is in a low level state, RESET is in a high level state, and zero clearing and RESET are both invalid, a "1" at the D terminal is in a high level state and is loaded to the Q terminal; to sum up, Rx _ Ack becomes a high state and thus Latch _ En signal becomes a high state, so that the input data of the Latch 201 and the Latch set 202 can be loaded to the output.
Then, the asynchronous transmission module generates a sending response signal, feeds the sending response signal back to the sending module, and generates a sending response effective signal:
in step 14, the Q terminal of the latch 201 is simultaneously connected to the D terminal of the first synchronous response register 501 as a Tx _ Ack signal, the Tx _ Ack signal is synchronized by TXCLK after passing through the first synchronous response register 501 and the second synchronous response register 502, so as to eliminate the influence of metastable state possibly caused when the Tx _ Ack enters the TXCLK clock domain, and then the Tx _ Ack signal and the output after passing through the third synchronous response register 503 are processed together by the edge detection circuit to obtain the Tx _ Ack _ Valid signal.
Sending a response effective signal to drive and generate a sending request signal, then accessing the sending request signal into an asynchronous transmission module, and simultaneously pulling up the request signal accessed into a receiving module:
in step 15, under the Tx _ Ack _ Valid driving, Tx _ Req _ Valid is again changed to a high state to drive the second toggle register 102 to send a toggle, the Tx _ Req signal is pulled to a high state and enters the D terminal of the latch 201, and accordingly, the data at the input terminal of the latch group 202 is also updated.
In step 16, since the Rx _ Req signal, i.e., the Tx _ Ack signal, enters the first synchronization request register 301 and the first synchronization response register 501 at the same time point, and TXCLK and RXCLK are independent from each other, the occurrence time of step 13 and step 15 may be consecutive to each other. The following is described separately for these two cases:
for the first occurrence of step 13, since step 15 does not occur when the Latch _ En signal changes to the high state, and the DATA of the input end D and the output end Q of the Latch 201 and the Latch group 202 do not change, no new Rx _ Req _ Valid signal is generated, the Rx _ Ack signal keeps the high state, that is, the input end DATA of the Latch 201 and the Latch group 202 can be loaded to the output end at any time, and then in step 15, once the corresponding Tx _ Req and Tx _ DATA occur, the Rx _ Req is loaded to the output end, and the Rx _ Req changes to the high state;
for the case that step 15 occurs first, since the Rx _ Ack signal is in a low state, that is, the DATA at the input terminals of the latch 201 and the latch group 202 cannot be loaded to the output terminal, the whole circuit is maintained in the current state, and thereafter, in step 13, once the corresponding Tx _ Req and Tx _ DATA are loaded to the output terminal, Rx _ Req goes into a high state.
In step 17, when Rx _ Req goes high, the falling edge response register 402 is cleared, so that Latch _ En signal goes low, so that the data at the input terminals of the Latch 201 and the Latch group 202 is no longer loaded to the output terminal.
Step 18, the procedure of the following steps is the same as the procedure from step 6 to step 17, and the above steps are repeated with the continuous transmission and synchronization of the data from the transmitting end to the receiving end, which is not described herein again.
The transmitting end clock TXCLK and the receiving end clock RXCLK are independent from each other, and the frequency of TXCLK can be larger than the frequency of RXCLK or smaller than the frequency of RXCLK. For the case where the TXCLK frequency is greater than the RXCLK frequency, the timing sequence for continuing to transmit data is shown in FIG. 4. Since the time points of Rx _ Req arriving at the first synchronization request register 301 and Tx _ Ack arriving at the first synchronization response register 501 are the same, and the frequency of TXCLK is greater than RXCLK, so that the Tx _ Ack _ Valid signal is pulled higher than the Rx _ Req _ Valid signal, the Tx _ Req signal flip occurs before the Rx _ Ack signal is pulled high, that is, a new request is generated at the transmitting end, and then the Latch _ En signals of the Latch 201 and the Latch group 202 are Valid again, the rate of the whole data transmission process depends on the clock frequency of the receiving end, and it can be known from fig. 4 that the time for completing one data transmission is 3 RXCLK periods. For the case where the TXCLK frequency is less than the RXCLK frequency, the timing sequence for continuing to transmit data is shown in FIG. 5. Since the time points of the Rx _ Req arriving at the first synchronous request register 301 and the Tx _ Ack arriving at the first synchronous response register 501 are the same, and the frequency of TXCLK is less than that of RXCLK, so that the Rx _ Req _ Valid signal is pulled higher than the Tx _ Ack _ Valid signal, the Rx _ Ack signal is pulled higher than the Tx _ Req signal, that is, the Latch _ En signals of the Latch 201 and the Latch set 202 are Valid first, and then a new request is generated from the transmitting end, so the rate of the whole data transmission process depends on the clock frequency of the transmitting end. As can be seen from fig. 5, the time for completing one data transmission is 3 TXCLK periods.
In summary, the synchronization method and apparatus of the embodiments of the present invention fully utilize the upper and lower edges of the data request signals Tx _ Req and Rx _ Req, and utilize the asynchronous transmission module to isolate the sending module from the receiving module, thereby ensuring that the sending end initiates a new sending request and the receiving end receives a new request to independently and concurrently operate, so that the data transmission rate across clock domains is only limited by the slower clock frequency of the sending or receiving end — for the case of the faster frequency of the sending end, the transmission speed is 3 clock cycles of the receiving end; for the case that the transmitting end is slow, the transmission rate is 3 transmitting end clock cycles. The method improves the data transmission efficiency to the maximum extent on the premise of eliminating the metastable state influence of cross-clock domain data transmission, and has obvious improvement compared with the prior method.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Although the foregoing has described the practice of the present invention in detail, it will be apparent to those skilled in the art that modifications may be made to the practice of the invention as described in the foregoing examples, or that certain features may be substituted in the practice of the invention. All changes, equivalents and modifications which come within the spirit and scope of the invention are desired to be protected.
Claims (7)
1. A synchronizer of asynchronous circuit, including sending module, asynchronous transmission module, receiving module, sending end clock TXCLK, receiving end clock RXCLK, characterized by that, the said sending module is driven by sending end clock TXCLK, produce, upgrade and send request and data, and send the response signal synchronously by way of the register beats; the asynchronous transmission module asynchronously transmits the request and the data from the sending module to the receiving module and simultaneously generates a sending response signal; the receiving module is driven by a receiving end clock RXCLK, synchronously receives the request signal in a register beating mode, acquires effective data when the edge of the synchronized request signal jumps, and simultaneously generates a receiving response signal;
the sending module transmits the sent DATA Tx _ DATA to the asynchronous transmission module, and the sending module specifically includes: the synchronous edge detection circuit comprises a first overturning register (101), a second overturning register (102), a first synchronous response register (501), a second synchronous response register (502), a third synchronous response register (503) and an edge detection circuit, wherein the edge detection circuit consists of two NAND gates and one OR gate; the first flip register (101) performs first data transmission when a first data signal first _ data is pulled high, and outputs a high level to enable a Latch enable signal Latch _ En to be in a high level state; a second inversion register (102) inverts the transmission request signal Tx _ Req when the transmission response Valid signal Tx _ Ack _ Valid is detected for the first data transmission or internally; a first synchronous response register (501) and a second synchronous response register (502) synchronously transmit a response signal Tx _ Ack; the third synchronous response register (503) and the edge detection circuit are connected in sequence with the or gate to detect whether the transmission response signal Tx _ Ack is effectively inverted, if the transmission response signal Tx _ Ack _ Valid is inverted, a transmission response effective signal Tx _ Ack _ Valid is generated through the or gate, the first data signal first _ data and the transmission response effective signal Tx _ Ack _ Valid obtain a high-level signal through the or gate, namely, the transmission request effective signal Tx _ Req _ Valid is accessed to the En end of the second inversion register (102), the Q end of the second inversion register (102) is inverted to obtain a transmission request signal Tx _ Req, and the transmission request signal Tx _ Req is accessed to the asynchronous transmission module.
2. The synchronous apparatus of an asynchronous circuit according to claim 1, wherein said asynchronous transmission module receives and transmits a request Tx _ Req and DATA Tx _ DATA, the asynchronous transmission module comprising: the DATA transmission device comprises a latch (201), a latch group (202), a rising edge response register (401) and a falling edge response register (402), wherein the latch (201) receives a transmission request signal Tx _ Req, the latch group (202) receives DATA Tx _ DATA, and when the latch (201) and the latch group (202) generate a receiving response signal Rx _ Ack in a first DATA transmission or asynchronous transmission module, the Tx _ Req and the Tx _ DATA are transmitted to respective output ends to become a request signal Rx _ Req and receiving DATA Rx _ DATA accessing a receiving module; the request signal Rx _ Req is also used as a transmission response signal Tx _ Ack fed back to the transmission module; the rising edge response register (401) and the falling edge response register (402) control a reception response signal Rx _ Ack, which is equivalent to a Latch _ En signal after the first data transfer transmission is completed, to be changed into a high level or a low level state according to the states of the Tx _ Ack signal and the reception response Valid signal Rx _ Ack _ Valid signal.
3. The synchronous apparatus of an asynchronous circuit as claimed in claim 2, wherein said Latch enable signal Latch _ En is specifically: the first _ data signal is delayed by one clock cycle to become a first _ data _ d signal, and kept as long as the time when the Tx _ Req signal is generated, the first _ data _ d signal and the Rx _ Ack signal pass through an or gate to obtain a Latch enable signal Latch _ En.
4. The synchronous device of claim 2, wherein the receiving module receives the collected valid DATA, so that the RX _ DATA completes updating, the receiving module comprises a first synchronous request register (301), a second synchronous request register (302), a third synchronous request register (303), and an edge detection circuit composed of two nand gates and one or gate, which are connected in sequence, the first synchronous request register (301) and the second synchronous request register (302) synchronously receive the RX _ Req signal to the third synchronous request register (303), and the edge detection circuit composed of two nand gates and one or gate detect whether the RX _ Req signal is effectively inverted, when the synchronous request signal output by the second synchronous request register (302) is inverted, the or gate generates a pulse signal, the pulse signal is a reception request Valid signal Rx _ Req _ Valid and a reception response Valid signal Rx _ Ack _ Valid.
5. A method for synchronizing means for synchronizing asynchronous circuits according to any of claims 1 to 4, characterized in that it comprises the following steps:
step one, when data generated by the front end of a sending module needs to be sent to a receiving module, the sending module enters a sending state and starts to send first data;
step two, the asynchronous transmission module transmits the request signal and the data generated by the sending module to the receiving module and generates a sending response signal at the same time;
step three, the receiving module starts to receive data and generates a receiving response effective signal after the asynchronous transmission module updates the request signal;
the first step specifically comprises:
step 1, carrying out global reset operation;
step 2, when sending data, the sending module generates a sending request signal;
and 3, turning over the sending request signal to access the abnormal transmission module.
6. The method according to claim 5, wherein the second step specifically comprises:
step 4, pulling up enabling signals of a latch (201) and a latch group (202) of the asynchronous transmission module, and opening a transmission channel;
step 5, receiving the sending request signal, generating a receiving request signal, transmitting the data output by the sending module to the input end of the receiving module, and feeding back the receiving request signal as a sending response signal to the sending module;
and 6, pulling down the enable signals of the latch (201) and the latch group (202) and closing the transmission channel.
7. The method according to claim 6, wherein the third step specifically comprises:
and 7, carrying out synchronous beating operation on the receiving request signal, registering effective data, and generating a receiving response effective signal and feeding back the effective signal to the asynchronous transmission module.
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