CN105610532B - The method for transmission processing and device of signal, equipment - Google Patents
The method for transmission processing and device of signal, equipment Download PDFInfo
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- CN105610532B CN105610532B CN201410631790.3A CN201410631790A CN105610532B CN 105610532 B CN105610532 B CN 105610532B CN 201410631790 A CN201410631790 A CN 201410631790A CN 105610532 B CN105610532 B CN 105610532B
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04J3/00—Time-division multiplex systems
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- H04J3/06—Synchronising arrangements
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Abstract
The present invention provides a kind of method for transmission processing of signal and devices, equipment, wherein, the above method includes: the request signal for detecting the first equipment generation in the first clock domain, wherein the request signal is used to indicate permission and receives data in first clock domain；The request signal is converted into holding signal, the holding signal is persistently to keep effective signal before second clock domain synchronizes successfully the holding signal；The holding signal is synchronized using the second clock domain, obtains the output signal of the request signal, and the output signal is exported to the second equipment being located in the second clock domain.Using above-mentioned technical proposal provided by the invention, it solves in the related technology, cross clock domain signals transmission, which exists, to be occupied more hardware resource, realizes the technical problems such as complexity, thus guaranteeing that elimination is metastable simultaneously, reduce hardware resource, reduces the complexity of realization.
Description
Technical field
The present invention relates to the communications field, method for transmission processing and device in particular to a kind of signal, equipment.
Background technique
In the communications field or hardware logic design field, the system in single clock domain and few is pertained only to, for comparing
Usually there is the transmission between multiple clock domain signals in system, due to metastable presence, if signal passes in complicated application
Transmission method is not proper, will cause metastable a wide range of propagation, influences the normal function of system.Using rationally efficiently across clock
Domain transmission method can guarantee that system is stable and function is normal to avoid metastable appearance.
In the related technology, commonly it can be divided into following a few classes across the method for clock signal transmission:
One, directly to the signal interactive across clock is needed, utilize two-stage or the clock of three-level register pair destination clock-domain
It carries out playing bat processing, signal is synchronized to destination clock-domain, is completed across clock transfer.
Two, across clock signal biography is handled using asynchronous first in, first out (First-In First-Out, referred to as FIFO)
It is defeated.Two clocks of asynchronous FIFO are respectively intended to complete that data are written into FIFO and read data from FIFO.Pass through one
Complete write-in and reading process complete the cross clock domain transmission of signal.
Although can use the signal transmission that above-mentioned technical proposal realizes cross clock domain, there are following technical problems:
If directly carrying out register using the first scheme to signal and playing bat processing, first it cannot be guaranteed that eliminating metastable state, and
During register plays bat, the clock domain as belonging to signal changes, it is possible to cause the loss of signal；If using
Second scheme is handled the transmission of cross clock domain signal using asynchronous FIFO mode, although Asia can relatively efficiently be eliminated
Stable state, but FIFO itself occupies more hardware resource, increases logic complexity.
In view of the above problems in the related art, it there is no effective solution scheme at present.
Summary of the invention
The present invention provides a kind of method for transmission processing of signal and device, equipment, at least solve in the related technology across
Clock domain signals transmission, which exists, to be occupied more hardware resource, realizes the technical problems such as complexity.
According to an aspect of the invention, there is provided a kind of method for transmission processing of signal, comprising: detect the first clock
The request signal that the first equipment generates in domain, wherein the request signal is used to indicate permission and receives in first clock domain
Data；The request signal is converted into holding signal, the holding signal is same to the holding signal in second clock domain
Before walking successfully, effective signal is persistently kept；The holding signal is synchronized using the second clock domain, obtains institute
The output signal of request signal is stated, and the output signal is exported to the second equipment being located in the second clock domain.
Preferably, after being synchronized using the second clock domain to the holding signal, further includes: pass through described
One clock domain synchronizes the output signal, obtains for making the signal for keeping invalidating signal.
Preferably, the output signal is exported to the second equipment being located in the second clock domain, comprising: connect
Receive the answer signal generated according to the output signal in the second clock domain；The answer signal is synchronized to described first
Clock domain, and the answer signal after synchronizing is exported to first equipment, wherein the answer signal is for triggering institute
It states the first equipment and receives the data from second equipment.
Preferably, at least one of signal is 1 bit: the request signal, the holding signal, output letter
Number.
According to another aspect of the present invention, a kind of transmission processing device of signal is provided, comprising: detection module is used
In the request signal for detecting that the first equipment generates in the first clock domain, wherein the request signal is used to indicate permission in institute
It states the first clock domain and receives data；Conversion module, for the request signal to be converted to holding signal, the holding signal is
Before second clock domain synchronizes successfully the holding signal, effective signal is persistently kept；First synchronization module, for benefit
The holding signal is synchronized with the second clock domain, obtains the output signal of the request signal；Output module is used
In the output signal is exported to be located at the second clock domain in the second equipment.
Preferably, above-mentioned apparatus further include: the second synchronization module, for being believed by first clock domain the output
It number synchronizes, obtains for making the signal for keeping invalidating signal.
Preferably, above-mentioned apparatus further include: receiving module, for receiving according to the output signal in the second clock
The answer signal that domain generates；Third synchronization module for the answer signal to be synchronized to first clock domain, and will synchronize
The answer signal afterwards is exported to first equipment, wherein the answer signal is received for triggering first equipment
Data from second equipment.
According to a further aspect of the invention, a kind of transmission processing apparatus of signal is provided, comprising: controller is used for
When detecting the request signal of the first equipment in the first clock domain, the request signal is converted into holding signal, with
And the holding signal is sent to SYN register, wherein the request signal is used to indicate permission in first clock
Domain receives data, and the holding signal is before second clock domain synchronizes successfully the holding signal, and lasting holding is effective
Signal；The SYN register is connect with the controller, for using the second clock domain to the holding signal into
Row synchronizes, and obtains the output signal of the request signal, and the output signal is exported in the second clock domain
The second equipment.
Preferably, above equipment further include: feedback register is connect with the SYN register, is used for the output
Signal feeds back to the controller, and is synchronized by first clock domain to the output signal, obtains for making
The signal for keeping invalidating signal is stated, and the signal for keeping invalidating signal is sent to the controller.
Preferably, the controller is also used to receive and be answered according to the output signal what the second clock domain generated
Answer signal, and the answer signal be synchronized to first clock domain, and the answer signal after synchronizing export to
First equipment, wherein the answer signal receives the data from second equipment for triggering first equipment.
Through the invention, holding signal is converted to using the request signal for generating the first equipment in the first clock domain, and
Using the second clock domain to the holding signal technological means that synchronizes and export, solve in the related technology, across
Clock domain signals transmission, which exists, to be occupied more hardware resource, realizes the technical problems such as complexity, thus metastable guaranteeing to eliminate
While state, reduce hardware resource, reduces the complexity of realization.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes part of this application, this hair
Bright illustrative embodiments and their description are used to explain the present invention, and are not constituted improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is the flow chart according to the method for transmission processing of the signal of the embodiment of the present invention；
Fig. 2 is the structural block diagram according to the transmission processing device of the signal of the embodiment of the present invention；
Fig. 3 is another structural block diagram according to the transmission processing device of the signal of the embodiment of the present invention；
Fig. 4 is the structural block diagram according to the transmission processing apparatus of the signal of the embodiment of the present invention；
Fig. 5 is another structural block diagram according to the transmission processing apparatus of the signal of the embodiment of the present invention；
Fig. 6 is the realization principle schematic diagram transmitted according to the cross clock domain signal of the embodiment of the present invention；
Fig. 7 is to be shown according to synchronization stretching (Sync&Pulse Broaden) inside modules working principle of the embodiment of the present invention
It is intended to；
Fig. 8 is according to the embodiment of the present invention for embodying the waveform diagram of signal cross clock domain transmission process.
Specific embodiment
Hereinafter, the present invention will be described in detail with reference to the accompanying drawings and in combination with Examples.It should be noted that not conflicting
In the case of, the features in the embodiments and the embodiments of the present application can be combined with each other.
The embodiment of the present invention cannot thoroughly avoid metastable state across time-domain transmission for signal in the related technology, occupy more hard
Part resource realizes the disadvantages of complicated, a kind of implementation of signal transmission between different clock-domains is provided, for realizing signal
Transmitting between different clock-domains.The transmission of signal between the clock domain that the program supports frequency, phase entirely different, is supported
Pulse width is less than the transmission of the signal of clock cycle.The implementation described further below.
Fig. 1 is the flow chart according to the method for transmission processing of the signal of the embodiment of the present invention.As shown in Figure 1, this method packet
Include following processing step:
Step S102 detects the request signal that the first equipment generates in the first clock domain, wherein the request signal is used for
Instruction allows to receive data in above-mentioned first clock domain；
Above-mentioned request signal is converted to holding signal by step S104, and above-mentioned holding signal is in second clock domain to upper
It states before keeping signal to synchronize successfully, persistently keeps effective signal；
Step S106 synchronizes above-mentioned holding signal using above-mentioned second clock domain, obtains above-mentioned request signal
Output signal, and above-mentioned output signal is exported to the second equipment being located in above-mentioned second clock domain.
By above-mentioned each processing step, since the request signal for being sent to second clock domain is converted to holding signal,
And effective signal can be persistently kept before the holding signal is synchronized successfully by second clock domain, it is thereby achieved that
The broadening of pulse signal, metastable defect cannot thoroughly be eliminated by avoiding, also, save register resources, reduce reality
Now across the complexity of time-domain transmission channel.
In order to save operation resource, avoid that signal is kept persistently to keep, it is also necessary to set above-mentioned holding signal in vain
It sets, in a preferred embodiment of the invention, can use above-mentioned output signal and be configured: utilizing above-mentioned second clock
After domain synchronizes above-mentioned holding signal, above-mentioned output signal is synchronized by above-mentioned first clock domain, is used
In the signal for making above-mentioned holding invalidating signal, i.e., it will be divided into two-way by above-mentioned output signal obtained in step S106, one
Road is exported to above-mentioned second equipment, in addition all the way for generating the signal for making above-mentioned holding invalidating signal.In this way, can be right
When above-mentioned output signal synchronizes successfully, remove above-mentioned holding signal (i.e. setting keeps invalidating signal).Wherein, in concrete application mistake
Cheng Zhong, by keep signal be set as invalid process can be presented as by keep signal be set as low level, but not limited to this.
For realizing the process of above-mentioned holding invalidating signal by reflexive infeed mechanism, for example, in step S102-
When executing subject in S106 is a designated equipment (such as controller), can by the first clock domain to above-mentioned output signal into
After row synchronizes, the designated equipment is fed back to, sets invalid for above-mentioned holding signal by the designated equipment.
Before step S102, i.e., the request signal for being sent to second clock domain is converted into the effective holding signal of holding
Before, it is also necessary to detect that the first clock domain generates above-mentioned request signal, also, after exporting above-mentioned output signal, receive
The answer signal generated according to above-mentioned output signal in above-mentioned second clock domain；When above-mentioned answer signal is synchronized to above-mentioned first
Clock domain, and the above-mentioned answer signal after synchronizing is exported to above-mentioned first equipment, wherein above-mentioned answer signal is above-mentioned for triggering
First equipment receives the data from above-mentioned second equipment.Data can be realized in the transmission of different clock-domains in this way.One
During a concrete application, following treatment process can be shown as, but not limited to this:
Above-mentioned second equipment will need the data sent to be put into interface signal line Data_ while sending answer signal
Out is upper and maintains, and after the first equipment receives above-mentioned answer signal, sets above-mentioned request signal in vain, and receive
Data from the second equipment.
It in a preferred embodiment of the invention, can be by above-mentioned request signal, above-mentioned guarantor in order to save operation resource
It holds at least one of signal, above-mentioned output signal and is set as 1 bit.Register resources can be saved in this way:
1, it is clapped when beat using two-stage or three-level register, when data are synchronized to this method of destination register, example
The data by 2 8bit are such as needed to pass to destination clock-domain, then it is 2*8*2=that two-stage, which beats the register number used when clapping,
32, it is 2*8*3=48 that three-level, which beats the register number used when clapping,
And when using the scheme of the embodiment of the present invention, the request used due to handshake phase, feedback, to keep signal be all single
Bit, the register number used in intermediate handshake procedure are far smaller than 8 multiple, and data are disposably to pass to after the completion of shaking hands
Destination clock-domain, pilot process do not need register participation, so can beat the method clapped than two-stage or three-level saves 3 times or more
Register number.
2, when using FIFO to realize across clock transfer, many registers can be used to realize by building FIFO itself, example
16 registers are at least used if when it is 2 that width, which is 8 depth, using register number and far more than the embodiment of the present invention
Scheme.
The embodiment of the present invention can be reduced the reason of register usage amount, be that multiple single-bit signals has been used to complete centre
Shake hands, shake hands after the completion of just disposably the data of more bits are passed on, avoid multi-bit data in intermediate steps
Transmitting, also just reduce occupied register number.
The embodiment of the invention also provides a kind of transmission processing devices of signal, for realizing the above method, such as Fig. 2 institute
Show, which includes following processing module:
Detection module 20, for detecting the request signal of the first equipment generation in the first clock domain, wherein request letter
It number is used to indicate permission and receives data in above-mentioned first clock domain；
Conversion module 22 is connected to detection module 20, for above-mentioned request signal to be converted to holding signal, above-mentioned holding
Signal is persistently to keep effective signal before second clock domain synchronizes successfully above-mentioned holding signal；
First synchronization module 24, is connected to conversion module 22, for utilizing above-mentioned second clock domain to above-mentioned holding signal
It synchronizes, obtains the output signal of above-mentioned request signal；
Output module 26 is connected to the first synchronization module 24, for exporting above-mentioned output signal to positioned at above-mentioned second
The second equipment in clock domain.
The function of being realized by above-mentioned modules, equally can to avoid cannot thoroughly eliminate metastable defect, also,
Register resources are saved, reduces and realizes the complexity across time-domain transmission channel.
In a preferred embodiment, the transmission processing device of signal provided in an embodiment of the present invention, as shown in figure 3, also
It may include: the second synchronization module 28, for being synchronized by above-mentioned first clock domain to above-mentioned output signal, be used for
Make the signal of above-mentioned holding invalidating signal.
During a preferred implementation, the transmission processing device of signal provided in an embodiment of the present invention, as shown in figure 3,
It can also include: receiving module 30, for receiving the answer signal generated according to above-mentioned output signal in above-mentioned second clock domain；
Third synchronization module 32 is connected to receiving module 30, for above-mentioned answer signal to be synchronized to above-mentioned first clock domain, and will be same
Above-mentioned answer signal after step is exported to above-mentioned first equipment, wherein above-mentioned answer signal connects for triggering above-mentioned first equipment
Receive the data from above-mentioned second equipment.
The embodiment of the present invention also provides a kind of transmission processing apparatus of signal, as shown in figure 4, the equipment includes:
Controller (also known as control register) 40, in the request for detecting the first equipment in the first clock domain
When signal, above-mentioned request signal is converted into holding signal, and above-mentioned holding signal is sent to SYN register, wherein
Above-mentioned request signal is used to indicate permission and receives data in above-mentioned first clock domain, and above-mentioned holding signal is in second clock domain pair
Before above-mentioned holding signal synchronizes successfully, effective signal is persistently kept；
SYN register 42 is connect with controller 40, for being carried out using above-mentioned second clock domain to above-mentioned holding signal
It is synchronous, the output signal of above-mentioned request signal is obtained, and above-mentioned output signal is exported in above-mentioned second clock domain
Second equipment.
During a preferred implementation, as shown in figure 5, can also include: feedback register 44, with SYN register 42
Connection, for above-mentioned output signal to be fed back to above controller, and by above-mentioned first clock domain to above-mentioned output signal into
Row synchronizes, and obtains the signal for making above-mentioned holding invalidating signal, and the signal of above-mentioned holding invalidating signal is sent to
State controller 40.
In a preferred embodiment of the present invention, controller 40 is also used to receive according to above-mentioned output signal above-mentioned the
The answer signal that two clock domains generate, and is synchronized to above-mentioned first clock domain for above-mentioned answer signal, and upper after synchronizing
It states answer signal to export to above-mentioned first equipment, wherein above-mentioned answer signal comes from for triggering above-mentioned first equipment reception
State the data of the second equipment.
It should be noted that register involved in the transmission processing apparatus of the signal provided in the embodiment of the present invention
(such as SYN register, feedback register etc.) can be one or more, and particular number can be determines according to actual conditions.
Above-described embodiment in order to better understand is described in detail below in conjunction with preferred embodiment.
The preferred embodiment of the present invention provides a kind of biography of signal that passes through handshake and can broaden automatically according to feedback
Defeated system realizes the cross clock domain transmission of signal, improves the correctness of signal transmission, guarantees the work of system normal table.
The transmission processing device of signal provided in this embodiment mainly includes following sections: host (is equivalent to above-mentioned reality
Apply the first equipment in example), slave (the second equipment being equivalent in above-described embodiment) and synchronization stretching module (be equivalent to above-mentioned
The transmission processing apparatus of the signal provided in embodiment and/or the transmission processing device of signal).Wherein host corresponds to clock domain and is
(host clock) Master Clock, it is slave clock (Slave Clock), synchronization stretching inside modules that slave, which corresponds to clock domain,
Existing Master Clock, and have Slave Clock.
● the function of host has: issuing request signal, receives data, terminates current request letter according to slave answer signal
Number.
● the function of slave has: receiving request signal, sends data, sends answer signal.
● the function of synchronization stretching module has: the request signal of host being synchronized, certainly according to the response situation of slave
It is dynamic to be broadened, and it is transferred to slave module；The answer signal of slave is synchronized, host is transferred to.
The realization principle of cross clock domain signal transmission is as shown in Figure 6.
(1) host (Master) issues request signal (Master_Req_In), and expression can receive data.
(2) synchronization stretching module (Sync&Pulse Broaden) working principle is as shown in Figure 7.Control register receives master
The request signal (Master_Req_In) of machine, using Master_Req_In as signal is judged, in Master Clock clock
Domain generates a single-bit and keeps signal (keep), and keep signal passes through the SYN register (1,2) of Slave Clock clock domain
After synchronizing, the output signal (Maste_Req_Out) for becoming request signal is output to slave as request signal.Then,
The output signal (Maste_Req_Out) of request signal, it is synchronous by the feedback register (1,2) of Master Clock clock domain
Afterwards, the clear signal for becoming holding (keep) signal, feeds back to control register, and keep signal is returned to low level.
By the method for widening of step (2), can be synchronized to avoid host request signal (Master_Req_In)
It is lost when Slave Clock clock domain: when host clock and slave clock difference cause synchronization failure for the first time greatly very much, keep letter
Number since clear signal can not be received, it will be always held at high level, until by the correct sample-synchronous of Slave Clock at
Function；After synchronizing successfully, keep receives clear signal, it will is reduced to low level in time.
(3) after slave (Slave) receives the output signal Master_Req_Out of request signal, existed using the signal
Slave Clock clock domain generates an answer signal Slave_Ack_In, while the data sent will be needed to be put into interface letter
On number line Data_Out and maintain.
(4) answer signal (Slave_Ack_In) is synchronized to by synchronization stretching module (Sync&Pulse Broaden)
Master Clock clock domain, is output to host after becoming Slave_Ack_Out.
(5) after Host Detection to the output signal Slave_Ack_Out of normal answer signal, by request signal
Master_Req_In retracts low level, while the data in slave interface signal line being deposited into, this completes data from
Transmission of the slave to host
(6) after slave detects that host request signal retracts low level, by the answer signal Slave_Ack_In of oneself
Become low level.
By above 6 steps, the transmission that cross clock domain signal is realized by handshake is completed.In addition if
(3) step fails response, and host module can initiate request signal again, successfully completes data transmission until both sides shake hands.
The waveform diagram of Fig. 8 equally embodies the entire protocol of signal cross clock domain transmission.Wherein clk and pclk be two not
Same clock, signal data1~data4 will be transferred to clk from pclk.It is that clk clock domain issues request signal Master_ first
Req_In.Synchronization stretching module receives the request signal Master_Req_In of host, using Master_Req_In as judgement
Signal generates a single-bit in Master Clock clock domain and keeps signal keep, when keep signal passes through Slave Clock
After clock domain synchronizes, becomes the output signal Maste_Req_Out of request signal, be output to slave.Then, Maste_Req_
After Out is synchronized further through Master Clock clock domain, become the clear signal for keeping keep signal, for drawing keep signal
It is back to low level.After slave receives request signal Master_Req_Out, generated using the signal in Slave Clock clock domain
One answer signal Slave_Ack_In, while the data sent will be needed to be put on interface signal line Data_Out and kept
Firmly.When answer signal Slave_Ack_In is synchronized to Master Clock by synchronization stretching module (Sync&Pulse Broaden)
Clock domain is output to host after becoming Slave_Ack_Out.It, will after Host Detection to normal answer signal Slave_Ack_Out
Request signal Master_Req_In retracts low level, while the data in slave interface signal line being deposited into, and thus completes
Transmission of the data from slave to host.After slave detects that host request signal retracts low level, by the answer signal of oneself
Slave_Ack_In also becomes low level.
In conclusion the embodiment of the present invention realize it is following the utility model has the advantages that (1) with directly using register beat clap compare,
Metastable state cannot thoroughly be eliminated by avoiding, and when needing the signal that transmits very much, and be capable of reduction register resources at double
It uses.(2) it is compared with asynchronous FIFO, reduces the use of module complexity and hardware resource, implementation method is more succinct.
In another embodiment, a kind of software is additionally provided, the software is for executing above-described embodiment and preferred reality
Apply technical solution described in mode.
In another embodiment, a kind of storage medium is additionally provided, above-mentioned software is stored in the storage medium, it should
Storage medium includes but is not limited to: CD, floppy disk, hard disk, scratch pad memory etc..
Obviously, those skilled in the art should be understood that each module of the invention or each step can use general calculating
Device realizes that they can be concentrated on a single computing device, or be distributed in network constituted by multiple computing devices
On, optionally, they can be realized with the program code that computing device can perform, it is thus possible to be stored in storage
It is performed by computing device in device, and in some cases, it can be to be different from shown by sequence execution herein or retouch
The step of stating, perhaps they are fabricated to each integrated circuit modules or by the multiple modules or step system in them
Single integrated circuit module is made to realize.In this way, the present invention is not limited to any specific hardware and softwares to combine.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of method for transmission processing of signal characterized by comprising
Detect the request signal that the first equipment generates in the first clock domain, wherein the request signal, which is used to indicate, allows institute
It states the first equipment and receives data in first clock domain；
The request signal is converted into holding signal, the holding signal is synchronous to the holding signal in second clock domain
Before success, effective signal is persistently kept；
The holding signal is synchronized using the second clock domain, obtains the output signal of the request signal, and will
The output signal is exported to the second equipment being located in the second clock domain.
2. the method according to claim 1, wherein being carried out using the second clock domain to the holding signal
After synchronization, further includes:
The output signal is synchronized by first clock domain, is obtained for making the letter for keeping invalidating signal
Number.
3. the method according to claim 1, wherein exporting the output signal to positioned at the second clock
After the second equipment in domain, comprising:
Receive the answer signal generated according to the output signal in the second clock domain；
The answer signal is synchronized to first clock domain, and the answer signal after synchronizing is exported to described first
Equipment, wherein the answer signal receives the data from second equipment for triggering first equipment.
4. according to the method in any one of claims 1 to 3, which is characterized in that at least one of signal is 1 bit:
The request signal, the holding signal, the output signal.
5. a kind of transmission processing device of signal characterized by comprising
Detection module, for detecting the request signal of the first equipment generation in the first clock domain, wherein the request signal is used
First equipment is allowed to receive data in first clock domain in instruction；
Conversion module, for the request signal to be converted to holding signal, the holding signal in second clock domain to institute
It states before keeping signal to synchronize successfully, persistently keeps effective signal；
First synchronization module obtains the request letter for synchronizing using the second clock domain to the holding signal
Number output signal；
Output module, for exporting the output signal to the second equipment being located in the second clock domain.
6. device according to claim 5, which is characterized in that further include:
Second synchronization module obtains described for making for being synchronized by first clock domain to the output signal
Keep the signal of invalidating signal.
7. device according to claim 5, which is characterized in that further include:
Receiving module, for receiving the answer signal generated according to the output signal in the second clock domain；
Third synchronization module, the response for the answer signal to be synchronized to first clock domain, and after synchronizing
Signal is exported to first equipment, wherein the answer signal is received for triggering first equipment from described second
The data of equipment.
8. a kind of transmission processing apparatus of signal characterized by comprising
Controller, for when detecting the request signal of the first equipment in the first clock domain, the request signal to be turned
It is changed to holding signal, and the holding signal is sent to SYN register, wherein the request signal is used to indicate permission
First equipment receives data in first clock domain, and the holding signal is in second clock domain to the holding signal
Before synchronizing successfully, effective signal is persistently kept；
The SYN register is connect with the controller, for being carried out using the second clock domain to the holding signal
It is synchronous, the output signal of the request signal is obtained, and the output signal is exported in the second clock domain
Second equipment.
9. equipment according to claim 8, which is characterized in that further include:
Feedback register is connect with the SYN register, for the output signal to be fed back to the controller, and is passed through
First clock domain synchronizes the output signal, obtains the signal for making the holding invalidating signal, and will
The signal for keeping invalidating signal is sent to the controller.
10. equipment according to claim 8, which is characterized in that the controller is also used to receive and be believed according to the output
Number answer signal generated in the second clock domain, and the answer signal is synchronized to first clock domain, and will
The answer signal after synchronizing is exported to first equipment, wherein the answer signal is for triggering first equipment
Receive the data from second equipment.
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| CN201410631790.3A CN105610532B (en) | 2014-11-11 | 2014-11-11 | The method for transmission processing and device of signal, equipment |
| PCT/CN2015/074533 WO2016074402A1 (en) | 2014-11-11 | 2015-03-18 | Signal transmission processing method and apparatus, and device |
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| CN201410631790.3A CN105610532B (en) | 2014-11-11 | 2014-11-11 | The method for transmission processing and device of signal, equipment |
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| CN112148655B (en) * | 2019-06-28 | 2023-11-17 | 深圳市中兴微电子技术有限公司 | Multi-bit data clock domain crossing processing method and device |
| CN113821075A (en) * | 2021-09-27 | 2021-12-21 | 上海航天计算机技术研究所 | Clock domain crossing processing method and device for asynchronous multi-bit signal |
| CN114117972B (en) * | 2022-01-26 | 2022-06-10 | 之江实验室 | Synchronous device and method of asynchronous circuit |
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| GB2478795B (en) * | 2010-03-19 | 2013-03-13 | Imagination Tech Ltd | Requests and data handling in a bus architecture |
| US7977976B1 (en) * | 2010-05-21 | 2011-07-12 | Apple Inc. | Self-gating synchronizer |
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