CN112148655B - Multi-bit data clock domain crossing processing method and device - Google Patents
Multi-bit data clock domain crossing processing method and device Download PDFInfo
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Abstract
The application provides a multi-bit data cross-clock domain processing method and device; wherein the method comprises the following steps: acquiring data output from a transmitting clock domain side to a receiving clock domain side, wherein the transmitting clock domain and the receiving clock domain are different clock domains; detecting whether the data changes; under the condition that the data changes, updating the data and outputting the updated data; and under the condition that the data is unchanged, maintaining the original output data. The application solves the problems of high hardware cost and high transmission delay caused by the need of bidirectional interaction between the sending clock domain and the receiving clock domain in the processing mode of cross-clock domain transmission in the related technology.
Description
Technical Field
The application relates to the field of computers, in particular to a multi-bit data clock domain crossing processing method and device.
Background
In modern electronic systems, digital integrated circuit systems are increasingly large in scale, contain more and more modules, support more and more complex functions, and have higher power consumption requirements. Thus, socs (System on Chip) now typically include multiple clock domains, while clock architecture designs take the form of GALS, namely globally asynchronous (Global Asynchronous) processing and locally synchronous (Local Synchronous) processing.
The GALS clock architecture has many advantages, such as (1) on the premise of meeting performance requirements, each module can respectively operate at a clock frequency as low as possible, and dynamic power consumption is smaller; (2) The clock is easy to realize, the clock tree is small, the time sequence is easy to converge, and the area is smaller.
In a GALS SoC, there is inevitably a data transfer across the clock domain. Because of the uncertainty in the phase relationship between asynchronous clocks, it is easy for data to be transferred from one clock domain to another asynchronous clock domain without meeting the setup time (setup time) or hold time (hold time) of the registers, resulting in the occurrence of meta-stability. Metastable problems may result in erroneous sampling of the transmitted data, and if not handled properly, more severe may result in the SoC system being in an erroneous state, thus not functioning properly, and being difficult to locate.
For single bit signals, a two-stage register synchronization mode is generally adopted during cross-clock domain transmission, so that the probability of metastability is effectively reduced. Even if metastable state occurs, the single bit signal adopts two-stage synchronous processing, and error data sampling can not occur, and only the delay of data transmission is changed.
For multi-bit signals, only two-stage register synchronization cannot be adopted during cross-clock domain transmission. Because there is a data correlation (data coherence) between the multi-bit signals, that is, if a metastable state occurs in a certain bit or multi-bit signal, erroneous intermediate data may be sampled, thereby causing an error state in the SoC system.
In the related art, the following three processing modes of the multi-bit signal cross-clock domain transmission are adopted: 1) Enabling a signal synchronization mode; 2) Handshake (handshake) interaction; 3) Asynchronous FIFO mode. The above modes in the related art all need the bidirectional interaction of the control signals of the sending clock domain and the receiving clock domain, and have the advantages of complex realization, high hardware cost and high transmission delay.
Aiming at the problems in the related art, no effective technical scheme exists at present.
Disclosure of Invention
The embodiment of the application provides a multi-bit data cross-clock domain processing method and device, which at least solve the problems of high hardware cost and high transmission delay caused by bidirectional interaction between a sending clock domain and a receiving clock domain in a cross-clock domain transmission processing mode in the related technology.
According to one embodiment of the present application, there is provided a method for processing multi-bit data across clock domains, including: acquiring data output from a transmitting clock domain side to a receiving clock domain side, wherein the transmitting clock domain and the receiving clock domain are different clock domains; detecting whether the data changes; under the condition that the data changes, updating the data and outputting the updated data; and under the condition that the data is unchanged, maintaining the original output data.
According to another embodiment of the present application, there is provided a processing apparatus for multi-bit data crossing clock domains, including: the device comprises an acquisition module, a receiving module and a processing module, wherein the acquisition module is used for acquiring data output to a receiving clock domain side by a transmitting clock domain side, wherein the transmitting clock domain and the receiving clock domain are different clock domains; the detection module is used for detecting whether the data change; the processing module is used for updating and outputting the data under the condition that the data is detected to change; and under the condition that the data is detected not to change, the original output data is maintained.
According to the application, the data output from the transmitting clock domain side to the receiving clock domain side is obtained, wherein the transmitting clock domain and the receiving clock domain are different clock domains, so that whether the data change is detected, and the data is updated and then output under the condition that the data change; under the condition that the data is not changed, the original output data is maintained; therefore, the method and the device realize the processing of the multi-bit data crossing the clock domain under the condition of relative independence of the sending clock domain and the receiving clock domain, solve the problems of high hardware cost and high transmission delay caused by the need of bidirectional interaction of the sending clock domain and the receiving clock domain in the processing mode of crossing the clock domain transmission in the related technology, and can use more application scenes and the whole implementation mode is efficient and concise.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1 is a flow chart of a method of processing multi-bit data across clock domains in accordance with an embodiment of the present application;
FIG. 2 is a schematic diagram of a multi-bit data cross-clock domain transfer apparatus according to an embodiment of the present application;
FIG. 3 is a schematic diagram of multi-bit data cross-clock domain transmission according to an embodiment of the application;
FIG. 4 is a schematic diagram of signal waveforms at various keys according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a multi-bit data cross-clock domain processing apparatus in accordance with an alternative embodiment of the application.
Detailed Description
The application will be described in detail hereinafter with reference to the drawings in conjunction with embodiments. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.
Example 1
In this embodiment, a method for processing multi-bit data across clock domains is provided, and fig. 1 is a flowchart of a method for processing multi-bit data across clock domains according to an embodiment of the present application, as shown in fig. 1, where the flowchart includes the following steps:
step S102, obtaining data output from a transmitting clock domain side to a receiving clock domain side, wherein the transmitting clock domain and the receiving clock domain are different clock domains;
step S104, detecting whether the data change;
step S106, under the condition that the data is changed, updating the data and outputting the updated data; and when the data is unchanged, the original output data is kept.
Through the steps S102 to S106, data output from the transmitting clock domain side to the receiving clock domain side is obtained, wherein the transmitting clock domain and the receiving clock domain are different clock domains, and further whether the data change is detected, and the data is updated and then output under the condition that the data change; under the condition that the data is not changed, the original output data is maintained; therefore, the method and the device realize the processing of the multi-bit data crossing the clock domain under the condition of relative independence of the sending clock domain and the receiving clock domain, solve the problems of high hardware cost and high transmission delay caused by the need of bidirectional interaction of the sending clock domain and the receiving clock domain in the processing mode of crossing the clock domain transmission in the related technology, and can use more application scenes and the whole implementation mode is efficient and concise.
It should be noted that, the steps of the methods of steps S102 to S106 are performed on the receiving clock domain side, that is, performed by the device or equipment on the receiving clock domain side, and do not involve the transmitting clock domain side. As in the alternative implementation of the present embodiment, for the manner of acquiring the data output from the transmitting clock domain side to the receiving clock domain side in step S102 of the present application, this may be achieved by:
step S102-11, receiving data output to a receiving clock domain side by a register of the transmitting clock domain side;
and step S102-12, synchronizing the data by an N-level data synchronizer at the receiving clock domain side, wherein the value of N is determined by the average occurrence fault interval time.
It can be seen that, after receiving the data output from the transmitting clock domain side, the data synchronizer at the receiving clock domain side performs the synchronization process, that is, the steps S102-11 and S102-12 are performed at the receiving clock domain side.
The number of stages N of the synchronizer is determined by the average time between failures (Mean Time Between Failure, MTBF) requirement.
In equation (1), S reserves a decision time for the data synchronizer to register. The resolution time (i.e., the time that the register randomly returns to a stable value of 0 or 1 after entering a metastable state because the setup or hold time is not satisfied. The relationship between the stages N and S of the data synchronizer is shown as follows.
S＝T·(N-1)
N is greater than or equal to 2 formula (2)
In formula (2), T represents the clock period of the receiving clock domain. For example, when n=2, then S equals 1 clock cycle of the receive clock; when n=3, then S equals 2 clock cycles of the receive clock. τ is a constant associated with the process. W is the sum of the register setup time and hold time, and is related to the process. FC is the frequency of the receive clock. FD is the frequency at which data is transmitted. In summary, the S value is determined according to the MTBF requirement, thereby determining the number of stages N of the data synchronizer.
In addition, in another alternative implementation manner of this embodiment, the manner of determining whether the detected data related to step S104 of the present application is changed may be: a change detector at the receiving clock domain side detects whether the data in the current period is changed compared with the data in the previous period, so as to determine whether the received data is changed. It can be seen that the detection is also performed by a change detector on the side of the receiving clock domain.
In another alternative embodiment of the present application, in the case that data changes, the data is output after being updated, including: under the condition that the data change, outputting an effective value by an edge detector at the receiving clock domain side, and triggering a data selector at the receiving clock domain side to output updated data; in the case that the data is unchanged, maintaining the original output data includes: in the case of data change, the edge detector at the receiving clock domain side outputs invalid value and triggers the data selector to keep the original output data. It can be seen that the output of data (including the updated output and the retention of the original output data) is performed by the receive clock domain side edge detector.
It should be noted that, the method steps of the present application further include: after detecting whether the data changes, the data output by the change detector is buffered through an M-stage buffer at the receiving clock domain side, wherein M is larger than or equal to N-1.
In order that the present application may be more clearly understood, reference will now be made to the following description of alternative embodiments of the present application;
the alternative embodiment provides a design method and a device for transmitting the multi-bit data across the clock domain in the digital integrated circuit so as to meet the requirement of transmitting the multi-bit data across the clock domain in the digital integrated circuit.
Fig. 2 is a schematic structural diagram of a multi-bit data cross-clock domain transmission device according to an embodiment of the present application, as shown in fig. 2: the transmit clock domain (clock domain 1) and the receive clock domain (clock domain 2) are different clock domains, with asynchronous relationships between clocks. Meanwhile, the transmitting clock domain and the receiving clock domain may be different power domains (power domain1 and power domain 2), or different voltage domains (voltage domain1 and voltage domain 2).
The sending data output from the sending clock domain register enters the receiving clock domain, is received by the multi-bit data cross-clock domain transmission device, is correctly processed and is provided for the functional logic circuit of the receiving clock domain.
The multi-bit data clock domain crossing device comprises the following 5 functional modules: a data synchronizer, a change detector, a buffer, an edge detector, and a data selector.
The overall workflow (i.e., signal processing flow) of the apparatus includes:
step S11, the received data are subjected to synchronous processing through a data synchronizer;
step S12, detecting whether the data has a change by using a change detector;
step S13, if the received data has a change, the change detector outputs a change indication signal, and the change indication signal is buffered by a buffer to be stable in the multi-bit data;
step S14, the change indication signal is processed by the edge detector to indicate the data selector to update the output data;
in step S15, if the received data is unchanged, the data selector holds the original output.
It should be noted that the whole process is performed in the receiving clock domain, and the transmitting clock domain is not involved.
The description of each functional module in the device is as follows.
The data synchronizer is a two-stage or multi-stage register synchronizer that is co-located wide with the transmitted data to reduce the probability of metastability across the clock domain. The number of synchronizer stages N is determined by the average time between failures (Mean Time Between Failure, MTBF) requirement.
Wherein S reserves a decision time for the data synchronizer to register. The resolution time (i.e., the time that the register randomly returns to a stable value of 0 or 1 after entering a metastable state because the setup or hold time is not satisfied. The relationship between the number of stages N and S of the data synchronizer is:
S＝T·(N-1)
N≥2
where T represents the clock period of the receive clock domain. For example, when n=2, then S equals 1 clock cycle of the receive clock; when n=3, then S equals 2The clock period of the receive clock. Furthermore, τ is a constant associated with the process. W is the sum of the register setup time and hold time, and is related to the process. F (F) C Is the frequency of the receive clock. F (F) D Is the frequency at which data is transmitted.
Therefore, the number of stages N of the data synchronizer is determined by determining the S value according to the MTBF requirement. It should be noted that each transmit data needs to be changed after at least N clock cycles of the receive clock domain to ensure that the transmit data can be sampled correctly without loss.
The change detector is used for detecting whether the synchronized data changes or not; the change detector outputs a valid value if there is a change in the data of the current cycle compared to the data of the previous cycle. The change detector outputs an invalid value if the data of the current cycle is unchanged from the data of the previous cycle.
The buffer is used for carrying out register buffer processing on the output value of the change detector, and is used for waiting for the stability of multi-bit data, maintaining the correlation among bits in the multi-bit data and avoiding the error sampling of the intermediate state of the multi-bit data. The relation between the buffer level M of the buffer and the level N of the data synchronizer is as follows: m is greater than or equal to N-1
Optionally, the data transmission delay (latency) is: latency= (n+m) ·t
Where Latency represents the time interval between data input to output. When the number of stages M of the buffer is equal to the number of stages N-1 of the data synchronizer, the data can be correctly sampled on the premise of meeting the MTBF requirement, and the transmission delay is optimal.
The edge detector is used for detecting whether the output of the buffer changes; if the signal of the current cycle changes compared to the signal of the previous cycle, the edge detector output is a valid value and remains for one sampling clock cycle. The edge detector output is an invalid value if the signal of the current cycle is unchanged from the signal of the previous cycle.
The data selector is used for taking the output of the edge detector as a selection signal and performing alternative selection output on currently input multi-bit data and last valid multi-bit data. When the select signal output by the edge detector is an inactive value, the last valid multi-bit data remains output. When the selection signal is a valid value, the currently input multi-bit data is selected to be updated and output.
The selectable implementation mode aims at the application scene of multi-bit data crossing clock domains, unidirectional control data transmission is realized, the transmission delay is configurable, the efficiency is high, the ingenious performance is realized, the sending clock is not needed to participate in the processing of crossing the clock domains, and the independence of the sending clock domain and the receiving clock domain is improved.
Therefore, the alternative embodiment is not only suitable for the application scenario of multi-bit data cross clock domains in the general case, but also suitable for the application scenario that the sending clock domain and the receiving clock domain are relatively independent, for example, the sending clock domain and the receiving clock domain are in different power domains or different voltage domains. Based on this, no design circuit means in the transmit clock domain is required; on the other hand, other than data transmission, no other control signals cross clock domains (or power domains or voltage domains), so that high efficiency and simplicity are realized. In addition, the data synchronizer series and the buffer series are set according to the requirement of Mean Time Between Failures (MTBF), so that the configuration is flexible.
Fig. 3 is a schematic diagram of multi-bit data transmission across clock domains according to an embodiment of the present application, as shown in fig. 3, in which the embodiment samples data at a clock rising edge, and the 5 functional modules are a data synchronizer (20), a change detector (21), a buffer (22), a rising edge detector (23), and a data selector (24), respectively.
The data synchronizer (20) is a two-stage or multi-stage register synchronizer that is co-located wide with the transmitted data, for receiving and synchronizing data0 transmitted from the transmit clock domain to reduce the probability of metastability across the clock domain. Generally, a two-stage data synchronizer may meet the MTBF requirements. In this embodiment, the data synchronizer is composed of D flip-flops (DFFs), with the number of stages n=2, and the data bit width is 3 bits.
The function of the change detector (21) is to detect whether the synchronized data changes, and the output signal is processed by the change detector (21), the buffer (22) and the rising edge detector (23) and then used for controlling the data selector (24). If the data2 of the current cycle is changed in a bit or bits from the data3 of the previous cycle, the change detector (21) outputs signal1 as 1' b1. If the data2 of the current cycle is unchanged from the data3 of the previous cycle, the change detector (21) outputs signal1 as 1' b0. In this embodiment, the change detector (21) is composed of a D flip-flop and an exclusive or gate (XOR).
The buffer (22) is used for buffering the output signal1 of the change detector (21), and correctly selecting and sampling after the data2 is stable, so that the acquisition of intermediate state data is avoided. In the present embodiment, the buffer (22) is composed of D flip-flops, and the buffer level M is the same as the data synchronizer (20) level N, that is, m=2. signal2 is the first stage buffered output signal and signal3 is the second stage buffered output signal.
The function of the rising edge detector (23) is to detect whether a rising edge change has occurred in the output signal3 of the buffer (22). If the signal3 of the current cycle is changed from 1' b0 to 1' b1 compared to the signal4 of the previous cycle, the rising edge detector output signal5 is 1' b1 and remains for one sampling clock cycle for the data selector (24) to gate and update the output data. In addition, the edge detector output signal5 is 1' b0. In the present embodiment, the rising edge detector (23) is composed of a D flip-flop, an not gate, an AND gate (AND), AND the like.
The function of the data selector (24) is to make a one-out-of-the-choice output of the currently inputted multi-bit data2 and the last valid multi-bit data4. When the selection signal5 is 1' b0, the last valid data4 is held to be output. When the selection signal5 is 1' b1, the update output of the currently inputted data2 is selected. In this embodiment, the data selector (24) is composed of a D flip-flop and a one-out-of-two selector (MUX).
The input signal is the data transmitted by the transmitting clock domain and the clock of the receiving clock domain, the output signal is the data received by the receiving clock domain, and the whole transmission delay is n+m=4 clock cycles of the receiving clock.
Fig. 4 is a schematic diagram of signal waveforms at various key points according to an embodiment of the present application, and signal names of fig. 4 correspond to the respective signals shown in fig. 3. As shown in fig. 4, at a time point between the 2 nd and 3 rd times, the data0 transmitted by the transmission clock domain changes from 3'b000 to 3' b111. The transmit clock is not shown in fig. 3, as embodiments of the present application do not require attention to transmit clock information, and are relatively independent of the transmit clock domain. Data0 is sampled at each rising edge by the clock of the receiving clock domain. The data synchronizer performs two-stage synchronization on data 0. The first stage output data is data1, and the second stage output data is data2.
At time 3, each bit of data1 may be either 0 or 1 due to metastability, so data1 as a whole may be any intermediate state from 3'b000 to 3' b111. Only intermediate state 3' b101 is exemplified in fig. 4.
At time 4, data1 is sampled correctly 3' b111 with a high probability in the MTBF time interval. Meanwhile, the change detector detects a change between data2 and data3, and the output signal1 changes from 1'b0 to 1' b1.
Note that at this time, data2 is in the intermediate state (3' b 101), erroneous sampling output to data4 should be avoided. Therefore, signal1 is buffered in two stages in the buffer, and then instruction signal3 is outputted. Data update of data4 is controlled by signal3.
And 5. The 5 th moment is the signal buffering moment, and the data correlation of each bit is maintained when the data2 is recovered to a stable state.
At time 6, after the rising edge detector detects the rising edge of signal3, the output signal5 changes from 1'b0 to 1' b1, and remains for 1 clock cycle. Meanwhile, the signal5 strobe data selector, data4 is updated, outputs data2, i.e., outputs multi-bit data after crossing clock domains, with an overall transmission delay of 4 clock cycles of the receive clock.
According to the embodiment, the multi-bit data cross-clock domain control method and the multi-bit data cross-clock domain control device mainly aim at multi-bit data cross-clock domain application scenes, unidirectional control of data transmission is achieved, transmission delay is configurable, efficiency is high, ingenious, a sending clock is not needed to participate in cross-clock domain processing, and independence of the sending clock domain and a receiving clock domain is improved. The application is not only suitable for the application scene of multi-bit data crossing clock domains in the common condition, but also is more suitable for the application scene that the sending clock domain and the receiving clock domain are relatively independent, for example, the sending clock domain and the receiving clock domain are in different power domains or different voltage domains. Therefore, there is no need to design a circuit device in the transmit clock domain; besides data transmission, no other control signals cross clock domains (or power domains or voltage domains), so that high efficiency and simplicity are realized. Furthermore, the present application supports setting the number of data synchronizer stages and the number of buffer stages according to the Mean Time Between Failures (MTBF) requirement to make the configuration flexible.
Example 2
The embodiment also provides a multi-bit data clock domain crossing processing device, which is used for implementing the above embodiment and the preferred implementation, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
FIG. 5 is a block diagram of a multi-bit data cross-clock domain processing apparatus according to an embodiment of the application, as shown in FIG. 5, comprising: an obtaining module 52, configured to obtain data output from a transmitting clock domain side to a receiving clock domain side, where the transmitting clock domain and the receiving clock domain are different clock domains; the detection module 54 is coupled and linked with the acquisition module 52 and is used for detecting whether the data changes; the processing module 56 is coupled with the detection module 54 and is used for outputting the updated data when the change of the data is detected; and when detecting that the data is unchanged, maintaining the original output data.
Optionally, the acquiring module 52 in the present application further includes: a data synchronizer for receiving data output from the register on the side of the transmit clock domain to the side of the receive clock domain; and synchronizing the data, wherein the data synchronizer is an N-level synchronizer, and the value of N is determined by the average fault interval time.
Optionally, the detection module 54 in the present application may further include: and the change detector is used for detecting whether the data in the current period is changed compared with the data in the previous period so as to determine whether the received data is changed.
Optionally, the processing module 56 in the present application may further include: the edge detector is used for outputting an effective value under the condition that data change occurs, and triggering a data selector at the receiving clock domain side to output updated data; and outputting an invalid value under the condition that the data is changed, and triggering the data selector to keep the original output data.
Optionally, the apparatus in the present application may further include: and the buffer is used for buffering the data output by the change detector after detecting whether the data changes, wherein the buffer is an M-stage buffer, and M is more than or equal to N-1.
It should be noted that each of the above modules may be implemented by software or hardware, and for the latter, it may be implemented by, but not limited to: the modules are all located in the same processor; alternatively, the above modules may be located in different processors in any combination.
It will be appreciated by those skilled in the art that the modules or steps of the application described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may alternatively be implemented in program code executable by computing devices, so that they may be stored in a memory device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps within them may be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principle of the present application should be included in the protection scope of the present application.
Claims (8)
1. A method for processing multi-bit data across clock domains, comprising:
acquiring data output from a transmitting clock domain side to a receiving clock domain side, wherein the transmitting clock domain and the receiving clock domain are different clock domains;
detecting whether the data changes;
under the condition that the data changes, updating the data and outputting the updated data; under the condition that the data is not changed, the original output data is maintained;
the obtaining the data output from the transmitting clock domain side to the receiving clock domain side comprises the following steps: receiving data output to the receiving clock domain side by the transmitting clock domain side; the data is synchronously processed by a data synchronizer at the receiving clock domain side;
wherein said detecting whether said data has changed comprises: and detecting whether the data in the current period is changed compared with the data in the previous period by the change detector at the receiving clock domain side so as to determine whether the received data is changed.
2. The method according to claim 1, wherein the receiving the data output from the transmitting clock domain side to the receiving clock domain side; the data is synchronously processed by a data synchronizer at the receiving clock domain side, which comprises the following steps:
receiving data output to the receiving clock domain side by a register at the transmitting clock domain side;
and synchronizing the data through an N-level data synchronizer at the receiving clock domain side, wherein the value of N is determined by the average fault interval time.
3. The method according to claim 1, characterized in that it comprises:
and under the condition that the data is changed, updating the data and outputting the updated data, wherein the method comprises the following steps: under the condition that the data change, outputting an effective value by an edge detector at the receiving clock domain side, and triggering a data selector at the receiving clock domain side to output updated data;
in the case that the data is unchanged, maintaining the original output data, including: and under the condition that the data is unchanged, outputting an invalid value by an edge detector at the receiving clock domain side, and triggering the data selector to keep the original output data.
4. A method according to claim 3, wherein after detecting whether the data has changed, the method further comprises:
and buffering the data output by the change detector through an M-level buffer at the receiving clock domain side, wherein M is more than or equal to N-1.
5. A multi-bit data cross-clock domain processing apparatus, comprising:
the device comprises an acquisition module, a receiving module and a processing module, wherein the acquisition module is used for acquiring data output to a receiving clock domain side by a transmitting clock domain side, wherein the transmitting clock domain and the receiving clock domain are different clock domains;
the detection module is used for detecting whether the data change;
the processing module is used for updating and outputting the data under the condition that the data is detected to change; under the condition that the data is detected to be unchanged, original output data is maintained;
wherein, the acquisition module includes: receiving data output to the receiving clock domain side by the transmitting clock domain side; the data is synchronously processed by a data synchronizer at the receiving clock domain side;
wherein, the detection module includes: and the change detector is used for detecting whether the data in the current period is changed compared with the data in the previous period through the change detector at the receiving clock domain side so as to determine whether the received data is changed.
6. The apparatus of claim 5, wherein the acquisition module comprises:
a data synchronizer for receiving data output from a register on a transmitting clock domain side to the receiving clock domain side; and carrying out synchronous processing on the data, wherein the data synchronizer is an N-level synchronizer, and the value of N is determined by average fault interval time.
7. The apparatus of claim 5, wherein the processing module comprises:
the edge detector is used for outputting an effective value and triggering a data selector at the receiving clock domain side to output updated data under the condition that the data are changed; and outputting an invalid value under the condition that the data is unchanged, and triggering the data selector to keep the original output data.
8. The apparatus of claim 7, wherein the apparatus further comprises:
and the buffer is used for buffering the data output by the change detector after detecting whether the data is changed, wherein the buffer is an M-stage buffer, and M is more than or equal to N-1.
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| CN201910578841.3A CN112148655B (en) | 2019-06-28 | 2019-06-28 | Multi-bit data clock domain crossing processing method and device |
| JP2021558008A JP7360472B2 (en) | 2019-06-28 | 2020-04-30 | Multi-bit data cross-clock domain processing method and device |
| PCT/CN2020/088019 WO2020259080A1 (en) | 2019-06-28 | 2020-04-30 | Multi-digit data cross-clock domain processing method and apparatus |
| KR1020217035272A KR20210141739A (en) | 2019-06-28 | 2020-04-30 | Method and apparatus for processing multi-digit data in cross clock domain |
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| CN105808476A (en) * | 2016-04-12 | 2016-07-27 | 珠海格力电器股份有限公司 | Cross-clock-domain data transmission method and device |
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| US6900665B2 (en) * | 2003-06-10 | 2005-05-31 | James Ma | Transfer of digital data across asynchronous clock domains |
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| US8363766B2 (en) * | 2008-06-06 | 2013-01-29 | Freescale Semiconductor, Inc. | Device and method of synchronizing signals |
| US20120033772A1 (en) * | 2010-08-08 | 2012-02-09 | Freescale Semiconductor, Inc | Synchroniser circuit and method |
| CN103576738A (en) * | 2012-08-01 | 2014-02-12 | 中兴通讯股份有限公司 | Method and device for clock domain crossing processing of asynchronous signals |
| US9722767B2 (en) * | 2015-06-25 | 2017-08-01 | Microsoft Technology Licensing, Llc | Clock domain bridge static timing analysis |
| CN107577623A (en) * | 2017-07-19 | 2018-01-12 | 成都华微电子科技有限公司 | Cross clock domain asynchronous fifo and data processing method |
| CN109408427B (en) * | 2017-08-18 | 2021-01-22 | 龙芯中科技术股份有限公司 | Cross-clock domain data processing method and system |
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| CN102929808A (en) * | 2012-11-02 | 2013-02-13 | 长沙景嘉微电子股份有限公司 | Clock domain crossing data transmission circuit with high reliability |
| CN105610532A (en) * | 2014-11-11 | 2016-05-25 | 中兴通讯股份有限公司 | Signal transmission processing method, signal transmission processing device and signal transmission processing equipment |
| CN106897238A (en) * | 2015-12-18 | 2017-06-27 | 浙江大华技术股份有限公司 | A kind of data processing equipment and method |
| CN105808476A (en) * | 2016-04-12 | 2016-07-27 | 珠海格力电器股份有限公司 | Cross-clock-domain data transmission method and device |
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| KR20210141739A (en) | 2021-11-23 |
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