CN112953475B

CN112953475B - Multi-bit data clock domain crossing synchronization circuit

Info

Publication number: CN112953475B
Application number: CN202110154156.5A
Authority: CN
Inventors: 王佳琪; 张涛
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2021-02-04
Filing date: 2021-02-04
Publication date: 2022-08-02
Anticipated expiration: 2041-02-04
Also published as: CN112953475A

Abstract

The invention discloses a multi-bit data cross-clock domain synchronization circuit, which belongs to the field of integrated circuits and comprises a data sending unit, an upstream clock, an encoding unit, a delay unit, a decoding unit, a delay control unit, a downstream clock and a data receiving unit; the data sending unit, the coding unit, the delay unit and the decoding unit are connected in sequence; the decoding unit is respectively connected with the delay control unit and the data receiving unit; the upstream clock is connected with the data sending unit and provides a clock for the data sending unit; the downstream clock is respectively connected with the delay control unit and the data receiving unit and provides clocks for the delay control unit and the data receiving unit. The invention can realize the synchronization of multi-bit data from a slow clock domain to a fast clock domain, has the characteristic of flexible adjustment, improves the circuit portability, can be applied to the directions of data delay adjustment, data synchronization and the like, and has great engineering significance.

Description

Multi-bit data clock domain crossing synchronization circuit

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a multi-bit data clock domain crossing synchronization circuit.

Background

Aiming at the problem of multi-bit data cross-clock domain synchronization, an indication signal mode is generally adopted, a downstream clock domain synchronizes the indication signal for two beats, and then data is received according to the synchronized indication signal, so that the problems of low synchronization efficiency, incapability of eradicating a metastable state and the like exist. For the problem of data delay adjustment, a method of manually inserting a gate circuit is generally adopted, the delay time is fixed, flexible adjustment of delay cannot be realized, and in the application with a feedback signal, the method of manually inserting the gate circuit cannot realize automatic adjustment.

Disclosure of Invention

The invention aims to provide a multi-bit data cross clock domain synchronization circuit to solve the problem of the requirement of multi-bit data cross clock domain synchronization.

In order to solve the above technical problem, the present invention provides a multi-bit data clock domain crossing synchronization circuit, which includes a data sending unit, an upstream clock, an encoding unit, a delay unit, a decoding unit, a delay control unit, a downstream clock and a data receiving unit;

the data sending unit, the coding unit, the delay unit and the decoding unit are connected in sequence; the decoding unit is respectively connected with the delay control unit and the data receiving unit;

the upstream clock is connected with the data sending unit and provides a clock for the data sending unit;

the downstream clock is respectively connected with the delay control unit and the data receiving unit and provides clocks for the delay control unit and the data receiving unit.

Optionally, the delay unit is composed of a plurality of stages of delay circuits, each stage of delay circuit includes a first inverter, a second inverter and a data selector;

the control end of a data selector in each stage of delay circuit is connected with the delay control unit, and the delay control unit controls the data selector to realize delay adjustment of the delay unit.

Optionally, the encoding unit uses hamming code encoding to generate an error flag bit of any bit, and outputs the error flag bit to the delay control unit.

Optionally, the decoding unit decodes the data to obtain actual data and an error flag bit, and outputs the error flag bit to the delay control unit.

Optionally, the delay control unit includes an internal counter, the number of stages of the internal counter is the same as the number of stages of the delay circuit in the delay unit, and the internal counter uses the error flag as an enable condition.

Optionally, the delay control unit starts counting and converts the count value into an enable signal of a control end of the data selector of a certain bit in the delay unit, where the count value is incremented from 0, with the error flag bit as an enable condition of a counter corresponding to the certain bit.

The multi-bit data clock domain crossing synchronization circuit provided by the invention is realized by a Hamming code and a delay circuit of combinational logic, and the delay of each path of data is adjusted in a targeted manner, so that the metastable state is eliminated fundamentally; the device comprises an encoding unit, a decoding unit, a delay unit and a delay control unit, wherein the encoding unit uses a Hamming code and adds check code bits in data; the decoding unit may return a certain bit error flag; the delay control unit uses combinational logic to adjust delay according to the error flag until the error flag bit is normal; the delay unit is internally subdivided into a plurality of groups of multi-stage delay circuits, each bit of data corresponds to one group of delay circuits, and each stage of delay circuits is composed of two inverters and a data selector. The invention can realize the synchronization of multi-bit data from a slow clock domain to a fast clock domain, has the characteristic of flexible adjustment, improves the circuit portability, can be applied to the directions of data delay adjustment, data synchronization and the like, and has greater engineering significance.

Drawings

Fig. 1 is a block diagram of a multi-bit data clock domain crossing synchronization circuit provided by the present invention.

Detailed Description

The multi-bit data cross clock domain synchronization circuit proposed by the present invention is further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

Fig. 1 is a block diagram of a multi-bit data clock domain crossing synchronization circuit provided by the present invention, which includes a data sending unit 1, an upstream clock 2, an encoding unit 3, a delay unit 4, a decoding unit 8, a delay control unit 9, a downstream clock 10, and a data receiving unit 11.

The data sending unit 1, the encoding unit 3, the delay unit 4 and the decoding unit 8 are connected in sequence; the decoding unit 8 is connected with the delay control unit 9 and the data receiving unit 11 respectively;

the upstream clock 2 is connected with the data sending unit 1 and provides a clock for the data sending unit 1;

the downstream clock 10 is connected to the delay control unit 9 and the data receiving unit 11, respectively, and provides clocks for the delay control unit 9 and the data receiving unit 11.

With continued reference to fig. 1, the delay unit 4 is composed of a plurality of stages of delay circuits, each stage of delay circuit includes a first inverter 5, a second inverter 6 and a data selector 7; the control end of the data selector 7 in each stage of delay circuit is connected with the delay control unit 9, and the delay control unit 9 controls the data selector 7 to realize delay adjustment of the delay unit 4.

The encoding unit 3 generates an error flag of any bit by encoding using a hamming code, and outputs the error flag to the delay control unit 9. The decoding unit 8 decodes the data to obtain actual data and an error flag bit, and outputs the error flag bit to the delay control unit 9. The delay control unit 9 includes an internal counter having the same number of stages as the number of stages of the internal delay circuit of the delay unit 4, and the internal counter uses the error flag as an enable condition. The delay control unit 9 starts counting by using the error flag bit as an enable condition of a counter corresponding to a certain bit, converts the count value into an enable signal of a control end of the data selector 7 of a certain bit in the delay unit 4, and increases the count value from 0.

The working process is as follows:

firstly, a data sending unit 1 sends data at the rising edge of an upstream clock 2;

the coding unit 3 is a combinational logic, adds check bits according to Hamming code data and outputs the check bits to the delay unit 4;

the initial delay of the delay unit 4 is 0 level, and the data is directly output without delay;

decoding unit 8 decodes data to obtain error flag bit of a certain bit;

delay control unit 9 starts a certain counter according to the error flag bit, and the count value controls data selector 7 in delay unit 4;

the delay unit 4 selects the corresponding data selector 7 to delay data according to the count value of the delay control unit 9;

seventhly, repeating the step four until the error mark position is 0;

transmitting the data again by the data transmitting unit 1 at the next rising edge of the upstream clock 2;

ninthly, because the count value of the delay control unit 9 is not changed, the data sequentially passes through the encoding unit 3, the delay unit 4 and the decoding unit 8, and an error flag bit cannot be generated, and the encoding unit 3, the delay unit 4 and the decoding unit 8 cannot be adjusted;

the data is synchronized across clocks by the r.

The multi-bit data clock domain crossing synchronization circuit provided by the invention can complete multi-bit data clock domain crossing synchronization under the prior art; the delay of each path of data is adjusted in a targeted manner, the metastable state is eliminated fundamentally, the characteristic of flexible adjustment is achieved, and the circuit portability is improved.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. A multi-bit data clock domain crossing synchronization circuit is characterized by comprising a data sending unit (1), an upstream clock (2), an encoding unit (3), a delay unit (4), a decoding unit (8), a delay control unit (9), a downstream clock (10) and a data receiving unit (11);

the data sending unit (1), the coding unit (3), the delay unit (4) and the decoding unit (8) are connected in sequence; the decoding unit (8) is respectively connected with the delay control unit (9) and the data receiving unit (11);

the upstream clock (2) is connected with the data sending unit (1) and provides a clock for the data sending unit;

the downstream clock (10) is respectively connected with the delay control unit (9) and the data receiving unit (11) and provides clocks for the delay control unit (9) and the data receiving unit (11);

the delay unit (4) is composed of a plurality of stages of delay circuits, each stage of delay circuit comprises a first inverter (5), a second inverter (6) and a data selector (7); the control end of a data selector (7) in each stage of delay circuit is connected with the delay control unit (9), and the delay control unit (9) controls the data selector (7) to realize delay adjustment of the delay unit (4);

the encoding unit (3) uses Hamming code encoding to generate an error flag bit of any bit and outputs the error flag bit to the delay control unit (9).

2. The multi-bit data clock domain crossing synchronization circuit according to claim 1, wherein said decoding unit (8) decodes data to obtain actual data and an error flag bit, and outputs the error flag bit to said delay control unit (9).

3. The multi-bit data clock domain crossing synchronization circuit according to claim 2, wherein said delay control unit (9) comprises an internal counter having the same number of stages as the number of stages of the delay circuit internal to said delay unit (4), the internal counter being enabled with an error flag bit.

4. The multi-bit data clock domain crossing synchronization circuit according to claim 3, wherein the delay control unit (9) starts counting with the error flag bit as an enable condition for a counter corresponding to a bit and converts the count value into an enable signal for the control terminal of the data selector (7) for a bit in the delay unit (4), the count value being incremented from 0.