CN102143023B - Error code testing system based on FPGA (Field Programmable Gate Array) - Google Patents
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Abstract
The invention discloses an error code testing system based on an FPGA (Field Programmable Gate Array), which comprises a code element sequence synchronization module, an error code counter, a user code generation module and a PRBS (Pseudo Random Binary Sequence) module, wherein the code element sequence synchronization module is used for realizing the synchronization of a receiving code element and a local code element; the error code counter is used for counting number of code element errors in same time period; the user code generation module is used for generating a custom code; and the PRBS module is used for generating a PRBS code element. The error code testing system disclosed by the invention improves the principles of the traditional circuit, apparatus and communication protocol design by applying integration and flexibility of the FPGA, and can be applied to a production line and research and development to be used as a main control chip of an error code testing apparatus.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of error code testing system based on FPGA.
Background technology
In today of high speed information development, communication has become indispensable part in people's life undoubtedly.Especially digital communication, it is strong with antijamming capability, high-quality long-distance transmissions, and be convenient to be connected with computer, being easy to the advantage such as encryption has become the important means of present information transmission, and along with the extensive use of large scale integrated circuit, the development of advancing by leaps and bounds that made digital communication obtain.It is particularly important that the reliability of its transmission seems.Meanwhile, due to the development of integrated circuit, FPGA has also obtained develop rapidly, and range of application is more and more wider, but, because holistic cost is still higher, FPGA is mainly used in space flight and aviation, instrument manufacturing, the high-end fields such as communication.Due to progress and the raising of integrated circuit technology, 60nm, 40nm, even 28nm technique ripe being used in the FPGA manufacture.And to be transferred to receiving terminal to information source from transmitting terminal, in long-distance transmissions, may be an other end that is positioned at the earth, or satellite-signal, realize transmitting, the error rate in transmission weigh the important indicator of digital communication system.The so-called error rate refers to the probability that error code occurs in transmitting procedure, and the computational methods in Practical Project are to get one period sufficiently long transmission time, ask during this period of time in the ratio of number and total code element number of reception of error code in receiving symbol.The size of the error rate is determined by system performance and the channel quality of path, quantitatively understand the running quality of system, just need to be measured its error rate.In prior art, common sequence synchronous method has sliding correlation method, Serial relation method and SAW device trapping etc.But all there is the implementation structure complexity in these methods, the shortcoming such as lock in time is long.
Summary of the invention
Purpose of the present invention just is to provide a kind of error-code testing method based on FPGA, and the method can be flexibly, fast the error code in digital communication process is tested.
To achieve these goals, the technical solution used in the present invention is such: a kind of error code testing system based on FPGA, and described system comprises sequence of symhols synchronization module, error code counter, user code generation module and PRBS module;
Wherein the sequence of symhols synchronization module is for realizing synchronizeing of receiving symbol and local code element; Wherein error code counter is for adding up the symbol error number of certain time period; The user code generation module is for generation of for custom code; The PRBS module produces the PRBS code element.
According to embodiments of the invention, this system also comprises the error code insert module, for transmitting terminal, to data, inserts error code.
According to embodiments of the invention, passing through between FPGA and host computer communicated by letter by MCU.
According to embodiments of the invention, described PRBS module comprises two PRBS code generators, and one of them is for generation of the code stream of emission, and another one PRBS code generator is for generation of to obtain code stream PRBS code source sequence relatively with receiving.
According to embodiments of the invention, described PRBS code generator adopts 64 tunnels parallel, and phase place differs from the parallel PRBS sequence of 1 phase place by turn, generates the PRBS code on 64 fixing tunnels of phase place.
According to embodiments of the invention, described PRBS code generator produces the PRBS sequence and meets PRBS generation equation.
According to embodiments of the invention, what described PRBS code generator produced is the m sequence, and m from 3 to 31.
According to embodiments of the invention, described user code generation module is for generation of user's definitions, and User Defined data maximum length is 512bit, and minimum length is 4bit.
According to embodiments of the invention, after receiving test data, by the sequence of symhols synchronization module, realize synchronizeing of receiving symbol and local code element.
According to embodiments of the invention, the synchronous PRBS sequence of described sequence of symhols synchronization module process comprises:
The synchronization acquistion state machine sends the PRBS sequence and loads pulse, and the PRBS sequence of symhols received is loaded in local PRBS code generator as seed;
Local PRBS code parallel circuit will produce and receive to obtain the code element of PRBS code mirror image, mirror image code element and receiving symbol can differ several clocks on phase place, the receiving end code element is adopted to delay circuit, make on the PRBS of reception and local new generations PRBS code element clock synchronously.
According to embodiments of the invention, the synchronous PRBS sequence of described sequence of symhols synchronization module process realizes by time delay: the PRBS code of the reception after time delay and the local PRBS code produced are delivered in comparator and are got XOR, then send and start to add up the pulse of error code number, after the time delay certain hour, and after waiting for several receive clocks, now reach and receive total code element number and equal clock number and be multiplied by parallel way, read the error code number of statistics simultaneously, if the error rate is greater than error code or the door value of the maximum of setting, again send synchronous loading pulse, until the error rate is less than given door value.
According to embodiments of the invention, described error code counter comprises: a road signal is to clock count, one road signal is to the total counting number of error code under clock of error code, and error code calculates and is divided into that total code element is calculated and number of bit errors calculating, and the error rate equals cumulative number of bit errors/(clock * walk abreast way).
As of the present invention preferred, described error code insert module the last position in 64 channel parallel datas of transmitting terminal is fixed and 1 XOR.
As of the present invention preferred, the connected mode between MCU and FPGA is by virtual parallel port EPP, RS serial ports or IIC pattern.
As of the present invention preferred, described PRBS code clock is at 155MHz～185MHz.
According to embodiments of the invention, be appreciated that, described error code testing system comprises loop fuction: after starting the PRBS decoding circuit, can produce 64 parallel rood PRBS codes simultaneously, through transtation mission circuit, convert the SerDes parallel-serial conversion chip that 16 parallel data stream sends to outside high speed to, convert road data-signal at a high speed to through SerDes and send continuously; Send to outside data, through external circuit or light path, convert signal of telecommunication loopback at a high speed to, loopback signal is as test data.
Compared with prior art, the invention has the advantages that:
1, the present invention uses clock that FPGA inside can move, multiplier unit, integrated serial transceiver, and configurable I/O mouth flexibly, compatibility is the circuit interface standard widely, the IO pin that quantity is large, inner abundant logical block, jumbo memory cell, make the serial communication that can carry out complicated logical operation and high speed in FPGA inside with aspect outside be connected, the work that needed in the past the polylith integrated circuit to complete, can concentrate on a FPGA inside and complete.Improved like this flexibility of design, the modification of Project design can not need the heavy design circuit plate that first goes, wiring, expensive cycle.
2, error-code testing method of the present invention uses the integrated and flexibility of FPGA, has promoted the theory to traditional circuit, instrument, communication protocol design, can be used in production line and research and development the main control chip as the instrument of error code testing.
The accompanying drawing explanation
Fig. 1 is FPGA function money figure of the present invention;
Fig. 2 is PRBS sequence occurring principle figure of the present invention;
Fig. 3 is that user defined code of the present invention produces circuit diagram;
Fig. 4 is PRBS sequence synchronization acquistion conceptual scheme of the present invention;
Fig. 5 is PRBS sequence synchronous regime transition diagram of the present invention;
Fig. 6 is middle Bit Error Code Statistics circuit of the present invention;
The statistical circuit that Fig. 7 is error code 0 of the present invention and error code 1.
Embodiment
Below in conjunction with accompanying drawing, with concrete enforcement, the invention will be further described;
FPGA error code testing functional block diagram shown in Figure 1.Comprise SFI-41 receiving interface, sequence of symhols synchronization module, error code counter, user code generation module, PRBS module, error code insert module and SPF-41 emission interface.
Wherein the sequence of symhols synchronization module is for realizing synchronizeing of receiving symbol and local code element; Wherein error code counter is for adding up the symbol error number of certain time period; The user code generation module is for generation of for custom code; The PRBS module produces the PRBS code element; The error code insert module is inserted error code for transmitting terminal to data.
The error-code testing method of FPGA based on shown in Fig. 1, high-speed data was first gone here and there and is changed before entering FPGA, go here and there and change by outside high speed transceiving chip and complete, the interface of FPGA and High Speed ICs is SFP-41, FPGA, as the logical circuit kernel, at first produces parallel multichannel data, when data send, the parallel data that FPGA is produced, through parallel-serial conversion, is connected with exterior I C from the SFP-4.1 interface.The data that send to outside are binary data at a high speed, i.e. " 0 ", the data flow that " 1 " forms, and this binary data mode that information is stored in computer just, the effect of communication will complete exactly the exchange of information and share, so will complete sending and receiving to this binary data, the function of the data link layer in this part data communication network.And tester of the present invention does not directly send actual information, adopt general standard, send the M sequence, according to statistics and calculating, in the sending and receiving in the M sequence, 0 and 1 quantity equates; Perhaps indivedual roots send a string by 0 and 1 sequence of symhols formed of user's self-defining in the demand of test.Use the M sequence, or user's defined nucleotide sequence, as transmitting and receive data in error code testing, gone the assessment of error code testing.Send to the transceiving chip of outside high speed.In error code testing, multichannel data adopts PRBS code or user defined code, and described user is 512 bits from scheduling the code sequence length the longest; Under the control of clock and parallel circuit, by the PRBS generator, produce and the synchronous PRBS code of receiving terminal; Through synchronous judgement, realize symbol synchronization again; Then carry out Bit Error Code Statistics, and the calculated value of error code is passed on MCU.
FPGA error code testing functional block diagram shown in Figure 1 comprises that transmitting portion SFI-4.1 transmission interface, receiving unit SFP-4.1 receiving interface, error code insertion portion, PRBS code or user code produce circuit, error code counting circuit and symbol synchronisation circuit.The rear MCU that powers on completes the port number of initialization configured rate and string the conversion of external chip, then by the initialization of FPGA, completes the setting of speed and pattern.After starting the PRBS decoding circuit, under the beat of clock, can produce 64 parallel rood PRBS codes simultaneously, through the SFP-4.1 transtation mission circuit, convert the SerDes parallel-serial conversion chip that 16 parallel data stream sends to outside high speed to, the data-signal that converts a road 10G through SerDes to sends continuously.Can insert the error code of 1 bit in sending data when sending, this part circuit inserts in circuit and completes at error code.Send to outside data, through external circuit or light path, convert signal of telecommunication loopback at a high speed to, loopback signal can be used as test data, it should be noted that, adopting the loopback signal mode is the method for error code testing, removes to assess the singal reporting code of communication receiving device and dispensing device.If only use the function of making a start, the signal of telecommunication of the 10G made a start, only as data source, can be used as the signal source of assessment communication transmitting device eye pattern.Test data is completed and is gone here and there and change by the SerDes chip of FPGA outside, and the high-speed data signal of 10G is converted to 16 tunnels, and FPGA receives the parallel data He Sui road clock on 16 tunnels by the SFP-4.1 interface.The data on 16 tunnels, through the deserializer of SFP-4.1 interface and FPGA inside, change into the parallel data on 64 tunnels, all receive the sequence of symhols of 64 at each receive clock.Synchronous circuit carries out the sequence of symhols of reception and local sequence of symhols synchronously.Receiving symbol sequence and local code metasequence after synchronous carry out the comparison of man-to-man bit, just can obtain the error code counting, and this part completes in error code counter.Finally by MCU, the error rate is passed to host computer again, and completed error code testing.The control of whole system is all to give an order and operate MCU by host computer, and MCU receives instruction by virtual and access FPGA and operation.
The circuit of directly realizing 10Ghz in FPGA inside is impossible at present.Can only take the method for Parallel Implementation, parallel figure place is more, and the frequency required is lower, but circuit is more complicated.Realize concurrently the m sequence on the inner Shi Yi of FPGA 64 tunnels at present, and require to be operated in 185MHz, this is a large difficult point of FPGA design and placement-and-routing.
The PRBS code is sent by the PRBS code generator, and described PRBS code generator has designed two, and one of them is for generation of the code stream of emission, and another one PRBS code generator is for generation of to obtain code stream PRBS code source sequence relatively with receiving.The principle of two PRBS code generators is the same, in this case, all adopts 64 tunnels parallel, the phase place difference of the code element that two PRBS code generators produce, and clock of the every hysteresis of code element is called symbol phases and lags behind one.Symbol phases depends on that the PRBS code generates the initial value of register, and this initial value, plant subcode, plants subcode and differs a phase place, makes the code element generated differ a phase place.
In the high speed error code testing, PRBS code generation type must adopt parallel circuit, generates the PRBS code on 64 fixing tunnels of phase place simultaneously.64 road PRBS generators produce one at each clock.Under a clock, the PRBS code parallel data that forms 64 tunnels, this 64 road PRBS code produces according to fixing continuous phase place successively, that is to say the order of this produced simultaneously PRBS code in 64 tunnel, it is consistent that the sequence of symhols produced under 64 clocks with a road PRBS code is wanted, otherwise be not just complete PRBS code.In this way, realized that parallel phase place differs from the parallel PRBS sequence of 1 phase place by turn.
The generation of PRBS meets and must equation occur PRBS, and it need to produce 155MHz, the m sequence parallel data on 64 tunnels, the m sequence from 3 to 31 that can do at present.In FPGA inside, first each m sequence is realized separately, each m sequence is unit independent of each other, a clock cycle all can produce 64 rood parallel datas simultaneously.The parallel data on 64 tunnels of each m sequence generation, finally select to need by a MUX m sequence sent.
Generate the PRBS code and must meet following equation, as following table 1 is that typical PRBS code produces equation:
| The M sequence | PRBS length | Multinomial |
| 3 | 7 | X3+X2+1 |
| 4 | 15 | X4+X3+1 |
| 5 | 31 | X5+X3+1 |
| 6 | 63 | X6+X5+1 |
| 7 | 127 | X7+X6+1 |
| 8 | 255 | X8+X6+X5+X4+1 |
| 9 | 511 | X9+X5+1 |
| 10 | 1,023 | X10+X7+1 |
| 11 | 2,047 | X11+X9+1 |
| 12 | 4,095 | X12+X6+X4+X+1 |
| 13 | 8,191 | X13+X4+X3+X+1 |
| 14 | 16,383 | X14+X5+X3+X+1 |
| 15 | 32,767 | X15+X14+1 |
| 16 | 65,535 | X16+X15+X13+X4+1 |
| 17 | 131,071 | X17+X14+1 |
| 18 | 262,143 | X18+X11+1 |
| 19 | 524,287 | X19+X6+X2+X+1 |
| 20 | 1,048,575 | X20+X3+1 |
| 21 | 2,097,151 | X21+X19+1 |
| 22 | 4,194,303 | X22+X21+1 |
| 23 | 8,388,607 | X23+X18+1 |
| 24 | 16,777,215 | X24+X23+X22+X17+1 |
| 25 | 33,554,431 | X25+X22+1 |
| 26 | 67,108,863 | X26+X6+X2+X+1 |
| 27 | 134,217,727 | X27+X5+X2+X+1 |
| 28 | 268,435,455 | X28+X25+1 |
| 29 | 536,870,911 | X29+X27+1 |
| 30 | 1,073,741,823 | X30+X6+X4+X+1 |
| 31 | 2,147,483,647 | X31+X28+1 |
In error code testing, can adopt the PRBS code according to demand, also can adopt user-defined pattern.The generation of user's definitions.The User Defined data are 512bit to the maximum, and minimum length is 4bit, its scheme as shown in Figure 3:
At first the user writes in the RAM of self-defining data to a 64x8, maximum and 512 bits, and low byte first sends, and in same byte, is that a high position first sends, and then writes user-defined transmission sequence length.
Next, be dumped in the RAM of a 512x64.The dump state machine repeats user data 64 times, and the length of each dump is user-defined length, and total length is that the User Defined sequence length is multiplied by 64 bits.Just all set send data in the RAM of this unloading.This has just completed 64 parallel-by-bits of user data.
Modulo-N counter is constantly read the data in 512x64, and these data are exactly custom data.
Below the principle of the naive model of a user-defined pattern production process: the RAM that the 512*64 position is set in the register of FPGA inside.At first to write user-defined data in these RAM by virtual parallel port, if it is 512 that the user defines length, if the width of virtual parallel port is 32 bit wides, such as sending data, be this sequence " 01,100,110 01,100,110 01100110 01100110... "), totally 512, and the storage of FPGA inside is 64 bit wides, virtual parallel port is 32 bit wides, need two clocks so often write a register, write 512 bits of whole sequence, just need 16 clocks.It is 8*64 that the length of 512 bits is changed into to the space taken.We will write the ram space of 512*64, also need this process of repetition 512/8 time, will be to 512/8 counting.After writing.Just data have been arranged in RAM.Then to go these data output.Each clock is got 64.So just circulated after 512 clocks one time.Control circuit produces the address signal of RAM, takes out successively.
After receiving test data, at first to synchronously realize synchronizeing of receiving symbol and local code element by sequence of symhols, the synchronous employing of the user code same footwork of sliding.
As shown in Figure 4,5, the tolerance provided by host computer in synchronous deterministic process limits, and by repeatedly comparing of tolerance and the error rate, realizes synchronization acquistion.The sequence of symhols of PRBS of take is synchronously example, the synchronization acquistion state machine sends the PRBS sequence and loads pulse, the PRBS sequence of symhols received is loaded in local PRBS code generator as seed, under the control of clock, local PRBS code parallel circuit will produce and receive to obtain the code element of PRBS code mirror image, mirror image code element and receiving symbol can differ several clocks on phase place, and the receiving end code element is adopted to delay circuit, make on the PRBS of reception and local new generations PRBS code element clock synchronously.Because be all the identical parallel circuit that identical PRBS code generation equation is realized, the continuous code stream produced under same clock frequently, as long as PRBS kind subcode is consistent, this two group codes stream produced can be directly used in error code relatively, has just realized the alignment of PRBS sequence of symhols.The PRBS code of the reception after time delay and the PRBS code of parallel output are delivered in comparator and are got XOR, then send and start to add up the pulse of error code number, after the time delay certain hour, read the error code number of statistics, if the error rate is greater than the error code of maximum of setting or door value, (value is provided by host computer, such as thresholding is 1E-2), again send synchronous loading pulse, until the error rate is less than given door value.After synchronization acquistion completes, put that synchronously to complete be 1, show that FPGA has completed the synchronous of code element, just can carry out follow-up error code testing.
Bit Error Code Statistics circuit as shown in Figure 6, the Bit Error Code Statistics circuit realizes in decision circuitry, when judgement, the Bit Error Code Statistics pulse is that the synchronization acquistion state machine sends, and by MCU, is sent after synchronous.
Error code counter as shown in Figure 6: a road signal is to clock count, and a road signal is to the total counting number of error code under clock of error code, and error code calculates and is divided into that total code element is calculated and number of bit errors calculating; The code element received is carried out to error rate calculation, and the present invention adopts parallel 64 tunnels, and 64 code elements of each clock reception, and the local code element that produces 64 code elements and receive of while is carried out XOR and done cumulative.The value of total code element equals parallel way and is multiplied by clock number, and the parallel way of carrying out here is 64.So the clock number that total code element equals counting is multiplied by 64.And, simultaneously to clock count, the error rate equals cumulative number of bit errors/(clock is multiplied by 64), has so just completed the calculating of the error rate.
In order to simulate the situation of actual track, obtain method by the insertion error code and realize in the time of test.The method of inserting error code is that the last position is fixed and 1 XOR in 64 channel parallel datas of transmitting terminal.Be equivalent to like this last negate, the data that send have just sent the error code of 1, i.e. the code element comparison to receiving terminal and another one PRBS generator should be able to have error code.Insertion that can be continuous, also can insert at interval.As long as set the interval of inserting, the error rate of insertion is fixed.
FPGA is by SFI41 interface and VSC8479 docking, realizes the transmission of 16 parallel data.At the inner deserializer (SerDes) that passes through the FPGA inside self of 1: 4 of FPGA, the data transaction 16 becomes the parallel data on 64 tunnels.
The current MCU bridge joint that passes through between FPGA and host computer.Connected mode between MCU and FPGA realizes by the virtual parallel port EPP pattern the most easily realized, the register definitions of parallel port is self-defining as required, definition synchronous control signal address in register, read bit error signal address etc., when MCU reads and writes corresponding address, the value of the corresponding register of FPGA changes.Perhaps in FPGA, spread out of value register to MCU, thereby realized the communication of virtual parallel port.Certainly, those skilled in the art can understand, and the connected mode between MCU and FPGA also realizes by RS serial ports, IIC isotype.
Claims (8)
1. the error code testing system based on FPGA, is characterized in that, described system comprises sequence of symhols synchronization module, error code counter, user code generation module, PRBS module, error code insert module and MCU;
Described MCU receives the host computer instruction access and operates FPGA, complete the port number of initialization configured rate and string the conversion of external chip after powering on, then complete the setting of speed and pattern by the initialization of FPGA, test is finally passed to host computer to the error rate;
Described PRBS module is for generation of the PRBS code element, after the PRBS modular circuit starts, under the beat of clock, produce the PRBS code on 64 parallel tunnels simultaneously, through the SFI-4.1 transtation mission circuit, the parallel data stream that converts 16 tunnels to sends to the SerDes parallel-serial conversion chip of outside high speed, and the data-signal that converts a road 10G through SerDes to sends continuously;
Described error code insert module, insert the error code of 1 bit to data for transmitting terminal;
Send to outside data, through external circuit or light path, convert signal of telecommunication loopback at a high speed to, loopback signal is as test data, test data is completed and is gone here and there and change by the SerDes chip of FPGA outside, the high-speed data signal of 10G is converted to 16 tunnels, and FPGA receives the parallel data He Sui road clock on 16 tunnels by the SFI-4.1 interface; The parallel data on 16 tunnels, through the deserializer of SFI-4.1 interface and FPGA inside, changes into the parallel data on 64 tunnels, all receives the sequence of symhols of 64 at each receive clock;
Described sequence of symhols synchronization module is for carrying out the sequence of symhols of reception and local sequence of symhols synchronously;
Described error code counter, for adding up the symbol error number of certain time period, carries out the comparison of man-to-man bit by receiving symbol sequence and local code metasequence after synchronous, obtains the error code counting;
Described user code generation module is for generation of user defined code.
2. error code testing system as claimed in claim 1, it is characterized in that, described PRBS module comprises two PRBS code generators, and one of them is for generation of the code stream of emission, and another one PRBS code generator is for generation of the PRBS sequence of symhols of the comparison of the sequence of symhols with receiving.
3. error code testing system as claimed in claim 2, is characterized in that, described PRBS code generator adopts 64 tunnels parallel, and phase place differs from the parallel PRBS sequence of 1 phase place by turn, generates the PRBS code on 64 fixing tunnels of phase place.
4. error code testing system as claimed in claim 3, is characterized in that, described PRBS code generator produces the PRBS sequence and meets PRBS generation equation.
5. error code testing system as claimed in claim 4, is characterized in that, what described PRBS code generator produced is the m sequence, and m from 3 to 31.
6. error code testing system as claimed in claim 1, is characterized in that, described user code generation module is for generation of user defined code, and the user defined code maximum length is 512bit, and minimum length is 4bit.
7. error code testing system as claimed in claim 1, is characterized in that, described error code insert module the last position in 64 channel parallel datas of transmitting terminal is fixed and 1 XOR.
8. error code testing system as described as one of claim 1 to 6, is characterized in that, the connected mode between MCU and FPGA is by virtual parallel port EPP, RS serial ports or IIC pattern.
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| CN117220832B (en) * | 2023-11-07 | 2024-03-15 | 苏州联讯仪器股份有限公司 | Error code insertion method, device, system and computer storage medium |
| CN117478107B (en) * | 2023-12-28 | 2024-02-27 | 芯光智网集成电路设计(无锡)有限公司 | Delay calibration method, transmitting end and source synchronous communication system |
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| CN102143023A (en) | 2011-08-03 |
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