CN109831251B - Method and device for obtaining bit error rate based on dynamic resource allocation algorithm - Google Patents
Method and device for obtaining bit error rate based on dynamic resource allocation algorithm Download PDFInfo
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Abstract
The invention relates to a method and a device for acquiring a bit error rate based on a dynamic resource allocation algorithm, wherein the method comprises the following steps: controlling a code stream generator transmitting end to transmit a test code stream at a preset rate, and counting the test code stream; receiving a code stream after the test of a tested device, and acquiring the number of error codes according to the test code stream; packing the error code quantity in a preset period to obtain a data packet; and acquiring the data packet to calculate the error rate. The bit error rate obtaining method and the device based on the dynamic resource allocation algorithm provided by the invention have the advantages that the unit test period is reduced, the times of obtaining the number of the error codes are increased in unit time to obtain larger number of the error codes, the actual test time is dynamically allocated according to the change of the system test condition, and the test result under the invalid or unstable test condition is eliminated, so that the bit error rate test result with larger order of magnitude and more stable and accurate is obtained.
Description
Technical Field
The invention relates to the technical field of optical fiber communication, in particular to a method and equipment for acquiring a bit error rate based on a dynamic resource allocation algorithm.
Background
The result of the error rate test calculation is a numerical value obtained by dividing the total number of the error codes acquired by the receiving end of the optical fiber transmission system within a period of time by the total number of the code sent by the sending end, for a test system with a certain code rate, the larger the number of the error codes acquired within a unit time is, the larger the error rate is, the limitation is imposed by the bit length of an error code number acquiring unit at the receiving end of the test system, and the theoretical maximum value of the number of the error codes acquired by reading each time is certain. Under the test condition of a mainstream code rate of 25.78125Gbps, the existing error rate calculation algorithm can only calculate the error rate of 1E-4 by matching with hardware, and cannot meet the requirement of a large error code rate of 1E-3, so that the test condition of the large error code rate cannot be met in the production test link of the optical module, and the test precision is greatly influenced.
Disclosure of Invention
In view of the above, it is necessary to provide a method and an apparatus for obtaining a bit error rate based on a dynamic resource allocation algorithm for addressing at least one of the above-mentioned problems.
A method for obtaining bit error rate based on dynamic resource allocation algorithm includes following steps:
controlling a code stream generator transmitting end to transmit a test code stream at a preset rate, and counting the test code stream;
receiving a code stream after the test of a tested device, and acquiring the number of error codes according to the test code stream;
packing the error code quantity in a preset period to obtain a data packet;
and acquiring the data packet to calculate the error rate.
In one embodiment, the step of obtaining the number of bit errors according to the test code stream further includes:
and acquiring synchronous state information corresponding to the tested code stream, wherein the time period in the synchronous state information adopts millisecond level.
Further, the step of obtaining the data packet by data packing the error code number at the predetermined period specifically includes:
and performing AND operation according to the synchronous state information, and performing addition operation on the error code quantity value in the test data to obtain real-time synchronous state information and accumulated error code quantity representing in a preset period.
In one embodiment, the step of obtaining the data packet to calculate the bit error rate specifically includes:
initializing test data, resetting synchronous state information and zeroing the error code number;
and extracting the synchronous state information in the data packet, detecting that the synchronous state information accords with a preset synchronous state, accumulating the number of error codes in the data packet and calculating the error code rate.
Further, when the synchronous state information is detected to be in an asynchronous state, the current accumulated error number is cleared, and the error test is judged to be in an out-of-step state.
In one embodiment, the step of obtaining the data packet to calculate the bit error rate further comprises: and refreshing the synchronous state information and the error rate by taking a preset unit time as a period.
The invention correspondingly provides a bit error rate obtaining device based on a dynamic resource allocation algorithm, which comprises:
the transmitting module is used for controlling the transmitting end of the code stream generator to transmit the test code stream at a preset rate and counting the test code stream;
the acquisition module is used for receiving the code stream after the test of the tested device and acquiring the error code quantity according to the test code stream;
the packing module is used for carrying out data packing on the error code quantity in a preset period to obtain a data packet;
and the calculation module is used for acquiring the data packet and calculating the error rate according to the data packet.
The invention also provides a bit error rate acquisition device based on the dynamic resource allocation algorithm, which comprises a processor and a memory for storing the executable instructions of the processor; wherein the processor is configured to perform the steps of:
controlling a code stream generator transmitting end to transmit a test code stream at a preset rate, and counting the test code stream;
receiving a code stream after the test of a tested device, and acquiring the number of error codes according to the test code stream;
packing the error code quantity in a preset period to obtain a data packet;
and acquiring the data packet to calculate the error rate.
The bit error rate obtaining method and the device based on the dynamic resource allocation algorithm provided by the invention have the advantages that the unit test period is reduced, the times of obtaining the number of the error codes are increased in unit time to obtain larger number of the error codes, the actual test time is dynamically allocated according to the change of the system test condition, and the test result under the invalid or unstable test condition is eliminated, so that the bit error rate test result with larger order of magnitude and more stable and accurate is obtained.
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Fig. 1 is a flowchart of a method for obtaining a bit error rate based on a dynamic resource allocation algorithm according to an embodiment of the present invention;
fig. 2 is a schematic block structure diagram of an error rate obtaining apparatus based on a dynamic resource allocation algorithm according to an embodiment of the present invention.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
An embodiment of the present invention provides a method for obtaining a bit error rate based on a dynamic resource allocation algorithm, including the following steps S100 to S400:
step S100: and controlling a transmitting end of the code stream generator to transmit the test code stream at a preset rate, and counting the test code stream. A software module in the system controls a code stream generator transmitting end to transmit a PRBS (pseudo random binary sequence) test code stream with a set rate (generally 25.78125Gbps), and counts the transmitted test code stream.
Step S200: and receiving the code stream after the test of the tested device, and acquiring the error code quantity according to the test code stream. The code stream of the tested device is received at the code stream receiving end, namely the tested code stream, and the tested code stream is compared with the test code stream of the transmitting end to obtain the error code therein, count the number of the error codes and store the error codes into a relevant register of the test equipment. In addition, the step of obtaining the error code quantity according to the test code stream further comprises the following steps: and acquiring synchronous state information corresponding to the tested code stream, wherein the time period in the synchronous state information is in millisecond level.
Step S300: and packing the error code quantity with a preset period to obtain a data packet. The periodic acquisition of test data from the test equipment includes testing the synchronization status and the number of bit errors at the receiving end, the acquisition period reaches the millisecond level, and the bit number of the bit error number register of the test equipment is 16 bits, namely the maximum number of bit errors which can be obtained by reading the register each time is 0xFFFF (65535). Under the normal test condition, the maximum number of the obtained codes in unit test time (1 second) is 65535000, and the error rate obtained by dividing the number of the test codes (25.78125G) sent in unit test time (1 second) at the sending end can reach 1E-3 level. Test data, such as the above-mentioned synchronization status and the number of bit errors, is obtained from the registers of the test equipment, and the data within a predetermined period, for example, 20 ms, is subjected to a packing process for subsequent processing. Specifically, step S300 further includes:
and performing AND operation according to the synchronous state information, and performing addition operation on the error code quantity value in the test data to obtain real-time synchronous state information and accumulated error code quantity representing in a preset period. And performing AND operation on the synchronous state value in the test data, and performing addition operation on the error code quantity value in the test data to obtain a real-time synchronous state and an accumulated error code quantity which can represent the error code performance in a preset period, such as 20 milliseconds.
Step S400: and acquiring the data packet to calculate the error rate. And acquiring a data packet, processing the data packet by combining with a monitoring signal of the test system, and calculating to obtain the error rate.
The step of obtaining data packets to calculate the bit error rate specifically includes:
step S410: initializing test data, resetting synchronization state information and zeroing error code number.
Step S420: and extracting the synchronous state information in the data packet, and accumulating the number of error codes in the data packet and calculating the error code rate when detecting that the synchronous state information accords with the preset synchronous state. In addition, when the synchronous state information is detected to be in an asynchronous state, the current accumulated error number is cleared, and the error test is judged to be in an out-of-step state. The process continues to repeat step S420 to process the next packet.
After obtaining the bit error rate, the method further comprises a result processing step, specifically: the synchronous state information and the bit error rate are refreshed with a predetermined unit time as a cycle.
In other words, the following steps can be obtained by integrating the above steps S400:
a loop processing process, in which each loop only processes one data packet, and each loop can be divided into the following steps:
step S410': when the test is started for the first time, test data needs to be initialized, and a synchronous state and a return-to-zero error number are reset;
step S420': detecting equipment monitoring signals, if the equipment monitoring signals are abnormal, removing the test data packet of the current round, and maintaining the current test data unchanged;
step S430': if the monitoring signal is normal, the data packet is processed, the synchronization state in the data packet is extracted, if the data packet is synchronized (link), the number of error codes in the data packet is accumulated and the error rate is calculated, and if the synchronization state is asynchronous (fail), the current accumulated number of error codes is eliminated. The monitoring signal is obtained by carrying out system monitoring on test reading jump caused by factors possibly appearing in a test system and influencing system stability, such as chip reset, power supply fluctuation and the like, an abnormal reading period is skipped or a reading jump data packet is removed according to the system state obtained by actual monitoring, the time counting is removed at the same time, only the real and stable reading data packet is reserved, and the test method for dynamically distributing the test time avoids the influence of the abnormality of test equipment on the test result and better fits the error code performance of a real tested channel.
Further comprising a result display step, step S440': and according to the result after the data packet processing, refreshing a software display interface in the whole second (for example, every 50 data packets when the preset period is 20 milliseconds), and displaying the error code test synchronization state and the error code rate result in real time.
The invention correspondingly provides a bit error rate obtaining device based on a dynamic resource allocation algorithm, as shown in fig. 2, comprising: an emission module 1000, an acquisition module 2000, a packaging module 3000, and a calculation module 4000. The transmitting module 1000 is configured to control the transmitting end of the code stream generator to transmit the test code stream at a predetermined rate, and count the test code stream. The obtaining module 2000 is configured to receive a code stream after the device under test is tested, and obtain the number of bit errors according to the test code stream. The packing module 3000 is used for packing the error code amount in a predetermined period to obtain a data packet. The calculating module 4000 is configured to obtain the data packet and calculate the bit error rate accordingly. The device may further include a display module (not shown in the figure) for refreshing the software display interface at the whole second (for example, every 50 data packets when the predetermined period is 20 ms) according to the result after the data packet processing, and displaying the error code test synchronization state and the error code rate result in real time.
The invention also provides a bit error rate acquisition device based on the dynamic resource allocation algorithm, which comprises a processor and a memory for storing the executable instructions of the processor; wherein the processor is configured to perform the steps S100 to S400 described above.
The bit error rate obtaining method and the device based on the dynamic resource allocation algorithm have the following characteristics that:
1. the times of reading the error code test state and the error code number in the unit test time (1 second) are increased from 500-millisecond reading to 1-millisecond reading, so that the maximum error code number theoretical value under the normal test condition which can be obtained in the unit test time (1 second) is increased to 500 times.
2. Because the single chip microcomputer is limited in the capacity of processing and finishing reading, displaying and other operations, the minimum test time period is set to be 20 milliseconds, and the addition operation and the error code number reading are required to be carried out on the test state value read every 20 times outside the single chip microcomputer, and the test state value is packed into a data packet, so that only 50 data packets need to be processed in unit test time (1 second).
3. The method comprises the steps of carrying out system monitoring on factors possibly occurring in a test system and influencing system stability, such as test reading jump caused by chip reset, power supply fluctuation and the like, skipping an abnormal reading period or removing a reading jump data packet according to the system state obtained by actual monitoring, removing the time counting, and only keeping the real and stable reading data packet, so that the number of data packets processed in unit test time (1 second) is variable according to the actual test condition.
The method has the advantages that the unit test period is shortened, the number of times of obtaining the error code number is increased in unit time to obtain larger error code number, actual test time is dynamically distributed according to the change of system test conditions, test results under invalid or unstable test conditions are eliminated, the obtained error code rate result is real and stable, the error code performance characteristics of the tested equipment can be accurately reflected, and the method is particularly suitable for occasions with requirements on stable test of large error code rates.
The apparatuses or modules illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. A typical implementation device is a computer, which may take the form of a personal computer, laptop computer, cellular telephone, camera phone, smart phone, personal digital assistant, media player, navigation device, email messaging device, game console, tablet computer, wearable device, or a combination of any of these devices.
One skilled in the art will recognize that one or more embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, one or more embodiments of the present description may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, one or more embodiments of the present description may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
One or more embodiments of the present description may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. One or more embodiments of the specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
The above description is only exemplary of the preferred embodiment of one or more embodiments of the present disclosure, and is not intended to limit the present disclosure, so that any modification, equivalent replacement, or improvement made within the spirit and principle of the present disclosure should be included in the scope of protection of the present disclosure.
Claims (6)
1. A bit error rate obtaining method based on a dynamic resource allocation algorithm is characterized by comprising the following steps:
controlling a code stream generator transmitting end to transmit a test code stream at a preset rate, and counting the test code stream;
receiving a code stream after the test of a tested device, and acquiring the number of error codes according to the test code stream;
packing the error code quantity in a preset period to obtain a data packet;
acquiring the data packet to calculate the error rate;
the step of obtaining the error code quantity according to the test code stream further comprises:
acquiring synchronous state information corresponding to the tested code stream, wherein the time period in the synchronous state information adopts millisecond level;
the step of obtaining the data packet by data packing the error code number in a predetermined period specifically includes: and performing AND operation according to the synchronous state information, and performing addition operation on the error code quantity value in the test data to obtain real-time synchronous state information and accumulated error code quantity representing in a preset period.
2. The method according to claim 1, wherein the step of obtaining the data packet to calculate the bit error rate specifically comprises:
initializing test data, resetting synchronous state information and zeroing the error code number;
and extracting the synchronous state information in the data packet, detecting that the synchronous state information is in a synchronous state, accumulating the number of error codes in the data packet and calculating the error code rate.
3. The method of claim 2, wherein the synchronization status information is detected to be in an out-of-synchronization status, the current accumulated error number is cleared, and the error test is determined to be in an out-of-synchronization status.
4. The method of claim 1, wherein the step of obtaining the data packet to calculate the bit error rate further comprises: and refreshing the synchronous state information and the error rate by taking a preset unit time as a period.
5. An error rate obtaining device based on a dynamic resource allocation algorithm is characterized by comprising:
the transmitting module is used for controlling the transmitting end of the code stream generator to transmit the test code stream at a preset rate and counting the test code stream;
the acquisition module is used for receiving the code stream after the test of the tested device and acquiring the error code quantity according to the test code stream;
the packing module is used for carrying out data packing on the error code quantity in a preset period to obtain a data packet;
the calculation module is used for acquiring the data packet and calculating the error rate according to the data packet;
the obtaining of the error code quantity according to the test code stream further comprises:
acquiring synchronous state information corresponding to the tested code stream, wherein the time period in the synchronous state information adopts millisecond level;
the data packing the error code quantity in a predetermined period to obtain the data packet specifically includes: and performing AND operation according to the synchronous state information, and performing addition operation on the error code quantity value in the test data to obtain real-time synchronous state information and accumulated error code quantity representing in a preset period.
6. The device for acquiring the bit error rate based on the dynamic resource allocation algorithm is characterized by comprising a processor and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the steps of:
controlling a code stream generator transmitting end to transmit a test code stream at a preset rate, and counting the test code stream;
receiving a code stream after the test of a tested device, and acquiring the number of error codes according to the test code stream;
packing the error code quantity in a preset period to obtain a data packet;
acquiring the data packet to calculate the error rate; the obtaining of the error code quantity according to the test code stream further comprises:
acquiring synchronous state information corresponding to the tested code stream, wherein the time period in the synchronous state information adopts millisecond level;
the data packing the error code quantity in a predetermined period to obtain the data packet specifically includes: and performing AND operation according to the synchronous state information, and performing addition operation on the error code quantity value in the test data to obtain real-time synchronous state information and accumulated error code quantity representing in a preset period.
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| CN112511266A (en) * | 2020-07-01 | 2021-03-16 | 中兴通讯股份有限公司 | Transmission method, detection method and device, acquisition method, network equipment and system |
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