CN102143023A - Error code testing system based on FPGA (Field Programmable Gate Array) - Google Patents
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Abstract
The invention discloses an error code testing system based on an FPGA (Field Programmable Gate Array), which comprises a code element sequence synchronization module, an error code counter, a user code generation module and a PRBS (Pseudo Random Binary Sequence) module, wherein the code element sequence synchronization module is used for realizing the synchronization of a receiving code element and a local code element; the error code counter is used for counting number of code element errors in same time period; the user code generation module is used for generating a custom code; and the PRBS module is used for generating a PRBS code element. The error code testing system disclosed by the invention improves the principles of the traditional circuit, apparatus and communication protocol design by applying integration and flexibility of the FPGA, and can be applied to a production line and research and development to be used as a main control chip of an error code testing apparatus.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of error code testing system based on FPGA.
Background technology
In today of high speed information development, communication has become indispensable part in people's life undoubtedly.Especially digital communication, it is strong with antijamming capability, high-quality long-distance transmissions, and be convenient to be connected with computer, advantage such as being easy to encrypt has become the important means of present information transmission, and, make digital communication obtain the development of advancing by leaps and bounds along with the extensive use of large scale integrated circuit.It is particularly important that the reliability of its transmission then seems.Meanwhile, because development of integrated circuits, FPGA has also obtained develop rapidly, and range of application is more and more wider, but since whole cost still than higher, FPGA is mainly used in space flight and aviation, instrument manufacturing, high-end fields such as communication.Since the progress and the raising of integrated circuit technology, 60nm, 40nm, even ripe being used in the FPGA manufacturing of 28nm technology.And to be transferred to receiving terminal to information source from transmitting terminal, in long-distance transmissions, may be an other end that is positioned at the earth, perhaps satellite-signal is realized reliable transmission, the error rate in the transmission weigh the important indicator of digital communication system.The so-called error rate is meant the probability that error code takes place in transmission course, the computational methods in the actual engineering are to get one period sufficiently long transmission time, asks the ratio of number with total code element number of reception of error code in the interior during this period of time receiving symbol.The size of the error rate will quantitatively be understood the running quality of system by the system performance and the channel quality decision of path, just need measure its error rate.Common sequence method for synchronous has sliding correlation method in the prior art, sequence correlation method and SAW device trapping etc.Shortcomings such as but all there is the implementation structure complexity in these methods, and lock in time is long.
Summary of the invention
Purpose of the present invention just is to provide a kind of error-code testing method based on FPGA, and this method can be flexibly, fast the error code in the digital communication process is tested.
To achieve these goals, the technical solution used in the present invention is such: a kind of error code testing system based on FPGA, and described system comprises sequence of symhols synchronization module, error code counter, user code generation module and PRBS module;
Wherein the sequence of symhols synchronization module is used to realize the synchronous of receiving symbol and local code element; Wherein error code counter is used to add up the symbol error number of certain time period; The user code generation module is used for generation and is used for custom code; The PRBS module produces the PRBS code element.
According to embodiments of the invention, this system also comprises the error code insert module, is used for transmitting terminal and inserts error code to data.
According to embodiments of the invention, passing through between FPGA and the host computer communicated by letter by MCU.
According to embodiments of the invention, described PRBS module comprises two PRBS code generators, and one of them is used to produce the code stream of emission, another one PRBS code generator be used to produce and receive code stream PRBS sign indicating number source sequence relatively.
According to embodiments of the invention, it is 64 the tunnel parallel that described PRBS code generator adopts, and phase place differs from the parallel PRBS sequence of 1 phase place by turn, generates 64 tunnel fixing PRBS sign indicating number of phase place.
According to embodiments of the invention, described PRBS code generator produces the PRBS sequence and meets PRBS generation equation.
According to embodiments of the invention, what described PRBS code generator produced is the m sequence, and m from 3 to 31.
According to embodiments of the invention, described user code generation module is used to produce the user definition sign indicating number, and User Defined data maximum length is 512bit, and minimum length is 4bit.
According to embodiments of the invention, after receiving test data, realize the synchronous of receiving symbol and local code element by the sequence of symhols synchronization module.
According to embodiments of the invention, the synchronous PRBS sequence of described sequence of symhols synchronization module process comprises:
The synchronization acquistion state machine sends the PRBS sequence and loads pulse, and the PRBS sequence of symhols that receives is loaded in the local PRBS code generator as seed;
Local PRBS sign indicating number parallel circuit will produce and receive the code element of PRBS sign indicating number mirror image, mirror image code element and receiving symbol can differ several clocks on phase place, receiving end code element employing delay circuit, synchronous on the new generation PRBS code element clock of the feasible PRBS that receives and this locality.
According to embodiments of the invention, the synchronous PRBS sequence of described sequence of symhols synchronization module process realizes by time-delay: the PRBS sign indicating number of the reception after the time-delay and the local PRBS sign indicating number that produces are delivered to and are got XOR in the comparator, send then and begin to add up the pulse of error code number, behind the time-delay certain hour, and wait for after several receive clocks, this moment and receive total code element number and equal clock number and be multiplied by parallel way, read the error code number of statistics simultaneously, if the error rate is greater than the error code or the door value of the maximum of setting, then send synchronous loading pulse again, till the error rate is less than given door value.
According to embodiments of the invention, described error code counter comprises: one road signal is to clock count, one road signal is to the total counting number of error code under clock of error code, and error code calculates and is divided into that total code element is calculated and number of bit errors calculating, the number of bit errors that the error rate equals to add up/(clock * walk abreast way).
As of the present invention preferred, described error code insert module is fixing and 1 XOR in the last position in 64 channel parallel datas of transmitting terminal.
As of the present invention preferred, the connected mode between MCU and the FPGA is by virtual parallel port EPP, RS serial ports or IIC pattern.
As of the present invention preferred, described PRBS sign indicating number clock is at 155MHz～185MHz.
Be appreciated that according to embodiments of the invention, described error code testing system comprises loop fuction: after starting the PRBS decoding circuit, can produce 64 parallel rood PRBS sign indicating numbers simultaneously, through transtation mission circuit, convert the SerDes and the conversion chip of going here and there that 16 parallel data stream sends to outside high speed to, convert one tunnel at a high speed data-signal to through SerDes and send continuously; Send to outside data, through external circuit or light path, convert signal of telecommunication loopback at a high speed to, loopback signal is as test data.
Compared with prior art, the invention has the advantages that:
1, the present invention uses clock that FPGA inside can move, multiplier unit, integrated serial transceiver, and configurable I/O mouth flexibly, compatibility is the circuit interface standard widely, the IO pin that quantity is big, inner abundant logical block, jumbo memory cell, make the serial communication that can carry out complicated logical operation and high speed in FPGA inside with aspect the outside be connected, the work that needed the polylith integrated circuit to finish in the past can both concentrate on a FPGA inside and finish.Improved the flexibility of design like this, the modification of Project design can not need the heavy design circuit plate that goes earlier, wiring, expensive cycle.
2, the integrated and flexibility of error-code testing method of the present invention utilization FPGA has promoted the theory to traditional circuit, instrument, communication protocol design, can be used in production line and the research and development main control chip as the instrument of error code testing.
Description of drawings
Fig. 1 is FPGA function money figure of the present invention;
Fig. 2 is PRBS sequence occurring principle figure of the present invention;
Fig. 3 is that user defined code of the present invention produces circuit diagram;
Fig. 4 is a PRBS sequence synchronization acquistion conceptual scheme of the present invention;
Fig. 5 is a PRBS sequence synchronous regime transition diagram of the present invention;
Fig. 6 is a middle Bit Error Code Statistics circuit of the present invention;
Fig. 7 is the statistical circuit of error code 0 of the present invention and error code 1.
Embodiment
The invention will be further described with concrete enforcement below in conjunction with accompanying drawing;
Referring to FPGA error code testing functional block diagram shown in Figure 1.Comprise SFI-41 receiving interface, sequence of symhols synchronization module, error code counter, user code generation module, PRBS module, error code insert module and SPF-41 emission interface.
Wherein the sequence of symhols synchronization module is used to realize the synchronous of receiving symbol and local code element; Wherein error code counter is used to add up the symbol error number of certain time period; The user code generation module is used for generation and is used for custom code; The PRBS module produces the PRBS code element; The error code insert module is used for transmitting terminal and inserts error code to data.
Error-code testing method based on FPGA shown in Figure 1, high-speed data was gone here and there earlier before entering FPGA and is changed, string and conversion are finished by the high speed transceiving chip of outside, the interface of FPGA and High Speed ICs is SFP-41, FPGA at first produces parallel multichannel data, when data send as the logical circuit kernel, parallel data process and string conversion FPGA produces are connected with exterior I C from the SFP-4.1 interface.The data that send to the outside are binary data at a high speed, i.e. " 0 ", the data flow that " 1 " is formed, and this binary data information mode of in computer, storing just, the effect of communication will be finished the exchange of information exactly and share, so will finish this binary data and send and reception the function of the data link layer in this part data communication network.And tester of the present invention does not directly send actual information, adopts general standard, sends the M sequence, according to statistics with calculate, the transmission in the M sequence and receive in 0 and 1 quantity equal; Perhaps indivedual roots send a string by 0 and 1 sequence of symhols of forming that the user defines voluntarily in the demand of test.Use the M sequence, perhaps the user definition sequence as transmitting and receive data in the error code testing, goes to finish the assessment of error code testing.Send to the transceiving chip of outside high speed.Multichannel data adopts PRBS sign indicating number or user defined code in error code testing, and described user is 512 bits from scheduling the sign indicating number sequence length the longest; Under the control of clock and parallel circuit, produce and the synchronous PRBS sign indicating number of receiving terminal by the PRBS generator; Through judging synchronously, realize symbol synchronization again; Carry out Bit Error Code Statistics then, and the calculated value of error code is passed on the MCU.
Comprise that referring to FPGA error code testing functional block diagram shown in Figure 1 sending part SFI-4.1 transmission interface, receiving unit SFP-4.1 receiving interface, error code insertion portion, PRBS sign indicating number or user code produces circuit, error code counting circuit and symbol synchronisation circuit.The back MCU that powers on finishes the port number of initialization and configured rate and the string and the conversion of external chip, finishes the setting of speed and sign indicating number type then by the initialization of FPGA.After starting the PRBS decoding circuit, under the beat of clock, can produce 64 parallel rood PRBS sign indicating numbers simultaneously, through the SFP-4.1 transtation mission circuit, convert the SerDes and the conversion chip of going here and there that 16 parallel data stream sends to outside high speed to, the data-signal that converts one road 10G through SerDes to sends continuously.Can insert the error code of 1 bit when sending in sending data, this part circuit inserts in the circuit at error code and finishes.Send to outside data,, convert signal of telecommunication loopback at a high speed to through external circuit or light path, loopback signal can be used as test data, need to prove that adopting the loopback signal mode is the method for error code testing, removes to assess the singal reporting code of communication receiving device and dispensing device.If only use the function of making a start, the signal of telecommunication of the 10G that makes a start can be used as the signal source of assessment communication transmitting device eye pattern only as data source.Test data is finished string and conversion by the SerDes chip of FPGA outside, and the high-speed data signal of 10G is converted to 16 the tunnel, and FPGA receives 16 tunnel parallel data by the SFP-4.1 interface and with the road clock.16 tunnel data change into 64 tunnel parallel data through the deserializer of SFP-4.1 interface and FPGA inside, all receive 64 sequence of symhols at each receive clock.Synchronous circuit carries out sequence of symhols and the local sequence of symhols that receives synchronously.Receiving symbol sequence and local code metasequence synchronously carry out the comparison of man-to-man bit, just can obtain the error code counting, and this part is finished in error code counter.By MCU the error rate is passed to host computer more at last, and finished error code testing.The control of whole system all is to give an order by host computer to operate MCU, and MCU receives instruction by virtual and visit FPGA and operation.
Circuit at the inner directly realization of FPGA 10Ghz is impossible at present.Can only take the method for Parallel Implementation, parallel figure place is many more, and then the frequency of Yao Qiuing is low more, but circuit is complicated more.Be to realize the m sequence concurrently with 64 the tunnel at present in FPGA inside, and require to be operated in 185MHz that this is a big difficult point of FPGA design and placement-and-routing.
The PRBS sign indicating number is sent by the PRBS code generator, and described PRBS code generator has designed two, and one of them is used to produce the code stream of emission, another one PRBS code generator be used to produce and receive code stream PRBS sign indicating number source sequence relatively.The principle of two PRBS code generators is the same, all adopt in this case 64 the tunnel parallel, the phase place difference of the code element that two PRBS code generators are produced, clock of the every hysteresis of code element is called symbol phases and lags behind one.Symbol phases depends on that the PRBS sign indicating number generates the initial value of register, and this initial value is promptly planted subcode, plants subcode and differs a phase place, makes the code element of generation differ a phase place.
In the high speed error code testing, PRBS sign indicating number generation type must adopt parallel circuit, generates 64 tunnel fixing PRBS sign indicating number of phase place simultaneously.64 road PRBS generators all produce one at each clock.Under a clock, form 64 tunnel PRBS sign indicating number parallel data, this 64 road PRBS sign indicating number produces according to fixing continuous phase place successively, that is to say the order of these 64 tunnel produced simultaneously PRBS sign indicating numbers, want consistent with the sequence of symhols that one road PRBS sign indicating number produces under 64 clocks, otherwise be not complete PRBS sign indicating number just.In this way, realized that parallel phase place differs from the parallel PRBS sequence of 1 phase place by turn.
The generation of PRBS meets and must equation take place PRBS, and it need produce 155MHz, 64 tunnel m sequence parallel data, the m sequence from 3 to 31 that can do at present.In FPGA inside, each m sequence is realized separately each m sequence all is unit independent of each other earlier, a clock cycle all can produce 64 rood parallel datas simultaneously.64 tunnel the parallel data that each m sequence produces need to select the m sequence that sends by a MUX at last.
Generating the PRBS sign indicating number and must meet following equation, is that typical PRBS sign indicating number produces equation as following table 1:
| The M sequence | PRBS length | Multinomial |
| ?3 | 7 | X3+X2+1 |
| ?4 | 15 | X4+X3+1 |
| ?5 | 31 | X5+X3+1 |
| ?6 | 63 | X6+X5+1 |
| ?7 | 127 | X7+X6+1 |
| ?8 | 255 | X8+X6+X5+X4+1 |
| ?9 | 511 | X9+X5+1 |
| ?10 | 1,023 | X10+X7+1 |
| ?11 | 2,047 | X11+X9+1 |
| ?12 | 4,095 | X12+X6+X4+X+1 |
| ?13 | 8,191 | X13+X4+X3+X+1 |
| ?14 | 16,383 | X14+X5+X3+X+1 |
| ?15 | 32,767 | X15+X14+1 |
| ?16 | 65,535 | X16+X15+X13+X4+1 |
| ?17 | 131,071 | X17+X14+1 |
| ?18 | 262,143 | X18+X11+1 |
| ?19 | 524,287 | X19+X6+X2+X+1 |
| ?20 | 1,048,575 | X20+X3+1 |
| 21 | 2,097,151 | X21+X19+1 |
| 22 | 4,194,303 | X22+X21+1 |
| 23 | 8,388,607 | X23+X18+1 |
| 24 | 16,777,215 | X24+X23+X22+X17+1 |
| 25 | 33,554,431 | X25+X22+1 |
| 26 | 67,108,863 | X26+X6+X2+X+1 |
| 27 | 134,217,727 | X27+X5+X2+X+1 |
| 28 | 268,435,455 | X28+X25+1 |
| 29 | 536,870,911 | X29+X27+1 |
| 30 | 1,073,741,823 | X30+X6+X4+X+1 |
| 31 | 2,147,483,647 | X31+X28+1 |
In error code testing, can adopt the PRBS sign indicating number according to demand, also can adopt user-defined sign indicating number type.The generation of user definition sign indicating number.The User Defined data are 512bit to the maximum, and minimum length is 4bit, its scheme as shown in Figure 3:
At first the user writes among the RAM of self-defining data to a 64x8, maximum and 512 bits, and low byte sends earlier, then is that high-order elder generation sends in the same byte, writes user-defined transmission sequence length then.
Next, be dumped among the RAM of a 512x64.The dump state machine repeats user data 64 times, and the length of each dump is user-defined length, and total length is multiplied by 64 bits for the User Defined sequence length.Just all set send data among the RAM of this unloading.This has just finished 64 parallel-by-bitizations of user data.
Modulo-N counter is then constantly read the data among the 512x64, and these data are exactly custom data.
Be the principle of the naive model of a user-defined sign indicating number type production process below: the RAM that the 512*64 position is set in the register of FPGA inside.At first to write user-defined data among these RAM by virtual parallel port, if user definition length is 512, if the width of virtual parallel port is 32 bit wides, such as sending data is this sequence " 01,100,110 01,100,110 01100110 01100110... "), totally 512, and the storage of FPGA inside is 64 bit wides, virtual parallel port is 32 bit wides, need two clocks so whenever write a register, write 512 bits of complete sequence, just need 16 clocks.It is 8*64 that the length of 512 bits is changed into occupation space.We will write the ram space of 512*64, also need this process of repetition 512/8 time, will be to 512/8 counting.After having write.Just data have been arranged among the RAM.To go these data output then.Each clock is got 64.So after 512 clocks, just circulated one time.Control circuit produces the address signal of RAM, takes out successively.
After receiving test data, at first will by sequence of symhols realize synchronously receiving symbol and local code element synchronously, the synchronous employing of the user code same footwork of sliding.
Shown in Fig. 4,5, the tolerance that is provided by host computer in synchronous deterministic process limits, and by repeatedly comparing of the tolerance and the error rate, realizes synchronization acquistion.Sequence of symhols with PRBS is example synchronously, the synchronization acquistion state machine sends the PRBS sequence and loads pulse, the PRBS sequence of symhols that receives is loaded in the local PRBS code generator as seed, under the control of clock, local PRBS sign indicating number parallel circuit will produce and receive the code element of PRBS sign indicating number mirror image, mirror image code element and receiving symbol can differ several clocks on phase place, receiving end code element employing delay circuit, synchronous on the new generation PRBS code element clock of the feasible PRBS that receives and this locality.Because all be the identical parallel circuit that identical PRBS sign indicating number generation equation is realized, the continuous code stream that under same clock frequently, produces, as long as PRBS kind subcode unanimity, then this of Chan Shenging two group code streams can be directly used in error code relatively, have just realized the alignment of PRBS sequence of symhols.The PRBS sign indicating number of the reception after the time-delay and the parallel PRBS sign indicating number that produces are delivered to and are got XOR in the comparator, send then and begin to add up the pulse of error code number, behind the time-delay certain hour, read the error code number of statistics, (value is provided by host computer if the error rate is greater than the error code of the maximum of setting or door value, such as thresholding is 1E-2), then send synchronous loading pulse again, till the error rate is less than given door value.After synchronization acquistion is finished, put that to finish synchronously be 1, show FPGA finished code element synchronously, just can carry out follow-up error code testing.
Bit Error Code Statistics circuit as shown in Figure 6, Bit Error Code Statistics circuit realize in decision circuitry, and when judging, the Bit Error Code Statistics pulse is that the synchronization acquistion state machine sends, and then sent by MCU after synchronously.
Error code counter as shown in Figure 6: one road signal is to clock count, and one road signal is to the total counting number of error code under clock of error code, and error code calculates and is divided into that total code element is calculated and number of bit errors calculating; The code element that receives is carried out error rate calculation, and it is parallel 64 the tunnel that the present invention adopts, and each clock receives 64 code elements, and the local simultaneously code element that produces 64 code elements and receive is carried out XOR and done and add up.The value of total code element equals parallel way and multiply by clock number, and the parallel way of Shi Hanging is 64 here.So the clock number that total code element equals to count multiply by 64.And simultaneously to clock count, the number of bit errors that the error rate equals to add up/(clock multiply by 64) so just finished the calculating of the error rate.
In order to simulate the situation of actual track, get method by the insertion error code and realize in the time of test.The method of inserting error code is fixing and 1 XOR in the last position in 64 channel parallel datas of transmitting terminal.Be equivalent to like this last negate, the data that send have just sent 1 error code, i.e. code element comparison to receiving terminal and another one PRBS generator should be able to have error code.Insertion that can be continuous also can be inserted at interval.As long as set the interval of inserting, the error rate of insertion is fixed.
FPGA is by SFI41 interface and VSC8479 butt joint, the transmission of the parallel data of realization 16.At the inner deserializer (SerDes) that passes through 1: 4 FPGA inside self of FPGA, the data transaction 16 becomes 64 tunnel parallel data.
The current MCU bridge joint that passes through between FPGA and the host computer.Connected mode between MCU and the FPGA realizes by the virtual parallel port EPP pattern of the easiest realization, the register definitions of parallel port is definition voluntarily as required, definition synchronous control signal address in the register, read bit error signal address etc., when MCU read and write corresponding address, the value of FPGA relevant register changed.Perhaps in FPGA, spread out of value the register to MCU, thereby realized the communication of virtual parallel port.Certainly, those skilled in the art can both understand, and the connected mode between MCU and the FPGA also realizes by RS serial ports, IIC isotype.
Claims (16)
1. the error code testing system based on FPGA is characterized in that, described system comprises sequence of symhols synchronization module, error code counter, user code generation module and PRBS module;
Wherein the sequence of symhols synchronization module is used to realize the synchronous of receiving symbol and local code element; Wherein error code counter is used to add up the symbol error number of certain time period; The user code generation module is used for generation and is used for custom code; The PRBS module produces the PRBS code element.
2. error code testing as claimed in claim 1 system is characterized in that this system also comprises the error code insert module, is used for transmitting terminal and inserts error code to data.
3. error code testing as claimed in claim 2 system is characterized in that, current between FPGA and the host computer communicated by letter by MCU.
4. as the described error code testing of one of claim 1 to 3 system, it is characterized in that, described PRBS module comprises two PRBS code generators, and one of them is used to produce the code stream of emission, another one PRBS code generator be used to produce and receive code stream PRBS sign indicating number source sequence relatively.
5. error code testing as claimed in claim 4 system is characterized in that, it is 64 the tunnel parallel that described PRBS code generator adopts, and phase place differs from the parallel PRBS sequence of 1 phase place by turn, generates 64 tunnel fixing PRBS sign indicating number of phase place.
6. error code testing as claimed in claim 5 system is characterized in that, described PRBS code generator produces the PRBS sequence and meets PRBS equation takes place.
7. error code testing as claimed in claim 6 system is characterized in that, what described PRBS code generator produced is the m sequence, and m from 3 to 31.
8. error code testing as claimed in claim 1 system is characterized in that described user code generation module is used to produce the user definition sign indicating number, and User Defined data maximum length is 512bit, and minimum length is 4bit.
9. as the described error code testing of claim 1 to 8 system, it is characterized in that, after receiving test data, realize the synchronous of receiving symbol and local code element by the sequence of symhols synchronization module.
10. error code testing as claimed in claim 9 system is characterized in that the synchronous PRBS sequence of described sequence of symhols synchronization module process comprises:
The synchronization acquistion state machine sends the PRBS sequence and loads pulse, and the PRBS sequence of symhols that receives is loaded in the local PRBS code generator as seed;
Local PRBS sign indicating number parallel circuit will produce and receive the code element of PRBS sign indicating number mirror image, mirror image code element and receiving symbol can differ several clocks on phase place, receiving end code element employing delay circuit, synchronous on the new generation PRBS code element clock of the feasible PRBS that receives and this locality.
11. error code testing as claimed in claim 10 system, it is characterized in that, the synchronous PRBS sequence of described sequence of symhols synchronization module process realizes by time-delay: the PRBS sign indicating number of the reception after the time-delay and the local PRBS sign indicating number that produces are delivered to and are got XOR in the comparator, send then and begin to add up the pulse of error code number, behind the time-delay certain hour, read the error code number of statistics, if the error rate is greater than the error code or the door value of the maximum of setting, then send synchronous loading pulse again, till the error rate is less than given door value.
12. error code testing as claimed in claim 9 system, it is characterized in that, described error code counter comprises: one road signal is to clock count, one road signal is to the total counting number of error code under clock of error code, error code calculates and to be divided into that total code element is calculated and number of bit errors calculating, the number of bit errors that the error rate equals to add up/(clock * walk abreast way).
13. error code testing as claimed in claim 9 system is characterized in that, described error code insert module the last position in 64 channel parallel datas of transmitting terminal fixing with 1 XOR.
14., it is characterized in that the connected mode between MCU and the FPGA is by virtual parallel port EPP, RS serial ports or IIC pattern as the described error code testing of one of claim 1 to 12 system.
15. error code testing as claimed in claim 13 system is characterized in that described PRBS sign indicating number clock is at 155MHz～185MHz.
16. as the described error code testing of one of claim 1 to 13 system, it is characterized in that, described error code testing system comprises loop fuction: after starting the PRBS decoding circuit, can produce 64 parallel rood PRBS sign indicating numbers simultaneously, through transtation mission circuit, convert the SerDes and the conversion chip of going here and there that 16 parallel data stream sends to outside high speed to, convert one tunnel at a high speed data-signal to through SerDes and send continuously; Send to outside data, through external circuit or light path, convert signal of telecommunication loopback at a high speed to, loopback signal is as test data.
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