CN117478107A

CN117478107A - Delay calibration method, transmitting end and source synchronous communication system

Info

Publication number: CN117478107A
Application number: CN202311829817.5A
Authority: CN
Inventors: 郑林吉; 段焕利
Original assignee: Core Optical Smart Network Integrated Circuit Design Wuxi Co ltd
Current assignee: Core Optical Smart Network Integrated Circuit Design Wuxi Co ltd
Priority date: 2023-12-28
Filing date: 2023-12-28
Publication date: 2024-01-30
Anticipated expiration: 2043-12-28
Also published as: CN117478107B

Abstract

The invention relates to the technical field of high-speed communication interfaces in integrated circuits, and particularly discloses a delay calibration method, a transmitting end and a source synchronous communication system, which comprises the following steps: a parallel sequence generator for generating a first calibration code and a second calibration code; a sliding window circuit for generating an adjustable delay value for the second calibration code generated by the parallel sequencer; the digital control delay unit is used for generating an adjustable delay value for the first calibration code generated by the parallel sequence generator; the delay calibration state machine enters a bit timing state according to the first detection mode and a word timing state according to the second detection mode, adjusts the delay value of the digital delay unit according to the first error code information in the bit timing state, and adjusts the delay value of the sliding window circuit according to the second error code information in the word timing state. The transmitting end provided by the invention can solve the problem that the numerical control delay unit performs bit timing and word timing on the transmitting end.

Description

Delay calibration method, transmitting end and source synchronous communication system

Technical Field

The present invention relates to the field of high-speed communication interfaces in integrated circuits, and in particular, to a delay calibration method, a transmitting end, and a source synchronous communication system.

Background

In the prior art, a parallel interface transmits data through a plurality of channels, a receiving side samples the data, the arrival time of a plurality of receiving channels is required to be in an effective window, otherwise, sampling errors can occur. Due to the differences of circuit printed board interconnection lines and the like, the situation that the arrival times are inconsistent can occur, and thus the situation that channels are not aligned and the like can occur. A delay alignment mechanism is then introduced to align the channels to ensure that the transmission is correct.

In the prior art, a numerical control delay unit is mainly introduced into a loop to align channels, and the implementation process is mainly concentrated on a receiving side. For example, the first scheme for implementing channel alignment is implemented by a predefined synchronization word, and mainly includes introducing a digital control delay unit at the receiving side to implement bit correction, and then adjusting the delay value of the digital control delay unit at the receiving side by sending the predefined synchronization word to implement the data alignment function of each channel.

The second scheme for realizing channel alignment is a closed loop calibration method based on read-write training delay, specifically adding a controllable delay circuit at a clock or data end, searching a low value and a high value of a data effective window through read-write feedback, and adjusting the delay of the clock and the data. The specific working process comprises the following steps: firstly, setting a delay value of a numerical control delay unit as a minimum value, transmitting a group of data to a receiving end by a transmitting end, then, transmitting the transmitted data back to the transmitting end by the receiving end, comparing the transmitted data with original data until a sudden change that a data difference is consistent with a data difference is generated, indicating that the left boundary of a data effective window is searched, and recording the delay control value of the numerical control delay unit at the moment; then, continuously increasing the delay value of the numerical control delay unit until abrupt change of the data consistency and the data difference occurs, indicating that the right boundary of the data effective window is searched, recording the delay value at the moment, and then averaging the delay value recorded by the left boundary and the delay value recorded by the right boundary to obtain the control value of the numerical control delay unit. The scheme is characterized in that the period of the regulation process is longer, and both sides are required to contain a transceiver circuit on the same PAD so as to ensure the feedback verification of data.

The third scheme for realizing channel alignment is an open loop calibration method based on specific delay, specifically, a fixed delay unit is added at the data or clock end, and the fixed delay setting value is obtained through pre-calculation.

Aiming at the several schemes in the prior art, the first implementation scheme mainly solves the problem that the numerical control delay unit is on the receiving side, but the numerical control delay unit cannot be used as a power when being on the transmitting side, and the channel alignment process can not be carried out any more; the numerical control delay unit of the second implementation scheme is mainly arranged on the transmitting side, so that the problem that the numerical control delay unit is arranged on the transmitting side can be solved, but simplex communication is only realized, and data can not be exchanged by bidirectional simultaneous communication; in the second implementation scheme, the channel alignment is realized based on an open-loop numerical control delay unit, a delay value needs to be preset, and a subsequent calibration function is not needed.

Therefore, in the calibration process mainly on the transmitting side of the digital control delay unit, especially in duplex communication, the scheme in the prior art lacks an effective feedback mechanism to reflect error code information to realize the calibration of the calibration circuit. Therefore, how to solve the delay calibration when the nc delay unit is located at the transmitting side is a technical problem to be solved by those skilled in the art.

Disclosure of Invention

The invention provides a delay calibration method, a transmitting end and a source synchronous communication system, which solve the problem that a numerical control delay unit in the related technology lacks corresponding delay calibration when being positioned at the transmitting end.

As a first aspect of the present invention, there is provided a transmitting terminal, including:

a parallel sequencer for generating a first calibration code when the delay calibration state machine is operating in a bit timing state and a second calibration code when the delay calibration state machine is operating in a word timing state;

a sliding window circuit for generating an adjustable delay value for the second calibration code generated by the parallel sequencer;

the digital control delay unit is used for generating an adjustable delay value for the first calibration code generated by the parallel sequence generator;

a delay calibration state machine comprising a bit timing state and a word timing state for performing a delay calibration method, wherein the delay calibration method comprises:

when starting, setting an initial delay value of a sliding window circuit and an initial delay value of a numerical control delay unit;

when the parallel sequence detector is determined to be in a first detection mode, controlling the delay calibration state machine to enter a bit timing state, and in the bit timing state, when the delay calibration state machine determines that the first calibration code is not matched with the first matching code according to error code information generated by the parallel sequence detector for the first calibration code, adjusting the delay value of the numerical control delay unit until the first calibration code is determined to be matched with the first matching code according to the error code information generated by the parallel sequence detector for the first calibration code, and the matching result is kept stable for a preset period, and determining the delay value corresponding to the numerical control delay unit as the first matching delay value; the parallel sequence detector is capable of generating a first matching code from the received first calibration code;

Maintaining the delay value of the numerical control delay unit at the first matching delay value, controlling the delay calibration state machine to enter a word timing state, when determining that the parallel sequence detector is in a second detection mode, determining that the second calibration code is not matched with the second matching code according to error code information generated by the parallel sequence detector for the second calibration code by the delay calibration state machine in the word timing state, adjusting the delay value of the sliding window circuit until the second calibration code is determined to be matched with the second matching code according to error code information generated by the parallel sequence detector for the second calibration code, and maintaining the matching result for a stable preset period, and determining the delay value of the sliding window circuit as the second matching delay value at the moment; the parallel sequence detector is capable of generating a second matching code from the received second calibration code;

and controlling the source synchronous communication system to work by taking the adjustable delay value of the numerical control delay unit at the transmitting end as a first matched delay value and the adjustable delay value of the sliding window circuit as a second matched delay value, and controlling the delay calibration state machine to exit the bit timing state and the word timing state.

Further, the sliding window circuit comprises a sliding window delay unit which is connected in a multistage cascade,

Each stage of sliding window delay unit comprises a D trigger and a first data selector, the input end of the D trigger of each stage of sliding window delay unit is connected with the output end of the D trigger of the previous stage of sliding window delay unit from the second stage of sliding window delay unit, the output end of the D trigger of each stage of sliding window delay unit is connected with the first input end of the first data selector of the same stage, the clock signal end of the D trigger of each stage of sliding window delay unit is used for inputting a clock signal,

the second input end of the first data selector of each stage of sliding window delay unit is connected with the output end of the first data selector of the previous stage of sliding window delay unit, the selection control end of each stage of sliding window delay unit is used for inputting delay control word signals,

the input end of the D trigger of the first-stage sliding window delay unit and the second input end of the first data selector of the first-stage sliding window delay unit are both used for inputting output signals of the sequencer, and the output end of the first data selector of the last-stage sliding window delay unit is used for outputting adjustable delay values of the sliding window circuit.

Further, the numerical control delay unit comprises a coarse tuning circuit and a fine tuning circuit, the output end of the coarse tuning circuit is connected with the input end of the fine tuning circuit, the input end of the coarse tuning circuit is the input end of the numerical control delay unit, the output end of the fine tuning circuit is the output end of the numerical control delay unit,

The coarse tuning circuit is used for performing first delay granularity calculation on the initial delay value in a bit timing state to obtain a first granularity delay value, wherein a calculation formula of the first granularity delay value is as follows:

，

wherein,representing a first granularity delay value,/for>Representing the intrinsic delay value of the coarse tuning circuit, +.>Delay control code representing coarse tuning circuit, +.>A delay step value representing a coarse tuning circuit;

the fine tuning circuit is configured to perform a second delay granularity calculation on the first granularity delay value in a bit timing state to obtain a second granularity delay value, where a delay granularity of the first granularity delay value is greater than a delay granularity of the second granularity delay value, and a calculation formula of the second granularity delay value is as follows:

，

wherein,representing a first granularity delay value,/for>Representing the value of the inherent delay of the fine tuning circuit,delay control word representing fine tuning circuit, +.>A delay step value representing a fine tuning circuit;

and the sum of the first granularity delay value and the second granularity delay value is the delay value of the numerical control delay unit.

Further, the coarse tuning circuit comprises a plurality of stages of cascaded coarse tuning units, each stage of coarse tuning unit comprises a second data selector and a delay unit, the input end of each stage of delay unit is connected with the output end of the previous stage of delay unit, the first input end of each stage of second data selector is connected with the output end of the previous stage of second data selector, and the second input end of each stage of second data selector is connected with the output end of the delay unit of the same stage;

The input end of the first-stage delay unit is connected with the first input end of the first-stage second data selector, and the input ends of the first-stage delay unit and the first-stage second data selector are both input ends of the coarse adjustment circuit; the output end of the second data selector of the last stage is the output end of the coarse tuning circuit;

the fine tuning circuit comprises a multi-stage cascaded tri-state gate array, the input end of each stage of tri-state gate array is connected with the output end of the previous stage of tri-state gate array from the second stage of tri-state gate array, the input end of the first stage of tri-state gate array is the input end of the fine tuning circuit, and the output end of the last stage of tri-state gate array is the output end of the fine tuning circuit; each stage of tristate gate array comprises a plurality of tristate gates with input ends connected and output ends connected.

Further, the parallel sequence generator comprises n cascaded D flip-flops for generating a PRBS code;

when n is 7, the PRBS code is a PRBS7 code, and the generating polynomial of the PRBS7 code is x ⁷ + x ⁶ +1, the parallel sequencer comprising 7 cascaded D flip-flops, the generator polynomial characterization: the output end of the sixth D trigger and the output end of the seventh D trigger are subjected to exclusive OR operation and then fed back to the first D trigger for circulation until the seventh D trigger outputs the PRBS7 code;

When n is 9, the PRBS code is a PRBS9 code, and the generating polynomial of the PRBS9 code is x ⁹ + x ⁵ +1, the parallel sequencer comprising 9 cascaded D flip-flops, the generator polynomial characterization: the output end of the fifth D trigger and the output end of the ninth D trigger are subjected to exclusive OR operation and then fed back to the first D trigger for circulation until the ninth trigger outputs the PRBS9 code;

when n is 15, the PRBS code is PRBS15 code, and the generating polynomial of the PRBS15 code is x ¹⁵ + x ¹⁴ +1, the parallel sequencer comprising 15 cascaded D flip-flops, the generator polynomial being characterized: fourteenth D flip-flopThe output end and the output end of the fifteenth D trigger are subjected to exclusive OR operation and then fed back to the first D trigger for circulation until the fifteenth D trigger outputs the PRBS15 code;

when n is 23, the PRBS code is PRBS23 code, and the generator polynomial of the PRBS23 code is x ²³ + x ¹⁸ +1, the parallel sequencer comprising 23 cascaded D flip-flops, the generator polynomial characterization: the output end of the eighteenth D trigger and the output end of the twenty-third D trigger are subjected to exclusive OR operation and then fed back to the first D trigger for circulation until the thirteenth D trigger outputs the PRBS23 code;

When n is 31, the PRBS code is PRBS31 code, and the generator polynomial of the PRBS31 code is x ³¹ + x ²⁸ +1, the parallel sequencer comprising 31 cascaded D flip-flops, the generator polynomial being characterized: and the output end of the twenty eighth D trigger and the output end of the thirty first D trigger are subjected to exclusive OR operation and then fed back to the first D trigger for circulation until the thirty first D trigger outputs the PRBS31 code.

As another aspect of the present invention, there is provided a source synchronous communication system comprising a receiving end and the transmitting end described above, the transmitting end and the receiving end being communicatively connected,

the receiving end at least comprises a parallel sequence detector, and the code pattern configuration of the parallel sequence detector is the same as that of a parallel sequence generator of the transmitting end;

the parallel sequence detector can detect a first calibration code and a second calibration code sent by the sending end, and generates error code information according to the detected first calibration code or second calibration code.

Further, the parallel sequence detector comprises a plurality of cascaded D flip-flops;

when the PRBS code generated by the parallel sequence generator is the PRBS7 code, the parallel sequence detector comprises 7 cascaded D triggers, and the output end of the sixth D trigger and the output end of the seventh D trigger are subjected to exclusive OR operation to obtain a first exclusive OR operation result;

When the PRBS code generated by the parallel sequence generator is a PRBS9 code, the parallel sequence detector comprises 9 cascaded D triggers, and the output end of the fifth D trigger and the output end of the ninth D trigger are subjected to exclusive OR operation to obtain a first exclusive OR operation result;

when the PRBS code generated by the parallel sequence generator is a PRBS15 code, the parallel sequence detector comprises 15 cascaded D triggers, and the output end of the fourteenth D trigger and the output end of the fifteenth D trigger are subjected to exclusive OR operation to obtain a first exclusive OR operation result;

when the PRBS code generated by the parallel sequence generator is a PRBS23 code, the parallel sequence detector comprises 23 cascaded D triggers, and the output end of the eighteenth D trigger and the output end of the twenty third D trigger are subjected to exclusive OR operation to obtain a first exclusive OR operation result;

when the PRBS code generated by the parallel sequence generator is a PRBS31 code, the parallel sequence detector comprises 31 cascaded D triggers, and the output end of the twenty eighth D trigger and the output end of the thirty first D trigger are subjected to exclusive OR operation to obtain a first exclusive OR operation result;

when the parallel sequence detector is in a first detection mode, a first exclusive-or operation result of the parallel sequence detector is a first calibration code predicted value generated according to a received first calibration code, and the parallel sequence detector can obtain first error code information after exclusive-or operation according to the first calibration code and the first calibration code predicted value;

When the parallel sequence detector is in a second detection mode, a first exclusive-or operation result of the parallel sequence detector is fed back to the input end of the first D trigger to be circulated, and the output result of the last D trigger and the received second calibration code are subjected to exclusive-or operation to obtain second error code information.

As another aspect of the present invention, there is provided a delay calibration method, which is applied to the source synchronous communication system described above, the delay calibration method comprising:

starting a delay calibration state machine, and setting an initial delay value of a sliding window circuit and an initial delay value of a numerical control delay unit;

when the parallel sequence detector is determined to be in a first detection mode, controlling the delay calibration state machine to enter a bit timing state, and in the bit timing state, when the delay calibration state machine determines that the first calibration code is not matched with the first matching code according to error code information generated by the parallel sequence detector for the first calibration code, adjusting the delay value of the numerical control delay unit until the first calibration code is determined to be matched with the first matching code according to the error code information generated by the parallel sequence detector for the first calibration code, and the matching result is kept stable for a preset period, and determining the delay value corresponding to the numerical control delay unit as the first matching delay value; the parallel sequence detector is capable of generating a first matching code from the received first calibration code, and the parallel sequence generator is capable of generating the first calibration code in the bit timing state;

Maintaining the delay value of the numerical control delay unit at the first matching delay value, controlling the delay calibration state machine to enter a word timing state, when determining that the parallel sequence detector is in a second detection mode, determining that the second calibration code is not matched with the second matching code according to error code information generated by the parallel sequence detector for the second calibration code by the delay calibration state machine in the word timing state, adjusting the delay value of the sliding window circuit until the second calibration code is determined to be matched with the second matching code according to error code information generated by the parallel sequence detector for the second calibration code, and maintaining the matching result for a stable preset period, and determining the delay value of the sliding window circuit as the second matching delay value at the moment; the parallel sequence detector is capable of generating a second matching code from the received second calibration code, the parallel sequence generator is capable of generating the second calibration code in the word timing state;

and controlling the source synchronous communication system to work by taking the delay value of the numerical control delay unit of the transmitting end as a first matched delay value and the delay value of the sliding window circuit as a second matched delay value, and controlling the delay calibration state machine to exit the bit timing state and the word timing state.

Further, when the delay calibration state machine determines that the first calibration code is not matched with the first matching code according to the error code information generated by the parallel sequence detector for the first calibration code, adjusting the delay value of the numerical control delay unit until the first calibration code is matched with the first matching code according to the error code information generated by the parallel sequence detector for the first calibration code, and the matching result keeps stable for a preset period, determining the delay value corresponding to the numerical control delay unit at the moment as the first matching delay value, including:

receiving first error code information returned by the parallel sequence detector, wherein the first calibration code sequentially passes through the sliding window circuit and the numerical control delay unit and is output to the parallel sequence detector, and the parallel sequence detector can generate a first matching code aiming at the first calibration code in a first detection mode and generate first error code information according to a matching result of the first calibration code and the first matching code;

judging the level state of the first error code information;

if the first error code information is in a high level, the current delay value of the numerical control delay unit is adjusted, and the step of receiving the first error code information returned by the parallel sequence detector is repeatedly executed until the obtained first error code information is in a low level;

And when the level states of the first error code information received in the continuous preset period are all low levels, determining a first matched delay value of the numerical control delay unit according to the current delay value corresponding to the numerical control delay unit.

Further, when the delay calibration state machine in the word timing state determines that the second calibration code is not matched with the second matching code according to the error code information generated by the parallel sequence detector for the second calibration code, adjusting the delay value of the sliding window circuit until the second calibration code is determined to be matched with the second matching code according to the error code information generated by the parallel sequence detector for the second calibration code, and the matching result is kept stable for a preset period, and determining the delay value of the sliding window circuit at the moment as the second matching delay value comprises:

receiving second error code information returned by the parallel sequence detector, wherein the second calibration code sequentially passes through the sliding window circuit and the numerical control delay unit and is output to the parallel sequence detector, and the parallel sequence detector can generate a second matching code aiming at the second calibration code in a second detection mode and generate second error code information according to a matching result of the second calibration code and the second matching code;

Judging the level state of the second error code information;

if the second error code information is in a high level, the current delay value of the sliding window circuit is adjusted, and the step of receiving the second error code information returned by the parallel sequence detector is repeatedly executed;

and when the level states of the second error code information received in the continuous preset period are all low levels, determining that the current delay value corresponding to the sliding window circuit is a second matched delay value of the sliding window circuit.

The transmitting end provided by the invention enters a bit timing state according to the first detection mode of the sequence detector of the receiving end and enters a word timing state according to the second detection mode of the sequence detector of the receiving end through the delay calibration state machine, and adjusts the delay value of the numerical control delay unit according to the first error code information output by the sequence detector of the receiving end in the bit timing state, and adjusts the delay value of the sliding window circuit according to the second error code information output by the sequence detector of the receiving end in the word timing state.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the description serve to explain, without limitation, the invention.

Fig. 1 is a block diagram of a transmitting end provided by the present invention.

FIG. 2 is a schematic diagram of a bit timing process provided by the present invention.

Fig. 3 is a schematic diagram of a word timing process provided by the present invention.

Fig. 4a is a flow chart illustrating the operation of the delay calibration state provided by the present invention.

FIG. 4b is a flow chart of the bit timing state provided by the present invention.

Fig. 4c is a flow chart of the word timing state provided by the present invention.

Fig. 5 is a schematic circuit diagram of a sliding window circuit according to the present invention.

Fig. 6a is a schematic circuit diagram of a digitally controlled delay cell according to the present invention.

Fig. 6b is a schematic diagram of a specific circuit of the delay unit according to the present invention.

Fig. 7a is a schematic circuit diagram of a parallel sequence generator for generating PRBS7 codes according to the present invention.

Fig. 7b is a schematic circuit diagram of a parallel sequence generator for generating PRBS9 codes according to the present invention.

Fig. 7c is a schematic circuit diagram of a parallel sequence generator for generating PRBS15 codes according to the present invention.

Fig. 7d is a schematic circuit diagram of a parallel sequence generator for generating PRBS23 codes according to the present invention.

Fig. 7e is a schematic circuit diagram of a parallel sequence generator for generating PRBS31 codes according to the present invention.

Fig. 8 is a block diagram of a source synchronous communication system according to the present invention.

Fig. 9a is a schematic diagram of the operation of the sequence detector in the bit timing process according to the present invention.

Fig. 9b is a schematic diagram of the operation of the sequence detector in the word timing process according to the present invention.

Fig. 9c is a schematic circuit diagram of an exclusive or logic circuit according to the present invention.

Fig. 10a is a schematic structural diagram of a parallel sequence detector in a first detection mode during sequence detection of the PRBS9 provided by the present invention.

Fig. 10b is a schematic structural diagram of the parallel sequence detector in the second detection mode when the PRBS9 is used for sequence detection.

Fig. 11 is a flowchart of a delay calibration method provided by the present invention.

Detailed Description

It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In this embodiment, a transmitting end is provided, fig. 1 is a block diagram of a transmitting end 10 provided according to an embodiment of the present invention, as shown in fig. 1, including:

a parallel sequencer 100 for generating a first calibration code when the delay calibration state machine is operating in a bit timing state and a second calibration code when the delay calibration state machine is operating in a word timing state;

in the embodiment of the present invention, the parallel sequencer 100 may generate a code pattern of a specific pattern, such as pseudo random binary code (PRBS) and custom data pattern, and the parallel sequencer 100 mainly generates a code that can be self-checked to provide an excitation signal for later calibration.

In particular, since the operating states of the delay calibration state machine of the subsequent stage include a bit timing state and a word timing state, the parallel sequencer 100 may generate a first calibration code for the bit timing state and a second calibration code for the word timing state.

A sliding window circuit 200 for generating an adjustable delay value for the second calibration code generated by the parallel sequencer;

in the embodiment of the present invention, the sliding window circuit 200 is capable of delaying the data of the sender multichannel for several integer periods, and specifically, in the embodiment of the present invention, an adjustable delay value may be generated for a word timing process described below.

A digital control delay unit 300 for generating an adjustable delay value for the first calibration code generated by the parallel sequencer;

in the embodiment of the present invention, the digital control delay unit 300 can adjust the phase of data or clock to output different delay values, thereby implementing the bit timing process described below.

Delay calibration state machine 400, including a bit timing state and a word timing state, is used to perform a delay calibration method.

It should be appreciated that the delay calibration state machine 400 is capable of controlling the parallel sequencer 100, the sliding window circuit 200, and the digitally controlled delay unit 300 to implement the bit alignment and word alignment processes.

In an embodiment of the present invention, a delay calibration method in a delay calibration state machine includes:

at start-up, setting an initial delay value of the sliding window circuit 200 and an initial delay value of the numerical control delay unit; it should be noted that, the initial delay value of the sliding window circuit and the initial delay value of the numerical control delay unit are both generally 0. Even if the sliding window circuit is not 0, the initial delay value is usually small, and the subsequent numerical control delay units can also compensate, so that the initial delay value of the sliding window circuit is negligible.

When the parallel sequence detector 100 is determined to be in the first detection mode, the delay calibration state machine 400 is controlled to enter a bit timing state, in the bit timing state, when the delay calibration state machine 400 determines that the first calibration code is not matched with the first matching code according to the error code information generated by the parallel sequence detector for the first calibration code, the delay value of the numerical control delay unit 300 is adjusted until the first calibration code is determined to be matched with the first matching code according to the error code information generated by the parallel sequence detector 100 for the first calibration code, the matching result is kept stable for a preset period, for example, the error code information is low, the error code information detected in the preset period is kept low, and the delay value corresponding to the numerical control delay unit 300 at the moment is determined to be the first matching delay value; the parallel sequence detector is capable of generating a first matching code from the received first calibration code;

Maintaining the delay value of the numerical control delay unit 300 at the first matching delay value, controlling the delay calibration state machine 400 to enter a word timing state, when determining that the parallel sequence detector is in a second detection mode, determining that the second calibration code is not matched with the second matching code according to error code information generated by the parallel sequence detector for the second calibration code by the delay calibration state machine in the word timing state, adjusting the delay value of the sliding window circuit 200 until the second calibration code is matched with the second matching code according to error code information generated by the parallel sequence detector for the second calibration code, maintaining a stable preset period of the matching result, and determining the delay value of the sliding window circuit 200 as the second matching delay value; the parallel sequence detector is capable of generating a second matching code from the received second calibration code;

the source synchronous communication system is controlled to work by taking the adjustable delay value of the numerical control delay unit 300 at the transmitting end as a first matched delay value and the adjustable delay value of the sliding window circuit as a second matched delay value, and the delay calibration state machine is controlled to exit the bit timing state and the word timing state.

In the embodiment of the invention, the transmitting end is applied to the source synchronous communication system, and because the source synchronous communication system is a multi-channel synchronous communication system, the sampling clock or the delay of the channel of the receiving end may not be in an effective sampling window, so that the receiving end needs to retime the clock at the receiving end for improving the reliability. The re-timing process is that the transmitting side transmits a predefined code, the receiving side continuously detects the code, and the numerical control delay unit performs delay scanning in a designated control period until the receiving side detects the predefined code. At this point the retiming is completed and this process may be referred to as a bit timing process. As shown in fig. 2, the sampling position of the clock is now between the valid sampling windows. However, for multi-channel, there is also a case of inter-channel bit offset, so a process of inter-channel delay alignment is also required, which may be called a word timing process. As shown in fig. 3, the offset between the channels is calibrated.

Therefore, the transmitting end provided by the invention enters the bit timing state according to the first detection mode of the sequence detector of the receiving end and enters the word timing state according to the second detection mode of the sequence detector of the receiving end through the delay calibration state machine, and adjusts the delay value of the numerical control delay unit according to the first error code information output by the sequence detector of the receiving end in the bit timing state, and adjusts the delay value of the sliding window circuit according to the second error code information output by the sequence detector of the receiving end in the word timing state.

It should be appreciated that in embodiments of the present invention, delay calibration state machine 400 primarily coordinates the states between sequencer 100, sliding window circuit 200, digitally controlled delay unit 300, and the sequence detector. The delay calibration state machine mainly comprises a bit timing state and a word timing state, and as shown in fig. 4a, the operation flow of the delay calibration state machine is as follows:

S1: the delay calibration state machine is started to perform some initialization settings, the transmitting end sets the test excitation of the parallel sequence generator to a preset code pattern, and the sliding window circuit and the numerical control delay unit are both set to be the minimum delay (the minimum delay is an initial delay value here, and the initial delay value is usually set to be 0) for output. The receiving end sets the sequence detector as a first detection mode.

S2: a bit timing state is entered. The bit timing state is to re-time the reception at both sides, and ensure that the clock is in an effective sampling window when sampling. As shown in fig. 4b, the specific procedure of the adjustment in the bit timing state is:

s201: and the parallel sequence generator at the transmitting end outputs the first calibration code.

S202: the sequence detector of the receiving end works in a first detection mode, performs matching of the first calibration code, and feeds back a matching result of the first calibration code to the transmitting end.

S203: the sending end judges the received first error code information, if the level of the first error code information is high, the delay of the numerical control delay unit is adjusted, and the step S201 is carried out again; otherwise, if the level is low, a plurality of clock cycles are continuously monitored, the low level is always kept, the channel bit timing is determined to be stable, the channel bit timing is considered to be completed, the bit timing state is jumped out, and the S3 word timing state is entered.

S3: a word timing state is entered. The word timing state is used to calibrate the channel offset. Correcting the inter-channel offset. As shown in fig. 4c, the specific procedure of the adjustment in the word timing state is:

s301: the delay value of the numerical control delay unit keeps the value of the bit timing state unchanged. The sliding window circuit is output through, and delay is not introduced by the sliding window circuit. The sequence detector of the receiving end operates in a second detection mode.

It should be understood here that the first calibration code issued by the parallel sequencer can pass through the sliding window circuit after passing through the bypass mode to the digitally controlled delay unit without introducing a delay in the initial delay value of 0 of the sliding window circuit, so that the sliding window circuit does not generate a delay adjustment for the first calibration code.

S302: the calibration code output of the transmitting end sequence generator passes through a sliding window circuit and a numerical control delay unit, and then passes through a channel to reach the sequence detector of the receiving end. The receiving end sequence detector compares the code pattern generated by the internal sequence generator with the received real-time code pattern to match the second calibration code, and feeds back the matching result of the second calibration code to the transmitting end.

S303: the transmitting end judges the received second error code information, if the level of the second error code information is high, adjusts the delay of the sliding window circuit of the corresponding channel, and then enters step S302 again. If the level of the second error code information is low, continuously monitoring a plurality of clock cycles, and keeping stable, and considering that the channel bit timing is completed and jumping out of the word timing state of the channel.

S4: and (5) ending the delay calibration state and entering other working states.

Specifically, as shown in fig. 5, the sliding window circuit 200 includes a sliding window delay unit 210 connected in cascade in a plurality of stages,

each stage of the sliding window delay units 210 comprises a D flip-flop 211 and a first data selector 212, starting from the second stage of the sliding window delay units, the input end of the D flip-flop 211 of each stage of the sliding window delay units is connected with the output end of the D flip-flop 211 of the previous stage of the sliding window delay unit, the output end of the D flip-flop 211 of each stage of the sliding window delay units is connected with the first input end of the first data selector 212 of the same stage, the clock signal end of the D flip-flop 211 of each stage of the sliding window delay units is used for inputting a clock signal,

the second input terminal of the first data selector 212 of each stage of sliding window delay unit is connected to the output terminal of the first data selector 212 of the previous stage of sliding window delay unit, the selection control terminal of each stage of sliding window delay unit is used for inputting a delay control word signal,

the input end of the D flip-flop 211 of the first stage sliding window delay unit and the second input end of the first data selector 212 of the first stage sliding window delay unit are both used for inputting the output signal of the sequencer, and the output end of the first data selector 212 of the last stage sliding window delay unit is used for outputting the adjustable delay value of the sliding window circuit.

In the embodiment of the present invention, the output end of the parallel sequencer 100 is connected to the input of the sliding window circuits of N channels, and the paths of the different first data selectors 212 are selected by the delay control word, so as to implement delays of different integer periods. Delay value of specific sliding window circuitCode represents a delay control word and T represents a clock period of the clock signal CLK.

Specifically, as shown in fig. 6a, the digitally controlled delay unit 300 includes a coarse tuning circuit 310 and a fine tuning circuit 320, wherein an output end of the coarse tuning circuit 310 is connected to an input end of the fine tuning circuit 320, coarse tuning and fine tuning are performed according to a delay adjustment signal of a delay calibration state machine, an input end of the coarse tuning circuit 310 is an input end of the digitally controlled delay unit 300, an output end of the fine tuning circuit 320 is an output end of the digitally controlled delay unit 300,

the coarse tuning circuit 310 is configured to perform a first granularity of delay calculation on an initial delay value in a bit timing state to obtain a first granularity delay value, where a calculation formula of the first granularity delay value is:

，

wherein,representing a first granularity delay value,/for>Representing the intrinsic delay value of the coarse tuning circuit, +.>Delay control code representing coarse tuning circuit, +. >A delay step value representing a coarse tuning circuit;

the fine tuning circuit 320 is configured to perform a second delay granularity calculation on the first granularity delay value in the bit timing state to obtain a second granularity delay value, where a delay granularity of the first granularity delay value is greater than a delay granularity of the second granularity delay value, and a calculation formula of the second granularity delay value is:

，

It should be understood that the digitally controlled delay unit 300 specifically includes a coarse tuning circuit and a fine tuning circuit, and performs coarse tuning and then fine tuning on the signal output from the sliding window circuit. The total delay value of the numerical control delay unit is the sum of the first granularity delay value of the coarse tuning circuit and the second granularity delay value of the fine tuning circuitThe calculation formula of (2) is as follows:

。

it is noted that the coarse tuning section and the fine tuning section are uniformly encoded in the digitally controlled delay unit, such as coarse tuning 3 bits and fine tuning 3 bits, and then, for the delay calibration state machine, when the delay value of the digitally controlled delay unit needs to be obtained, the control code including the coarse tuning control bit and the fine tuning control bit is scanned, the upper bits representing coarse tuning and the lower bits representing fine tuning. Preferably, the delay calibration state machine may scan the control code in a low to high or high to low order.

Similarly, when a delay adjustment signal from the delay calibration state machine is received, the NC delay unit reads the coarse control bit and the fine control bit according to the rule sampled by the NC delay unit through unified coding, and then controls the coarse control bit and the fine control bit according to the coarse control bit.

More specifically, the coarse tuning circuit 310 includes a plurality of cascaded coarse tuning units 311, each of the coarse tuning units includes a second data selector 311a and a delay unit 311b, from the second coarse tuning unit, an input terminal of each of the delay units 311b is connected to an output terminal of a previous delay unit 311b, a first input terminal of each of the second data selectors 311a is connected to an output terminal of the previous second data selector 311a, and a second input terminal of each of the second data selectors 311a is connected to an output terminal of the delay unit 311b of the same stage;

the input end of the first stage delay unit 311b is connected with the first input end of the first stage second data selector 311a, and is the input end of the coarse tuning circuit 311; the output end of the second data selector 311a of the last stage is the output end of the coarse tuning circuit 311;

the fine tuning circuit 320 comprises a multi-stage cascaded tri-state gate array 321, wherein from a second stage tri-state gate array 321, the input end of each stage tri-state gate array is connected with the output end of the previous stage tri-state gate array 321, the input end of the first stage tri-state gate array is the input end of the fine tuning circuit 320, and the output end of the last stage tri-state gate array is the output end of the fine tuning circuit 320; each stage of tristate gate array comprises a plurality of tristate gates with input ends connected and output ends connected.

It should be noted that, in the embodiment of the present invention, the control end of each stage of the tri-state gate array may be connected to a decoder, where the decoder may convert the control signal of the input binary code into a control code and input the control code to the control end of the corresponding tri-state gate array to implement control over the tri-state gate array.

In the embodiment of the present invention, a specific schematic circuit diagram of the delay unit 311b is shown in fig. 6 b. The delay unit 311b includes a plurality of buffers connected in series, and the larger the number of buffers is, the larger the delay is.

Specifically, in an embodiment of the present invention, the parallel sequencer 100 includes n cascaded D flip-flops for generating the PRBS code.

It should be appreciated that the parallel sequence generator 100 may generate patterns such as PRBS codes or custom codes.

Taking the example of generating PRBS codes, the polynomial to generate PRBS is:

PRBS31：x ³¹ + x ²⁸ + 1，

PRBS23：x ²³ + x ¹⁸ + 1，

PRBS15：x ¹⁵ + x ¹⁴ + 1，

PRBS9：x ⁹ + x ⁵ +1，

PRBS7：x ⁷ +x ⁶ +1。

as shown in fig. 7a, when n is 7, the PRBS code is a PRBS7 code, and the generator polynomial of the PRBS7 code is x ⁷ + x ⁶ +1, the parallel sequence generator comprises 7 cascaded D flip-flops, the PRBS7 code generator polynomial is x ⁷ + x ⁶ The meaning of the +1 representation is: the output end of the sixth D trigger and the output end of the seventh D trigger are subjected to exclusive OR operation and then fed back to the first D trigger for circulation until the seventh D trigger outputs the PRBS7 code;

As shown in FIG. 7a, X1 to X7 are D flip-flops, and X6 and X7 exclusive OR outputs are fed back to X1, so that the PRBS7 code is continuously output by the feedback loop.

As shown in fig. 7b, when n is 9, the PRBS code is a PRBS9 code, and the generator polynomial of the PRBS9 code is x ⁹ + x ⁵ +1, said parallelThe sequence generator comprises 9 cascaded D flip-flops, and the PRBS9 code has a generator polynomial of x ⁹ + x ⁵ The meaning of the +1 representation is: the output end of the fifth D trigger and the output end of the ninth D trigger are subjected to exclusive OR operation and then fed back to the first D trigger for circulation until the ninth trigger outputs the PRBS9 code;

as shown in FIG. 7b, X1 to X9 are D flip-flops, and X5 and X9 exclusive OR outputs are fed back to X1, so that the PRBS9 code is continuously output by the feedback loop.

As shown in FIG. 7c, when n is 15, the PRBS code is a PRBS15 code, and the generator polynomial of the PRBS15 code is x ¹⁵ + x ¹⁴ +1, the parallel sequence generator comprises 15 cascaded D flip-flops, the PRBS15 code generator polynomial is x ¹⁵ + x ¹⁴ The meaning of the +1 representation is: the output end of the fourteenth D trigger and the output end of the fifteenth D trigger are subjected to exclusive OR operation and then fed back to the first D trigger for circulation until the fifteenth D trigger outputs the PRBS15 code;

as shown in FIG. 7c, X1 to X15 are D flip-flops, and X14 and X15 exclusive OR outputs are fed back to X1, so that the PRBS15 code is continuously output by the feedback loop.

As shown in FIG. 7d, when n is 23, the PRBS code is a PRBS23 code, and the generator polynomial of the PRBS23 code is x ²³ + x ¹⁸ +1, the parallel sequence generator comprises 23 cascaded D flip-flops, the PRBS23 code generator polynomial is x ²³ + x ¹⁸ The meaning of the +1 representation is: the output end of the eighteenth D trigger and the output end of the twenty-third D trigger are subjected to exclusive OR operation and then fed back to the first D trigger for circulation until the thirteenth D trigger outputs the PRBS23 code;

as shown in FIG. 7D, X1 to X23 are D flip-flops, and the exclusive OR output of X18 and X23 is fed back to X1, so that the PRBS23 code is continuously output by the feedback loop.

As shown in fig. 7e, when n is 31, the PRBS code is a PRBS31 code, and the generator polynomial of the PRBS31 code is x ³¹ + x ²⁸ +1, the parallel sequence generator comprises 31 cascaded D flip-flops, the PRBS31 code generator polynomial is x ³¹ + x ²⁸ The meaning of the +1 representation is: first, theAnd the output end of the twenty-eighth D trigger and the output end of the thirty-first D trigger are subjected to exclusive OR operation and then fed back to the first D trigger for circulation until the thirty-first D trigger outputs the PRBS31 code.

As shown in FIG. 7e, X1 to X31 are D flip-flops, and X28 and X31 exclusive OR outputs are fed back to X1, so that the PRBS31 code is continuously output by the feedback loop.

In summary, the transmitting end provided by the invention solves the problems of bit timing and word timing when the numerical control delay unit is at the transmitting end by performing bit timing firstly by the delay calibration state machine matched with the numerical control delay unit and then performing word timing by the delay calibration state machine matched with the sliding window circuit.

As another embodiment of the present invention, there is provided a source synchronous communication system, as shown in fig. 8, including: a transmitting end 10 and a receiving end 20, the transmitting end 10 and the receiving end 20 are in communication connection,

the transmitting end 10 includes the transmitting end described above;

the receiving end 20 at least comprises a parallel sequence detector 21, and the code pattern configuration of the parallel sequence detector 21 is the same as the code pattern configuration of the parallel sequence generator 100 of the transmitting end;

the parallel sequence detector 21 can detect the calibration code sent by the sending end, and generate error code information according to the detection result.

In the embodiment of the invention, the source synchronous communication system comprises the transmitting end which is the transmitting end and can realize the bit timing and word timing process by combining the transmitting end with the transmitting end, so that the source synchronous communication system can realize channel alignment when the transmitting end is provided with the numerical control delay unit.

Specifically, in connection with fig. 8 and the foregoing detailed description of the transmitting end, the process of embodying bit timing and word timing is described as follows:

(1) Bit timing process. The parallel sequencer of the transmitting end 10 generates a predetermined pattern code, such as PRBS or other custom code, that passes through the sliding window circuit, where the data is directly bypassed (i.e., the data is passed directly through the bypass pattern of the sliding window circuit without delay) because the bit timing process is performed first. The numerical control delay unit delays again, the delay value is set to be a value at a boundary, generally a minimum value, and then the delay value is sent out through a driver of a sending end, a parallel sequence detector of a receiving end performs code pattern matching detection, a matching result is given, and error code information is fed back to the sending end. And the delay calibration state machine of the transmitting end continuously adjusts the delay value of the numerical control delay unit according to the fed back error code information so as to adjust the phase of the transmitted data and then carry out the next round of adjustment process. Finally, when the error code information fed back by each channel keeps a stable value without error code in a specified period, the bit timing process is considered to be completed. The sequence detector of one channel of the receiving end works as shown in fig. 9 a.

It should be appreciated that as shown in fig. 9a, the sequence detector is based on the self-checking characteristics of the PRBS code and uses the received beats of data as a seed to generate the next beat of data. And comparing the generated next beat of data with the actually received data to obtain error code information. For example, if the comparison is identical, the error information is 0, and if the comparison is not identical, the error information is 1.

(2) Word timing process. After bit timing is finished, the transmitting end carries out sliding window delay on the transmitting data of each channel, the numerical control delay unit keeps the delay value of the bit timing unchanged, the parallel sequence detector of the receiving end carries out code pattern matching, and error code information is fed back to the delay calibration state machine of the transmitting end so as to adjust and control the delay value of the sliding window circuit of each channel.

It should be noted that, the specific process bit of pattern matching is that the receiving end has a pattern generator (i.e. sequence detector) with the same configuration as the parallel sequence generator pattern of the transmitting end, and there is no channel offset. The received real-time pattern (data of the received bit timing) is pattern matched (e.g., by a comparator circuit) with an internally generated pattern (pattern generated by an internal pattern generator), and the function of the comparator circuit can be implemented using an exclusive-or logic circuit. The sequence detector of one channel of the receiving end works as shown in fig. 9 b.

Specifically, as shown in fig. 9c, an example of the xor logic circuit is specifically composed of a plurality of switching tubes to implement the xor function, and the specific working principle is well known to those skilled in the art and will not be described herein.

In an embodiment of the present invention, the parallel sequence detector 21 includes a plurality of cascaded D flip-flops;

when the parallel sequence detector is in a first detection mode (namely, a calibration state machine of a transmitting end is in a bit timing state), a first exclusive-or operation result of the parallel sequence detector is a first calibration code predicted value generated according to a received first calibration code, and the parallel sequence detector can obtain first error code information after carrying out exclusive-or operation according to the first calibration code and the first calibration code predicted value;

when the parallel sequence detector is in a second detection mode (namely, the calibration state machine of the transmitting end is in a word timing state), the first exclusive-or operation result of the parallel sequence detector is fed back to the input end of the first D trigger for circulation, and the output result of the last D trigger and the received second calibration code are subjected to exclusive-or operation to obtain second error code information.

It is noted that, on the parallel sequence detector, a high-speed communication interface and a low-speed communication interface are provided, where the high-speed communication interface and the low-speed communication interface are both connected to the transmitting end, the high-speed interface is used for receiving data information from the receiving end, such as a first/second calibration code with several adjustable delay values, and the low-speed communication interface is used for receiving control information from the transmitting end, such as control information of a mode of the sequence detector, preferably, before performing calibration in a bit timing state or a word timing state, a control message about mode switching can be sent first, so as to control the sequence detector to enter a corresponding first detection mode or a second detection mode.

The parallel sequence detector has different structures according to different detection modes. In the embodiment of the present invention, taking the sequence detection of the PRBS9 as an example, the structure of other PRBS codes is adaptively changed according to the structure of the sequence generator.

As shown in fig. 10a, the parallel sequence detector is in the first detection mode, and the data of the PRBS and the predicted value of the PRBS are xored and error information is output to match the sender to complete bit timing.

Fig. 10b shows a schematic diagram of the parallel sequence detector in the second detection mode. After the bit timing is completed, there is also a channel offset, so detection of the channel offset is also required. In this method, the received data is compared with the PRBS in the receiving end, and when the waveforms match, the error information is output as no signal, which is indicated by a low level signal. When the waveforms are not identical, the output waveform is a high one, which is indicated by a high level.

In summary, the source synchronous communication system provided by the invention can realize channel alignment by adopting the transmitting end.

The specific operation of the source synchronous communication system of the present invention may refer to the foregoing specific description of the transmitting end, and will not be repeated herein.

As another embodiment of the present invention, there is provided a delay calibration method applied to the aforementioned source synchronous communication system, as shown in fig. 11, the delay calibration method including:

s100, starting a delay calibration state machine, and setting an initial delay value of a sliding window circuit and an initial delay value of a numerical control delay unit;

s200, keeping the initial delay value of the sliding window circuit unchanged, controlling the delay calibration state machine to enter a bit timing state when the parallel sequence detector is determined to be in a first detection mode, and when the delay calibration state machine determines that the first calibration code is not matched with the first matching code according to error code information generated by the parallel sequence detector for the first calibration code in the bit timing state, adjusting the delay value of the numerical control delay unit until the first calibration code is determined to be matched with the first matching code according to the error code information generated by the parallel sequence detector for the first calibration code, keeping the matching result stable for a preset period, and determining the delay value corresponding to the numerical control delay unit as the first matching delay value; the parallel sequence detector is capable of generating a first matching code from the received first calibration code, and the parallel sequence generator is capable of generating the first calibration code in the bit timing state;

S300, maintaining the delay value of the numerical control delay unit at the first matching delay value, controlling the delay calibration state machine to enter a word timing state, when determining that the parallel sequence detector is in a second detection mode, determining that the second calibration code is not matched with the second matching code according to error code information generated by the parallel sequence detector for the second calibration code by the delay calibration state machine in the word timing state, adjusting the delay value of the sliding window circuit until the second calibration code is determined to be matched with the second matching code according to error code information generated by the parallel sequence detector for the second calibration code, maintaining a stable preset period of the matching result, and determining the delay value of the sliding window circuit as the second matching delay value; the parallel sequence detector is capable of generating a second matching code from the received second calibration code, the parallel sequence generator is capable of generating the second calibration code in the word timing state;

s400, controlling the source synchronous communication system to work by taking the delay value of the numerical control delay unit of the transmitting end as a first matched delay value and the delay value of the sliding window circuit as a second matched delay value, and controlling the delay calibration state machine to exit the bit timing state and the word timing state.

The delay calibration method provided by the invention is characterized in that a bit timing state is entered according to a first detection mode of a sequence detector of a receiving end, a word timing state is entered according to a second detection mode of the sequence detector of the receiving end, a delay value of the numerical control delay unit is adjusted according to first error code information output by the sequence detector of the receiving end in the bit timing state, and the delay value of the sliding window circuit is adjusted according to second error code information output by the sequence detector of the receiving end in the word timing state. When the delay calibration method is applied to a source synchronous communication system, the channel alignment can be completed through the bit timing and word timing processes when the digital control delay unit is positioned at the transmitting end, so that the delay calibration process of the digital control delay unit at the transmitting end is solved. In addition, the delay calibration method of the invention can realize the effect of bit-level delay calibration by transmitting error code information, and solves the influence of the delay of a receiving and transmitting channel on a state machine of a transmitting end.

As a specific embodiment, when the delay calibration state machine determines that the first calibration code does not match the first matching code according to the error code information generated by the parallel sequence detector for the first calibration code, adjusting the delay value of the numerical control delay unit until the first calibration code is determined to match the first matching code according to the error code information generated by the parallel sequence detector for the first calibration code, and the matching result keeps stable for a preset period, and determining the delay value corresponding to the numerical control delay unit at this time as the first matching delay value, including:

judging the level state of the first error code information;

In this embodiment, the first matching delay value of the numerical control delay unit is determined by determining the first error information returned by the parallel sequence detector.

It should be understood that the preset period may be specifically set as required, for example, may be 5 continuous periods, or the level states of the first error code information received in 10 continuous periods are all low levels, and then it may be determined that the delay value currently corresponding to the numerical control delay unit is the first matching delay value.

As another specific embodiment, when the delay calibration state machine in the word timing state determines that the second calibration code does not match the second matching code according to the error code information generated by the parallel sequence detector for the second calibration code, adjusting the delay value of the sliding window circuit until the second calibration code is determined to match the second matching code according to the error code information generated by the parallel sequence detector for the second calibration code and the matching result is kept stable for a preset period, and determining the delay value of the sliding window circuit at this time as the second matching delay value includes:

judging the level state of the second error code information;

In this embodiment, the second matching delay value of the numerical control delay unit is determined by determining the second error information returned by the parallel sequence detector.

Similarly, the preset period in this embodiment is also set as needed, and is not limited herein.

For the specific implementation of the delay calibration method of the present invention, reference may be made to the foregoing descriptions of the transmitting end and the source synchronous communication system, and details thereof are not repeated herein.

It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.

Claims

1. A transmitting terminal, comprising:

2. The transmitting terminal of claim 1, wherein the sliding window circuit comprises a sliding window delay unit connected in cascade in a plurality of stages,

3. The transmitting terminal of claim 1, wherein the digitally controlled delay unit comprises a coarse tuning circuit and a fine tuning circuit, an output terminal of the coarse tuning circuit is connected with an input terminal of the fine tuning circuit, an input terminal of the coarse tuning circuit is an input terminal of the digitally controlled delay unit, an output terminal of the fine tuning circuit is an output terminal of the digitally controlled delay unit,

，

wherein,representing a first granularity delay value,/for>Indicating the inherent delay value of the coarse tuning circuit,delay control code representing coarse tuning circuit, +.>A delay step value representing a coarse tuning circuit;

，

4. A transmitting terminal as defined in claim 3, wherein the coarse tuning circuit comprises a plurality of cascaded coarse tuning units, each of the coarse tuning units comprising a second data selector and a delay unit, each of the delay units having an input coupled to an output of a preceding stage of delay unit, a first input coupled to an output of a preceding stage of second data selector, and a second input coupled to an output of a same stage of delay unit, starting from the second coarse tuning unit;

5. The transmitting end of claim 1, wherein the parallel sequence generator comprises n cascaded D flip-flops for generating a PRBS code;

when n is 7, the PRBS code is a PRBS7 code, and the PRBS7 code is generated moreThe term is x ⁷ + x ⁶ +1, the parallel sequencer comprising 7 cascaded D flip-flops, the generator polynomial characterization: the output end of the sixth D trigger and the output end of the seventh D trigger are subjected to exclusive OR operation and then fed back to the first D trigger for circulation until the seventh D trigger outputs the PRBS7 code;

when n is 15, the PRBS code is PRBS15 code, and the generating polynomial of the PRBS15 code is x ¹⁵ + x ¹⁴ +1, the parallel sequencer comprising 15 cascaded D flip-flops, the generator polynomial being characterized: the output end of the fourteenth D trigger and the output end of the fifteenth D trigger are subjected to exclusive OR operation and then fed back to the first D trigger for circulation until the fifteenth D trigger outputs the PRBS15 code;

6. A source synchronous communication system, characterized by comprising a receiving end and a transmitting end as claimed in any one of claims 1 to 5, said transmitting end and receiving end being communicatively connected,

7. The source synchronous communication system according to claim 6, wherein the parallel sequence detector comprises a plurality of cascaded D flip-flops;

8. A delay calibration method for use in the source synchronous communication system of claim 6 or 7, the delay calibration method comprising:

9. The delay calibration method of claim 8, wherein when the delay calibration state machine determines that the first calibration code does not match the first matching code based on the error code information generated by the parallel sequence detector for the first calibration code, adjusting the delay value of the digitally controlled delay unit until the first calibration code is determined to match the first matching code based on the error code information generated by the parallel sequence detector for the first calibration code and the matching result remains stable for a preset period, determining the delay value corresponding to the digitally controlled delay unit at this time as the first matching delay value, comprising:

judging the level state of the first error code information;

10. The delay calibration method of claim 8, wherein the delay calibration state machine in the word timing state adjusts the delay value of the sliding window circuit when determining that the second calibration code does not match the second matching code based on the error code information generated by the parallel sequence detector for the second calibration code until determining that the second calibration code matches the second matching code based on the error code information generated by the parallel sequence detector for the second calibration code and the matching result remains stable for a preset period, and determining the delay value of the sliding window circuit at this time as the second matching delay value comprises:

Judging the level state of the second error code information;