CN117097330A - Delay self-calibration circuit, direct digital frequency synthesizer and delay self-calibration method - Google Patents
Delay self-calibration circuit, direct digital frequency synthesizer and delay self-calibration method Download PDFInfo
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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Abstract
The invention provides a delay self-calibration circuit, a direct digital frequency synthesizer and a delay self-calibration method, which are combined with a phase discriminator, a charge pump, a low-pass filter, an analog-to-digital converter, a coarse adjustment control unit, a coarse adjustment delay unit, a fine adjustment control unit and a fine adjustment delay unit to design the delay self-calibration circuit, so that delay or phase relation between a data signal and a sampling clock can be obtained, and delay between the data signal and the sampling clock can be automatically adjusted by combining coarse adjustment and fine adjustment according to actual requirements, even under various conditions such as process fluctuation, temperature fluctuation, clock change and the like, the delay or phase difference between the data signal and the sampling clock can be automatically and accurately adjusted through the delay self-calibration circuit, the phase difference between the data signal and the sampling clock can be locked at 50% of period, stable data can be accurately acquired in each sampling process, error code generation in high-speed data transmission is reduced, and clock working frequency is improved.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a delay self-calibration circuit, a direct digital frequency synthesizer, and a delay self-calibration method.
Background
With the progress of the development technology of society, the information throughput rate requires the water-logging boat to be high. In order to improve the highest working frequency, a multi-channel time-sharing alternating parallel technology is proposed, and a Numerical Control Oscillator (NCO) based on the technology can generate low-speed multi-channel digital sine wave signals with respectively lagged phases, then a high-speed digital signal is synthesized by multiple channels, and then the high-speed digital signal is converted into an analog signal to be output through a high-speed digital-to-analog converter (DAC). The time-sharing alternating direct digital frequency synthesis system reduces the speed requirement of the numerical control oscillator, but improves the complexity of the circuit, introduces more parasitic delay, needs to additionally increase an N-in-1 Multiplexer (MUX) and provide corresponding multiphase clocks, and meanwhile, the bottleneck of the system working speed is also transferred to a high-speed latch.
With further improvement of the working frequency, the period of the sampling clock is reduced, compared with gate level delay when each unit actually works, if the data and the sampling clock cannot meet a certain time sequence requirement, error codes can be generated in the data transmission process, and finally output waveform errors are caused.
In order to ensure the controllability of circuit sampling time, the prior art proposes a time sequence adjusting circuit based on a delay phase locking principle, which forms a feedback loop based on a phase locked loop, adjusts the delay between two input signals and obtains a desired fixed phase difference. However, for different clock frequencies, especially today's higher and higher sampling rates, the fixed phase difference between clocks cannot guarantee that the circuit is working at the optimal sampling position at any time, because the data link outside the loop, the units on the clock link, also introduce a certain delay and are affected by factors such as process fluctuations, temperature drift, clock variation, etc. This presents limitations in the prior art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an adjusting circuit for performing closed-loop, automatic and continuous tracking on the delay between data and sampling clock in a direct digital frequency synthesizer or digital-to-analog converter circuit, where the self-calibration circuit is based on a delay phase locking principle, and assists the main body part to work, so that the circuit can obtain an accurate phase relation between data and sampling clock under various conditions such as process fluctuation, temperature fluctuation, clock variation, etc., automatically adjust the delay between the two, meet the timing requirement of correct sampling, avoid error code generation, and facilitate the direct digital frequency synthesizer circuit to work at a higher clock frequency to obtain better high-speed performance.
In order to achieve the above object and other related objects, the present invention provides the following technical solutions.
A delay self-calibration circuit for adjusting a delay between a calibration data signal and a sampling clock, comprising:
the phase discriminator is used for receiving the data sampling signal and the clock sampling signal, comparing and outputting the phase difference of the data sampling signal and the clock sampling signal to obtain a first differential signal;
the charge pump stores and converts the first differential signal to obtain a second differential signal;
the low-pass filter performs charge and discharge processing under the control of the second differential signal to obtain a third differential signal;
the analog-to-digital converter is used for performing analog-to-digital conversion processing on the third differential signal to obtain a digital control code;
the coarse adjustment control unit carries out logic processing on the digital control code to obtain a clock inversion enabling signal and an N-bit coarse adjustment delay control code;
the coarse adjustment delay unit is used for receiving the clock inversion enabling signal, the sampling clock and the N-bit coarse adjustment delay control code, and adjusting the delay of the sampling clock under the control of the clock inversion enabling signal and the N-bit coarse adjustment delay control code to obtain a coarse adjustment sampling clock;
The fine adjustment control unit is used for converting the third differential signal to obtain a bias voltage;
the fine adjustment time delay unit is used for receiving the bias voltage and the coarse adjustment sampling clock, and adjusting the time delay of the coarse adjustment sampling clock under the control of the bias voltage to obtain a fine adjustment sampling clock;
wherein the data sampling signal is related to the data signal, the clock sampling signal is related to the sampling clock, the fine-tuning sampling clock is used for generating a multi-phase clock to control the phase of the data signal, and N is an integer greater than or equal to 2.
Optionally, the delay self-calibration circuit further includes a divide-by-two divider, the sampling clock is buffered and delayed and then input into the divide-by-two divider, and the divide-by-two divider outputs the clock sampling signal.
Optionally, the phase detector comprises an exclusive or gate.
Optionally, the coarse adjustment delay unit includes an exclusive-or gate and N-stage cascaded coarse adjustment delay subunit, a first input end of the exclusive-or gate is connected with the sampling clock, a second input end of the exclusive-or gate is connected with the clock inversion enabling signal, an output end of the exclusive-or gate is connected with an input end of the 1 st-stage coarse adjustment delay subunit, an input end of the i+1st-stage coarse adjustment delay subunit is connected with an output end of the i-th-stage coarse adjustment delay subunit, an output end of the N-th-stage coarse adjustment delay subunit outputs the coarse adjustment sampling clock, and a control end of the N-stage coarse adjustment delay subunit is connected with the N-bit coarse adjustment delay control code in a one-to-one correspondence manner, wherein i is an integer of 1 to N-1.
Optionally, the coarse adjustment delay subunit includes two multiplexers and a delay structure, a first input end of the two multiplexers is connected with an input end of the delay structure, an output end of the delay structure is connected with a second input end of the two multiplexers, a control end of the two multiplexers is connected with the coarse adjustment delay control code, a first input end of the two multiplexers is used as an input end of the coarse adjustment delay subunit, an output end of the two multiplexers is used as an output end of the coarse adjustment delay subunit, and a control end of the two multiplexers is used as a control end of the coarse adjustment delay subunit.
Optionally, in the coarse-tuning delay sub-unit of the j-th stage, the delay structure includes 2 (j-1) And the inverters are cascaded in sequence, wherein j is an integer from 1 to N.
Optionally, the fine adjustment control unit includes an operational amplifier, a PMOS tube and an NMOS tube, where an in-phase input end of the operational amplifier and an opposite-phase input end of the operational amplifier are respectively connected to two differential ends of the third differential signal, a source electrode of the PMOS tube is connected to a power supply voltage, an output end of the operational amplifier is connected to a gate electrode of the PMOS tube, a drain electrode of the PMOS tube is connected to a drain electrode of the NMOS tube, a gate electrode of the NMOS tube is connected to a drain electrode of the NMOS tube, a source electrode of the NMOS tube is grounded, and a gate electrode of the NMOS tube outputs the bias voltage.
Optionally, the fine adjustment delay unit includes a current mode inverter with S stages cascaded in turn, an input end of the current mode inverter with 1 st stage is connected to the coarse adjustment sampling clock, an input end of the current mode inverter with k-1 st stage is connected to an output end of the current mode inverter, an output end of the current mode inverter with S stage outputs the fine adjustment sampling clock, and the bias voltage is used as a tail current bias voltage of each stage of the current mode inverter, where S is an integer greater than or equal to 2, and k is an integer from 2 to S.
A direct digital frequency synthesizer, comprising:
the digital control oscillator generates digital sine wave signals with multiple paths of lagged phases respectively according to the data signals;
the X+1 multiplexers are arranged in parallel, the input ends of the X multiplexers are connected with the digital sine wave signals in a one-to-one correspondence manner, the input ends of one multiplexer receive preset binary codes, and the control ends of the multiplexers are respectively connected with multiphase clock signals;
the input ends of the x latches are connected with the output ends of the x multiplexers for receiving the digital sine wave signals in a one-to-one correspondence manner;
The input end of the digital-to-analog converter is connected with the output end of each latch, and analog signals are output;
the clock frequency division module generates the sampling clock according to a system clock;
the input end of the first buffer is connected with the sampling clock, and the output end of the first buffer is connected with the clock control end of each latch;
the input end of the second buffer is connected with the sampling clock;
the delay self-calibration circuit according to any one of claims 2 to 8, wherein the delay self-calibration circuit is respectively connected to an output end of the second buffer, an output end of the multiplexer receiving the preset binary code, and an output end of the clock frequency division module, and obtains and outputs the fine-tuning sampling clock;
the multiphase clock generation module is used for generating the multiphase clock signal according to the fine-tuning sampling clock;
wherein x is an integer greater than or equal to 2.
A delay self-calibration method applied to any one of the above delay self-calibration circuits, comprising:
closing the fine adjustment control unit, enabling the coarse adjustment control unit to generate N bits of the coarse adjustment delay control code, adjusting by the coarse adjustment control unit, finding out and keeping the N bits of the coarse adjustment delay control code which enable the digital control code to be close to a 1/2 range based on adjustment feedback of the coarse adjustment control unit, so that the phase difference between the data sampling signal and the clock sampling signal is close to-Ts/2;
The coarse adjustment control unit is kept, the fine adjustment control unit is enabled to be combined with the coarse adjustment control unit and the fine adjustment control unit to perform adjustment, and the phase difference between the data sampling signal and the clock sampling signal is further close to-Ts/2 through adjustment feedback of the fine adjustment control unit;
wherein Ts is the period of the sampling clock.
As described above, the delay self-calibration circuit, the direct digital frequency synthesizer and the delay self-calibration method provided by the invention have at least the following beneficial effects:
the delay self-calibration circuit is designed by combining a structure of a phase discriminator, a charge pump, a low-pass filter, an analog-to-digital converter, a coarse adjustment control unit, a coarse adjustment delay unit, a fine adjustment control unit and a fine adjustment delay unit, so that delay calibration adjustment of closed-loop tracking based on a delay phase locking principle is formed, delay or phase relation between a data signal and a sampling clock can be obtained, and delay between the data signal and the sampling clock can be automatically adjusted by combining coarse adjustment and fine adjustment according to actual requirements, even under various conditions such as process fluctuation, temperature fluctuation, clock change and the like, delay or phase difference between a data signal and a sampling clock can be automatically and accurately adjusted through the delay self-calibration circuit, the timing requirement of correct sampling is met, sampling error code generation is avoided, and the direct digital frequency synthesizer circuit is beneficial to work under higher clock frequency to obtain better high-speed performance when the direct digital frequency synthesizer circuit is applied to a direct digital frequency synthesizer.
Drawings
Fig. 1 shows a schematic diagram of the correct sampling timing.
FIG. 2 is a schematic diagram of an erroneous sampling timing.
Fig. 3 is a block diagram showing a structure of a sampling timing adjustment circuit in the prior art.
Fig. 4 is a block diagram showing the structure of the delay self-calibration circuit in the present invention.
Fig. 5 is a schematic diagram showing the input-output relationship of the phase detector in fig. 4.
Fig. 6 is a schematic diagram showing the conversion relationship between the input phase difference and the duty cycle and the output voltage of the charge pump in fig. 4.
Fig. 7 shows a circuit diagram of the coarse-tuning delay unit of fig. 4.
Fig. 8 is a circuit diagram of the fine adjustment control unit and the fine adjustment delay unit in fig. 4.
Fig. 9 is a block diagram of a direct digital frequency synthesizer according to the present invention.
Fig. 10 is a circuit diagram of a direct digital frequency synthesizer according to the present invention.
Fig. 11 is a schematic diagram of waveforms of the data domain and clock domain of the direct digital frequency synthesizer according to the present invention.
Fig. 12 is a schematic diagram of a calibration feedback loop locking process of the delay self-calibration circuit of the present invention.
Fig. 13 shows a flow chart of the coarse tuning process algorithm of the delay self-calibration circuit in the invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 13. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex. The structures, proportions, sizes, etc. shown in the drawings attached hereto are for illustration purposes only and are not intended to limit the scope of the invention, which is defined by the claims, but rather by the claims.
As described in the foregoing background, the inventors have studied and found that existing time-sharing alternating direct digital frequency synthesis systems reduce the speed requirement of a digitally controlled oscillator, but increase the complexity of the circuit, introduce more parasitic delay, require additional N-1 Multiplexers (MUX), provide corresponding multiphase clocks, and shift the bottleneck of the system operating speed to high-speed latches. With further improvement of the working frequency, the period of the sampling clock is reduced, compared with gate level delay when each unit actually works, if the data and the sampling clock cannot meet a certain time sequence requirement, error codes can be generated in the data transmission process, and finally output waveform errors are caused.
Ideally, taking rising edge sampling as an example, sampling in a phase with more stable data can ensure that no error occurs, as shown in fig. 1, each rising edge corresponds to a stable phase of data D <0> to D <7>, and at this time, sampling does not occur with errors and error codes are generated; if sampling is performed during the data change phase, the accuracy of sampling cannot be guaranteed, and as shown in fig. 2, each rising edge corresponds to the change phase of data D <0> to D <7>, and sampling is prone to error and error code.
In order to ensure the controllability of circuit sampling time, the prior art proposes a time sequence adjusting circuit based on a delay phase locking principle, which forms a feedback loop based on a phase locked loop, adjusts the delay between two input signals through a fixed delay circuit to obtain a desired fixed phase difference, and as shown in fig. 3, an input clock and an output clock are locked at a fixed phase difference through a delay phase locked loop, so that the time for establishing and maintaining a data sampling process can be met. However, for different clock frequencies, especially today with higher and higher sampling rates, the fixed phase difference between clocks cannot guarantee that the circuit is working at the optimal sampling position at any time, because the data link outside the loop, the units on the clock link, etc. also introduce a certain delay and are affected by factors such as process fluctuation, temperature drift, clock variation, etc., so that the real-time phase difference between the data and the sampling clock fluctuates, and sampling errors and bit errors may still occur. This presents limitations in the prior art.
Based on the above, the invention provides a delay automatic calibration and adjustment technical scheme based on delay phase locking: the delay self-calibration circuit is designed by combining a phase discriminator, a charge pump, a low-pass filter, an analog-to-digital converter, a coarse adjustment control unit, a coarse adjustment delay unit, a fine adjustment control unit and a fine adjustment delay unit, so that a delay calibration adjustment loop based on a delay phase locking principle is formed, on the basis of acquiring the delay or phase relation between a data signal and a sampling clock, the delay between the data signal and the sampling clock can be adjusted by combining coarse adjustment and fine adjustment according to actual requirements, and even under various conditions such as process fluctuation, temperature fluctuation, clock change and the like, the delay or phase difference between the data signal and the sampling clock can be automatically and accurately adjusted through the delay self-calibration circuit, the time sequence requirement of correct sampling is met, and sampling error code is avoided.
In detail, the present invention proposes a delay self-calibration circuit for adjusting the delay between a calibration data signal and a sampling clock CLK1, as shown in fig. 4, which at least includes:
the phase discriminator PD receives the data sampling signal fd 'and the clock sampling signal fs', compares and outputs the phase difference of the data sampling signal fd 'and the clock sampling signal fs', and obtains a first differential signal V1;
The charge pump stores and converts the first differential signal V1 to obtain a second differential signal V2;
the low-pass filter performs charge and discharge treatment under the control of the second differential signal V2 to obtain a third differential signal V3;
an analog-to-digital converter ADC performs analog-to-digital conversion processing on the third differential signal V3 to obtain a digital control code S < M-1:0> with M bits;
the coarse adjustment control unit performs logic processing on the digital control code S < M-1:0> to obtain a clock inversion enabling signal R (i.e. not shown in fig. 4) and an N-bit coarse adjustment delay control code DTW < N-1:0>;
the coarse adjustment delay unit is used for receiving a clock inversion enabling signal R, a sampling clock CLK1 and an N-bit coarse adjustment delay control code DTW < N-1:0>, and adjusting the delay of the sampling clock CLK1 under the control of the clock inversion enabling signal R and the N-bit coarse adjustment delay control code DTW < N-1:0 so as to obtain a coarse adjustment sampling clock CLK2;
the fine adjustment control unit is used for performing conversion processing on the third differential signal V3 to obtain a bias voltage Vbias;
the fine adjustment delay unit receives the bias voltage Vbias and the coarse adjustment sampling clock CLK2, and adjusts the delay of the coarse adjustment sampling clock CLK2 under the control of the bias voltage Vbias to obtain a fine adjustment sampling clock CLK3;
Wherein the data sampling signal fd 'is related to the data signal, the clock sampling signal fs' is related to the sampling clock CLK1, and the fine sampling clock CLK3 is used for generating a multiphase clock to control the phase of the data signal, and M, N is an integer greater than or equal to 2, respectively.
In detail, as shown in fig. 4, the delay self-calibration circuit further includes a divide-by-two divider, and the clock (frequency) fs of the sampling clock CLK1 is buffered and delayed and then input to the divide-by-two divider, and the divide-by-two divider outputs a clock sampling signal fs'.
In detail, as shown in fig. 4, the phase detector PD includes an exclusive or gate, and the data sampling signal fd 'and the clock sampling signal fs' are input to the phase detector PD formed of one exclusive or gate. The exclusive-OR gate is characterized in that: when one of the two inputs is '1' and the other is '0', outputting '1'; when the two inputs are both 0 or 1, a 0 is output. This characteristic causes the duty cycle of the output signal to be linearly dependent on the phase difference of the input signal when two signals of the same frequency and different phases are input to the exclusive-or gate, as shown in fig. 5, assuming that the period of the system clock sys_clk is T S The period of the data sampling signal fd 'and the clock sampling signal fs' is 2T S When the input phase difference increases from 0, the duty ratio of the output signal of the phase detector PD changes linearly from 0% to 100%, and then from 100% to 0%, so that it repeats with a period of 2 Ts.
The duty cycle of the output of the phase detector PD (i.e., the first differential signal V1) contains phase difference information, and is converted into a voltage signal (i.e., the third differential signal V3) by a Charge Pump (CP) and a Low Pass Filter (LPF). The phase detector and charge pump connections have different polarities, for example the connection polarities shown in fig. 4. The output of the phase detector PD is connected to the charge pump CP to control the charge and discharge of the low-pass filter at the output end, when the duty ratio is higher than 50%, the charge pump CP charges more VP at the output end, when the duty ratio is lower than 50%, the charge pump CP charges more VM at the output end, when the duty ratio is equal to 50%, the voltages at the VP and VM nodes will be equal, so that the duty ratio information varying from 0 to 100% is converted into a differential voltage signal, and in combination with fig. 5, a schematic diagram of the conversion relationship between the input phase difference-duty ratio-charge pump output voltage is obtained as shown in fig. 6, and the characteristic curve is repeated with a period of 2Ts due to the periodicity of the phase detector PD. If the polarity of the connection of the phase detector and the charge pump is reversed from that of fig. 4, the charge and discharge to the VP and VM nodes are reversed from that described above.
In detail, as shown in fig. 4, the differential output VP-VM of the charge pump CP passing through the low-pass filter simultaneously controls the coarse adjustment control unit and the fine adjustment control unit in the calibration circuit through two different paths, which respectively control the coarse adjustment delay unit and the fine adjustment delay unit. The coarse adjustment delay unit is controlled by discrete digital code values, so that the VP-VM is first converted into a digital control code S < M-1:0> with M bits by an analog-to-digital converter ADC, so as to satisfy the maximum dynamic range, where S < M-1:0> is equal to 1/2 of the range (i.e., 10 … binary), when vp=vm, and then input into the coarse adjustment control unit, the coarse adjustment control unit performs logic processing on the digital control code S < M-1:0>, to obtain a clock inversion enable signal R (i.e., not shown in fig. 4) and an N-bit coarse adjustment delay control code DTW < N-1:0>. The fine adjustment delay unit is directly controlled by continuous analog voltage.
In detail, in an alternative embodiment of the present invention, as shown in fig. 7, the coarse adjustment delay unit includes an exclusive-or gate and N-stage coarse adjustment delay subunits that are sequentially cascaded, where a first input end of the exclusive-or gate is connected to the sampling clock CLK1, a second input end of the exclusive-or gate is connected to the clock inversion enable signal R, an output end of the exclusive-or gate is connected to an input end of the 1 st-stage coarse adjustment delay subunit, an input end of the i+1-th-stage coarse adjustment delay subunit is connected to an output end of the i-th-stage coarse adjustment delay subunit, an output end of the N-th-stage coarse adjustment delay subunit outputs a coarse adjustment sampling clock CLK2, and a control end of the N-stage coarse adjustment delay subunit is connected to the N-bit coarse adjustment delay control code DTW < N-1:0> in a one-to-one correspondence manner, where i is an integer from 1 to N-1.
In more detail, as shown in FIG. 7The j-th level coarse-adjustment delay subunit comprises two multiplexer MUXs and a delay structure, wherein a first input end of the two multiplexer MUXs is connected with an input end of the delay structure, an output end of the delay structure is connected with a second input end of the two multiplexer MUXs, and a control end of the two multiplexer MUXs is connected with a coarse-adjustment delay control code DTW<j-1>The first input end of the two-way multiplexer MUX is used as the input end of the coarse adjustment delay subunit, the output end of the two-way multiplexer MUX is used as the output end of the coarse adjustment delay subunit, and the control end of the two-way multiplexer MUX is used as the control end of the coarse adjustment delay subunit. In the j-th level coarse-tuning delay subunit, the delay structure includes 2 (j-1) And the inverters are cascaded in sequence, wherein j is an integer from 1 to N.
In more detail, as shown in FIG. 7, the delay structure in each level of coarse-tuning delay subunits is different, different numbers of inverter chains form each level of delay units, and the first level of delay is generally composed of 1 inverter, when the coarse-tuning delay control code DTW<0>If the delay is 1, the 1 st level coarse-adjustment delay subunit selects the output waveform of the first level delay as output through the two multiplexers MUX in the 1 st level coarse-adjustment delay subunit, and when the coarse-adjustment delay control code DTW<0>When the input waveform is 0, the 1 st level coarse-adjustment delay subunit selects the input waveform which is not delayed as output through two multiplexers MUXs in the 1 st level coarse-adjustment delay subunit; the second delay consists of 2 inverters, the third delay consists of 4 inverters, … … and the nth delay consists of 2 (N-1) And an inverter, and so on. Coarse-adjustment delay control code DTW<N-1:0>The code value of (2) determines the delay of the coarse sample clock CLK2 compared to the sample clock CLK 1. When the clock inversion enable signal r= "1", the input sampling clock CLK1 may be inverted, with the effect equivalent to delaying the clock period of the sampling clock CLK1 by half.
In detail, in an alternative embodiment of the present invention, as shown in fig. 8, the fine adjustment control unit includes an operational amplifier, a PMOS transistor P1 and an NMOS transistor M1, wherein a non-inverting input end (connected to a voltage VP) of the operational amplifier and an inverting input end (connected to a voltage VM) of the operational amplifier are respectively connected to two differential ends of the third differential signal, a source electrode of the PMOS transistor P1 is connected to a power supply voltage, an output end of the operational amplifier is connected to a gate electrode of the PMOS transistor P1, a drain electrode of the PMOS transistor P1 is connected to a drain electrode of the NMOS transistor M1, a gate electrode of the NMOS transistor M1 is connected to a drain electrode of the NMOS transistor M1, a source electrode of the NMOS transistor M1 is grounded, and a gate electrode of the NMOS transistor M1 outputs a bias voltage Vbias.
In detail, as shown in fig. 8, the fine adjustment delay unit includes S stages of current-mode inverters sequentially cascaded, an input terminal of the 1 st stage of current-mode inverter is connected to a coarse adjustment sampling clock CLK2, an input terminal of the k stage of current-mode inverter is connected to an output terminal of the k-1 st stage of current-mode inverter, an output terminal of the S stage of current-mode inverter outputs a fine adjustment sampling clock CLK3, and a bias voltage Vbias is used as a tail current bias voltage of each stage of current-mode inverter, where S is an integer greater than or equal to 2, and k is an integer from 2 to S.
In more detail, as shown in fig. 8, the voltage VP and the voltage VM form a third differential signal V3 outputted after the low-pass filtering, the differential signal V is converted into a single end by the operational amplifier, and then converted into a bias current by the PMOS transistor P1, and the bias current flows through the diode-connected NMOS transistor M1, and the gate voltage of the NMOS transistor M1 is used for providing the tail current bias voltage of the current-mode inverter. When VP-VM increases, the bias voltage Vbias decreases, the inverter tail current decreases, and the delay of the inverter increases, such that the delay of the fine sample clock CLK3 relative to the coarse sample clock CLK2 increases.
Based on the above delay self-calibration circuit, the present invention also provides a direct digital frequency synthesizer, as shown in fig. 9-10, comprising:
The digital control oscillator NCO generates a plurality of paths of digital sine wave signals with respectively lagged phases according to the DATA signal DATA;
the multiplexer MUX, x+1 multiplexers (namely multiplexer MUX_0-MUX_x) are arranged in parallel, each input end of the x multiplexers (namely multiplexer MUX_1-MUX_x) is connected with each digital sine wave signal in a one-to-one correspondence manner, each input end of one multiplexer (namely multiplexer MUX_0) receives a preset binary code, and each control end of each multiplexer is connected with a multiphase clock signal;
the input ends of the x latches LATCH are connected with the output ends of x multiplexers (namely multiplexers MUX_1-MUX_x) for receiving the digital sine wave signals in a one-to-one correspondence manner;
the input end of the digital-to-analog converter DAC is connected with the output end of each LATCH LATCH, and an analog signal IOUT is output;
the clock frequency division module generates a sampling clock CLK1 according to the system clock, and the corresponding clock frequency is fs;
the input end of the first buffer is connected with the sampling clock CLK1, and the output end of the first buffer is connected with the clock control end of each LATCH;
a second buffer, the input end of which is connected with the sampling clock CLK1;
the delay self-calibration circuit is respectively connected with the output end of the second buffer, the output end of the multiplexer for receiving the preset binary code and the output end of the clock frequency division module to obtain and output a fine-tuning sampling clock CLK3;
The multiphase clock generation module generates multiphase clock signals according to the fine sampling clock CLK 3;
wherein x is an integer greater than or equal to 2.
In detail, as shown in fig. 9 to 10, the multiplexed data in the conventional time-sharing alternating direct digital frequency synthesis system is combined into one path of high-speed data through the multiplexer MUX and is latched by the sampling clock fs in the LATCH. In the direct digital frequency synthesizer, besides the common data, a path of waveform fd 'with the same frequency and the same time delay as the data is generated through a multiplexer MUX_0 and is used as the input of a self-calibration loop together with a sampling clock fs, and the waveform fd' and the sampling clock fs are processed by a delay self-calibration circuit to generate a control signal to adjust the delay of a multiphase clock signal, so that the phase of the data and the sampling clock is adjusted, and a new control signal is generated after the phase is changed, thus forming a closed loop feedback loop.
In more detail, as shown in fig. 9-10, in an alternative embodiment of the present invention, taking 8 channels as an example, the multiplexers mux_1 to mux_x are set as 8-in-1 multiplexers, the 8 low-speed signals are synthesized into 1-way high-speed data signal SDATA under the control of 8-phase clock, LATCH is performed by LATCH, the fs frequency is the system clock (sys_clk) frequency, the period is assumed to be Ts, and the process is the highest speed in the direct digital frequency synthesis system, so that timing errors are more likely to occur and thus the delay between the high-speed data signals SDATA and fs needs to be calibrated.
In addition to the normal data path, there is an additional multiplexer mux_0, which is mainly used to generate the waveform of the data sampling signal fd' aligned with the waveform of the high-speed data signal SDATA, by: the inputs of the multiplexers mux_1 to mux_x are respectively connected to 8 input data channels chanel_1 to chanel_8, and the input of the multiplexer mux_0 is connected to the preset binary code 10101010, besides, the multiplexers mux_0 and mux_1 to mux_x adopt the same structure, layout and clock delay, so that the waveform (i.e. the data sampling signal) fd' generated by the multiplexer mux_0 is completely aligned with the variation edge of the normal synthesized high-speed data signal SDATA, and the apparent period is 2Ts, and the waveform relationship is shown in fig. 11 (a). Fd' may thus indirectly but accurately represent the phase characteristics of the data and thus serve as one of the input signals to the delay calibration circuit. The 8-phase clocks of all the multiplexer muxes come from one multiphase clock generation module, the input clock of the multiphase clock generation module is provided by a fine-tuning sampling clock CLK3 output by the delay self-calibration circuit, and the source comes from the distribution of the system-on-chip clock, but the two-stage delay of the delay self-calibration circuit is performed in the middle. The total delay is determined by a coarse adjustment delay unit and a fine adjustment delay unit, and the coarse adjustment delay unit and the fine adjustment delay unit are regulated and controlled by the self-calibration circuit realized by the invention. The delay of the fine sampling clock CLK3 is adjusted to adjust the delay of the high-speed data signal SDATA with respect to the sampling clock fs.
The system clock (SYS_CLK) is supplied to a frequency divider through the same buffer in addition to the main sampling clock fs supplied to the LATCH array, and the same frequency divider and the high-speed latches DFF_1 to DFF_x in the data path are designed and clocked in the same manner so that the frequency-divided waveform fs' generated by the frequency divider represents the phase characteristics of the real sampling clock fs and has a period of 2T S The waveform relationship is shown in fig. 11 (b). Thus, fs' may indirectly but accurately characterize the phase of the sampling clock as another input to the delay self-calibration circuit. The delay self-calibration circuit takes fs' as a reference signal and is used for relatively adjusting the sampling clock CLK3The delay of the sampling clock CLK1 is calibrated, and the delay of the high-speed data signal SDATA relative to the sampling clock CLK1 (or fs) is adaptively adjusted to meet the timing requirements under various conditions such as process fluctuation, temperature fluctuation, clock variation, and the like.
The main task of the delay self-calibration circuit in this design is to adjust the phase difference between the high-speed data signal SDATA and the sampling clock fs in fig. 11, i.e., τd- τs, so that the rising edge (or falling edge) of the clock, i.e., the sampling time, is in the period of stable data waveform, and it is necessary to avoid that the rising edge (or falling edge) of the clock is exactly in the period of stable data waveform.
In more detail, the delay self-calibration process of the delay self-calibration circuit as shown in fig. 4 or 10 is divided into a coarse adjustment process and a fine adjustment process, and the detailed workflow is as follows:
(1) When the calibration starts, firstly, a coarse adjustment process is carried out, and the fine adjustment control unit is temporarily inactive. The differential output VP-VM of the charge pump is converted into a digital control code S < M-1:0> with M bits through an analog-to-digital converter ADC with differential input, so that the subsequent digital circuit can conveniently process the digital control code S < M-1:0 >.
(2) The digital control code S < M-1:0> generated by the analog-to-digital converter ADC is input into the coarse adjustment control unit, and the module is responsible for detecting and processing the digital control code S < M-1:0> generated by the analog-to-digital converter ADC and generating N-bit coarse adjustment delay control code DTW < N-1:0> and clock inversion enabling signal R, and different coarse adjustment delay control codes and clock inversion enabling signals R enable the coarse adjustment delay unit to generate different delay times.
(3) The coarse-tuning control unit first generates 0 to 2 N -1 varying coarse-tuning delay control codes DTW, each of the coarse-tuning delay control codes DTW of different code values generating a data sample signal fd ' of different delays and also generating a phase difference of the different data sample signal fd ' from the clock sample signal fs ', the phase difference being passed through a phase detector PD, a charge pump CP, a low-pass filter LPF, an analog-to-digital converter ADC loop and finally being reflected to the digital control code S output by the analog-to-digital converter ADC <M-1:0>On the other hand, each coarse-tuning delay control code DTW corresponds to an ADC outputAnd outputting a digital control code S.
(4) Coarse tuning control unit scans 0 to 2 N The coarse-tuning delay control code DTW of the-1 variation, and the most desirable result is the point where the phase difference τd-Ts of the data sampling signal fd 'and the clock sampling signal fs' is equal to |ts/2|, i.e. the point where the phase detector output duty cycle is equal to 50%, or the charge pump output voltage VP-vm≡0, because the clock sampling instant is in the middle of the data being most stable, as shown in fig. 1. At this time, the digital control code S output by the ADC<M-1:0>At 1/2 scale (i.e., binary 10 … 000). Since the coarse-tuning process is discrete, the coarse-tuning control unit eventually only needs to select and hold a coarse-tuning delay control code DTW closest to the point, and the coarse-tuning process ends.
(5) After the coarse adjustment control unit finds a coarse adjustment delay control code DTW close to 50% duty ratio through a certain algorithm, the point is used as an initial point of a fine adjustment process, so that the fine adjustment control unit is enabled, and the implementation method is as shown in fig. 8, after the output VP-VM of the charge pump is subjected to differential to single end operation, the tail current of the inverter chain is controlled through bias voltage Vbias, and the larger the VP-VM is, the smaller the tail current is, the charging and discharging speed of the inverter is reduced, and the total delay D of the inverter chain is larger; conversely, the smaller the VP-VM, the smaller the overall delay D of the fine-tuning delay unit. At this time, the signal flows through the fine adjustment delay unit, the external multiphase clock generation module, the multiplexer mux_0, the phase discriminator, the charge pump, the low-pass filter, the fine adjustment control unit and is fed back to the fine adjustment delay unit, so that a feedback loop is formed, and therefore, the fine adjustment process is a closed loop feedback process.
(6) The fine-tuning feedback adjustment process eventually stabilizes in a state where the phase difference τd- τs of the data sample signal fd 'and the clock sample signal fs' is almost equal to |ts/2|, i.e. the duty cycle of the phase detector PD output is almost equal to 50% and the charge pump output voltage VP-vm≡0. The detailed principle of this feedback is as follows:
a. because of the phase discrimination characteristics of the exclusive or gate phase discriminator, two points of 50% duty cycle found by the coarse adjustment circuit in step (4) may exist in one period of-Ts to Ts, such as two points A, B in fig. 6, and both points may be initial points of the fine adjustment process. Since the transmission characteristic curves at these two points are opposite in polarity, there must be both positive and negative feedback cases in the delay calibration feedback loop.
b. If the initial point of fine adjustment is near the point A, analyzing the feedback polarity of the line segment where the point A is located: assuming that τd increases, the duty cycle decreases and VP-VM decreases, and the total delay D of the fine-tuning delay unit in FIG. 4 decreases, i.e., τd decreases, so that the delay calibration loop is negative feedback in the range of-Ts to 0. Even if the initial point set for the fine adjustment process at the end of the coarse adjustment process in step (4) is not exactly equal to the point a of 50% duty ratio, as long as the phase difference is within the range of-Ts to 0, the polarity of the feedback is unchanged, and meanwhile, due to the high gain of the differential-to-single-ended operational amplifier in fig. 8, the stable points VP-VM are necessarily approximately equal, and the loop is always stable near the point a or a very small range of the point a due to the negative feedback action. A schematic of the operation is shown in fig. 12.
c. If the fine adjustment initial point is point B, analyzing the feedback polarity of point B: assuming that τd increases, the duty cycle increases, VP-VM increases, the total delay D of the fine-tuning delay unit in FIG. 4 increases, causing τd to further increase, and the same applies when τd decreases. Therefore, the delay calibration loop is positive feedback in the range of the point B and the phase difference of 0 to Ts. The self-calibration circuit does not stabilize within the range of 0 to TS, but deviates from and enters the range of nTs to (n+1) TS, (n= ±1), and eventually stabilizes, but the duty ratio is not equal to 50% at this time, and thus is not the optimal stabilization point for the sampling process.
(7) In order to locate the fine adjustment initial point near the point A, a certain algorithm judgment can be added in the course of coarse adjustment. Scanning 0 to 2 during coarse adjustment N During the course of the coarse-tuning delay control code DTW of-1 variation, a digital control code S generated by the analog-to-digital converter ADC is added<M-1:0>When detecting the digital control code S<M-1:0>When traversing 10 … words from large to small, namely, the point corresponding to the coarse adjustment delay control code DTW at the moment is considered to be near the point A, the coarse adjustment control unit can immediately finish the coarse adjustment process and keep the coarse adjustment delay control code DTW at the moment, otherwise, the coarse adjustment delay control code DTW is continuously increased The code value of the delay control code DTW is adjusted and so on until the coarse adjustment delay control code DTW reaches a maximum value. The algorithm flow diagram is shown in fig. 13 (m=n=8 bits for example). Conversely, if the feedback polarity of the implemented circuit is opposite to the example in fig. 4, the digital control code S should be detected<M-1:0>The time of traversing 10 … codewords from small to large.
(8) After the phase difference of the circuit is stabilized near the point A, the rising edge of the sampling clock and the changing edge of the data are just different by 50% of the phase difference, and the phase difference is tracked in real time through negative feedback, so that even if the circuit is influenced by factors such as temperature drift, mechanical stress, process deviation, clock frequency change and the like, the feedback loop continuously operates, the time sequence relationship between the data and the clock is as shown in fig. 11, and the sampling time is kept at the middle section of the data stability, so that good time sequence can be ensured.
The above is the working process of the data and sampling clock delay self-calibration circuit realized by the invention.
Based on the delay self-calibration circuit, the invention also provides a delay self-calibration method which is applied to the delay self-calibration circuit and comprises the following steps:
s1, closing a fine adjustment control unit, enabling the coarse adjustment control unit to generate an N-bit coarse adjustment delay control code DTW < N-1:0>, adjusting by the coarse adjustment control unit, and finding out the N-bit coarse adjustment delay control code DTW < N-1:0> which enables the digital control code S < M-1:0> to be close to a 1/2 range based on adjustment feedback of the coarse adjustment control unit and keeping the digital control code DTW < N-1:0>, so that the phase difference between a data sampling signal fd 'and a clock sampling signal fs' is close to-Ts/2;
S2, maintaining the coarse adjustment control unit, enabling the fine adjustment control unit, combining the coarse adjustment control unit and the fine adjustment control unit for adjustment, and enabling the phase difference between the data sampling signal fd 'and the clock sampling signal fs' to be further close to-Ts/2 through adjustment feedback of the fine adjustment control unit;
where Ts is the period of the sampling clock CLK 1.
In summary, in the delay self-calibration circuit, the direct digital frequency synthesizer and the delay self-calibration method provided by the invention, the delay self-calibration circuit is designed by combining the structures of the phase discriminator, the charge pump, the low-pass filter, the analog-to-digital converter, the coarse adjustment control unit, the coarse adjustment delay unit, the fine adjustment control unit and the fine adjustment delay unit, so that the delay calibration adjustment of closed-loop tracking based on the delay phase locking principle is formed, the delay or phase relation between a data signal and a sampling clock can be obtained, the delay between the two can be automatically adjusted by combining coarse adjustment and fine adjustment according to actual requirements, the initial point of a delay control digital code setting calibration loop can be automatically generated, the delay between the sampling clock edge and the data change edge is locked at 50% of the period, and even under various conditions such as process fluctuation, temperature fluctuation, clock change and the like, the delay or phase difference between the data signal and the sampling clock can be automatically and accurately adjusted by the delay self-calibration circuit, the phase difference between the two is locked at 50% of the period, the accurate acquisition of stable data in each sampling process can be ensured, the error code generation in high-speed data transmission can be reduced, the generation of the error code can be improved, the working frequency can be directly obtained, and the direct digital frequency synthesizer can be better in the frequency can work at the frequency, and the direct digital frequency can work be better.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A delay self-calibration circuit for adjusting a delay between a calibration data signal and a sampling clock, comprising:
the phase discriminator is used for receiving the data sampling signal and the clock sampling signal, comparing and outputting the phase difference of the data sampling signal and the clock sampling signal to obtain a first differential signal;
the charge pump stores and converts the first differential signal to obtain a second differential signal;
the low-pass filter performs charge and discharge processing under the control of the second differential signal to obtain a third differential signal;
the analog-to-digital converter is used for performing analog-to-digital conversion processing on the third differential signal to obtain a digital control code;
the coarse adjustment control unit carries out logic processing on the digital control code to obtain a clock inversion enabling signal and an N-bit coarse adjustment delay control code;
The coarse adjustment delay unit is used for receiving the clock inversion enabling signal, the sampling clock and the N-bit coarse adjustment delay control code, and adjusting the delay of the sampling clock under the control of the clock inversion enabling signal and the N-bit coarse adjustment delay control code to obtain a coarse adjustment sampling clock;
the fine adjustment control unit is used for converting the third differential signal to obtain a bias voltage;
the fine adjustment time delay unit is used for receiving the bias voltage and the coarse adjustment sampling clock, and adjusting the time delay of the coarse adjustment sampling clock under the control of the bias voltage to obtain a fine adjustment sampling clock;
wherein the data sampling signal is related to the data signal, the clock sampling signal is related to the sampling clock, the fine-tuning sampling clock is used for generating a multi-phase clock to control the phase of the data signal, and N is an integer greater than or equal to 2.
2. The delay self-calibration circuit of claim 1, further comprising a divide-by-two divider, wherein the sampling clock is buffered and delayed before being input to the divide-by-two divider, and wherein the divide-by-two divider outputs the clock sampling signal.
3. The delay self-calibration circuit of claim 1, wherein the phase detector comprises an exclusive or gate.
4. The delay self-calibration circuit according to claim 1, wherein the coarse-adjustment delay unit comprises an exclusive-or gate and N-stage sequentially cascaded coarse-adjustment delay sub-units, a first input end of the exclusive-or gate is connected with the sampling clock, a second input end of the exclusive-or gate is connected with the clock inversion enabling signal, an output end of the exclusive-or gate is connected with an input end of the 1 st-stage coarse-adjustment delay sub-unit, an input end of the i+1-stage coarse-adjustment delay sub-unit is connected with an output end of the i-stage coarse-adjustment delay sub-unit, an output end of the N-stage coarse-adjustment delay sub-unit outputs the coarse-adjustment sampling clock, and a control end of the N-stage coarse-adjustment delay sub-unit is connected with the N-bit coarse-adjustment delay control code in a one-to-one correspondence manner, wherein i is an integer of 1 to N-1.
5. The delay self-calibration circuit of claim 4, wherein the coarse-tuning delay sub-unit comprises two multiplexers and a delay structure, a first input of the two multiplexers is connected with an input end of the delay structure, an output of the delay structure is connected with a second input end of the two multiplexers, a control end of the two multiplexers is connected with the coarse-tuning delay control code, a first input of the two multiplexers is used as an input end of the coarse-tuning delay sub-unit, an output of the two multiplexers is used as an output end of the coarse-tuning delay sub-unit, and a control end of the two multiplexers is used as a control end of the coarse-tuning delay sub-unit.
6. The delay self-calibration circuit of claim 5, wherein in the coarse-tuning delay sub-unit of stage j, the delay structure comprises 2 (j-1) And the inverters are cascaded in sequence, wherein j is an integer from 1 to N.
7. The delay self-calibration circuit according to claim 1, wherein the fine adjustment control unit comprises an operational amplifier, a PMOS tube and an NMOS tube, wherein a non-inverting input end of the operational amplifier and an inverting input end of the operational amplifier are respectively connected to two differential ends of the third differential signal, a source electrode of the PMOS tube is connected to a power supply voltage, an output end of the operational amplifier is connected to a gate electrode of the PMOS tube, a drain electrode of the PMOS tube is connected to a drain electrode of the NMOS tube, a gate electrode of the NMOS tube is connected to a drain electrode of the NMOS tube, a source electrode of the NMOS tube is grounded, and a gate electrode of the NMOS tube outputs the bias voltage.
8. The delay self-calibration circuit according to claim 7, wherein the fine adjustment delay unit comprises S-stage sequentially cascaded current-mode inverters, the input end of the 1 st-stage current-mode inverter is connected with the coarse adjustment sampling clock, the input end of the k-1 st-stage current-mode inverter is connected with the output end of the k-1 st-stage current-mode inverter, the output end of the S-stage current-mode inverter outputs the fine adjustment sampling clock, the bias voltage is used as the tail current bias voltage of each stage of current-mode inverter, S is an integer greater than or equal to 2, and k is an integer from 2 to S.
9. A direct digital frequency synthesizer, comprising:
the digital control oscillator generates digital sine wave signals with multiple paths of lagged phases respectively according to the data signals;
the X+1 multiplexers are arranged in parallel, the input ends of the X multiplexers are connected with the digital sine wave signals in a one-to-one correspondence manner, the input ends of one multiplexer receive preset binary codes, and the control ends of the multiplexers are respectively connected with multiphase clock signals;
the input ends of the x latches are connected with the output ends of the x multiplexers for receiving the digital sine wave signals in a one-to-one correspondence manner;
the input end of the digital-to-analog converter is connected with the output end of each latch, and analog signals are output;
the clock frequency division module generates the sampling clock according to a system clock;
the input end of the first buffer is connected with the sampling clock, and the output end of the first buffer is connected with the clock control end of each latch;
the input end of the second buffer is connected with the sampling clock;
the delay self-calibration circuit according to any one of claims 2 to 8, wherein the delay self-calibration circuit is respectively connected to an output end of the second buffer, an output end of the multiplexer receiving the preset binary code, and an output end of the clock frequency division module, and obtains and outputs the fine-tuning sampling clock;
The multiphase clock generation module is used for generating the multiphase clock signal according to the fine-tuning sampling clock;
wherein x is an integer greater than or equal to 2.
10. A delay self-calibration method applied to the delay self-calibration circuit of any one of claims 1 to 8, comprising:
closing the fine adjustment control unit, enabling the coarse adjustment control unit to generate N bits of the coarse adjustment delay control code, adjusting by the coarse adjustment control unit, finding out and keeping the N bits of the coarse adjustment delay control code which enable the digital control code to be close to a 1/2 range based on adjustment feedback of the coarse adjustment control unit, so that the phase difference between the data sampling signal and the clock sampling signal is close to-Ts/2;
the coarse adjustment control unit is kept, the fine adjustment control unit is enabled to be combined with the coarse adjustment control unit and the fine adjustment control unit to perform adjustment, and the phase difference between the data sampling signal and the clock sampling signal is further close to-Ts/2 through adjustment feedback of the fine adjustment control unit;
wherein Ts is the period of the sampling clock.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117478107A (en) * | 2023-12-28 | 2024-01-30 | 芯光智网集成电路设计(无锡)有限公司 | Delay calibration method, transmitting end and source synchronous communication system |
| CN117590897A (en) * | 2023-11-23 | 2024-02-23 | 北京国科天迅科技股份有限公司 | Chip and chip control method |
| CN118249807A (en) * | 2024-05-28 | 2024-06-25 | 中国科学技术大学 | Large-range precise time delay adjusting circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117590897A (en) * | 2023-11-23 | 2024-02-23 | 北京国科天迅科技股份有限公司 | Chip and chip control method |
| CN117590897B (en) * | 2023-11-23 | 2024-08-06 | 北京国科天迅科技股份有限公司 | Chip and chip control method |
| CN117478107A (en) * | 2023-12-28 | 2024-01-30 | 芯光智网集成电路设计(无锡)有限公司 | Delay calibration method, transmitting end and source synchronous communication system |
| CN117478107B (en) * | 2023-12-28 | 2024-02-27 | 芯光智网集成电路设计(无锡)有限公司 | Delay calibration method, transmitting end and source synchronous communication system |
| CN118249807A (en) * | 2024-05-28 | 2024-06-25 | 中国科学技术大学 | Large-range precise time delay adjusting circuit |
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