JP2005354271A - Semiconductor device, clock phase adjustment circuit, transmission circuit, and reception circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for generating a broadband output clock with high accuracy. <P>SOLUTION: The semiconductor device is characterized by including: a delay section 2 including multi-stages of unit delay elements for sequentially delaying a received clock and for outputting an output of each unit element at each stage; phase synchronization means 4, 6 for feeding back a control signal on the basis of the output of each delay section to the delay section to apply feedback control to the delay amount of each unit delay element; a clock generating means 7 for generating an output clock on the basis of an output of each unit delay element of the delay section; a load capacitor connected to wires among the unit delay elements; and a switching means for switching connection/non-connection between the load capacitor and the wires installed among the unit delay elements. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device that obtains an output clock synchronized with a data bit, a clock phase adjustment circuit, a transmission circuit, and a reception circuit.

  In recent years, in systems using computers, data transmission at a high data rate is required due to a demand for high-speed processing. Accordingly, timing adjustment between data and clocks transmitted via different transmission lines has become an important design item.

  For example, for data transmission with an external memory, it is necessary to regenerate an accurate internal clock based on a clock from the outside of the chip. Even in a sampling circuit that latches and samples input data at an accurate timing, it is necessary to generate a sampling pulse at an accurate timing synchronized with the data. In addition, when transmitting data at various data rates, it is necessary to generate an accurate clock corresponding to the output data.

  In recent years, a DLL (abbreviation of delay phase locked loop) as a clock phase adjustment circuit that controls the phase of an output clock with high accuracy has become widespread as one that can be used for these various applications.

  Such a DLL circuit can generate a clock obtained by multiplying or multiplying the input clock frequency. That is, the DLL circuit includes a delay circuit including a plurality of unit delay circuits, a phase comparison circuit, a charge pump circuit, and a bias circuit. Here, the plurality of unit delay circuits are connected in series, the clock CK is input to the first stage unit delay circuit, and the multiphase clocks are output from the plurality of unit delay circuits from the first stage to the last stage. The phase comparison circuit compares the phases of the output signal of the first stage unit delay circuit and the output signal of the unit delay circuit separated by a predetermined number of stages, thereby obtaining a signal based on the phase difference. This phase difference signal is converted into a control voltage by a charge pump circuit and a bias circuit and fed back to the unit delay circuit.

The delay amount of each unit delay circuit varies depending on the control voltage, and the multiphase clock CK output from each unit delay circuit is the phase between the input signal of the first unit delay circuit and the output signal of the last unit delay circuit. The amount of delay is controlled so that. As a result, it is possible to generate n-phase multiphase clocks whose phases are evenly shifted by 1 / n cycles.
JP 2002-43313 A JP 2003-46377 A

  The above-described unit delay circuit of the DLL circuit may be composed of a transistor constituting a differential pair, a transistor constituting a current source, and the like. Each unit delay circuit delays the input clock by a unit delay and outputs it to the next unit delay circuit. In this case, the delay amount of each unit delay circuit can be controlled by using the transistor constituting the current source in the saturation region and changing the amount of current flowing between the source and the drain.

  By the way, in recent years, for example, mini-LVDS standards, which are image signal transmission standards, high-speed transfer rate memories, and the like have been required to be used in a wide frequency band as a DLL circuit.

  However, since it is necessary to drive the transistors constituting the current source in the saturation region, the control range of the current source is limited. If the control range of the current source transistor is designed so that it can be used in such a wide frequency band, fine adjustment of the frequency becomes difficult due to the limitation of the dynamic range, and the accuracy of the output clock is reduced. There was a problem.

  The present invention has been made in view of such a problem, and can control the output frequency in a wide band and can perform high-accuracy frequency adjustment in the entire band from low to high. An object of the present invention is to provide a clock phase adjustment circuit, a transmission circuit, and a reception circuit.

  The semiconductor device according to the present invention has a multi-stage unit delay element that sequentially delays an input clock, and outputs a delay unit that outputs an output of the unit delay element at each stage, based on an output from the delay unit A phase synchronization unit that feedback-controls a delay amount of the unit delay element by feeding back a control signal to the delay unit; a clock generation unit that generates an output clock based on an output of each unit delay element of the delay unit; and the unit The load capacitor connected to the wiring of the delay elements, and switching means for switching connection / disconnection between the wiring of the unit delay elements and the load capacitor are provided.

  According to such a configuration, the input clock is sequentially delayed by the multi-stage unit delay elements. The output of the unit delay element is given to the phase synchronization means, and a control signal for controlling the delay amount of the unit delay element is generated. The phase synchronization means feeds back the control signal to the delay unit and locks the delay amount of the unit delay element to an appropriate value. As a result, the clock generation means can obtain an output clock with appropriate timing according to the input clock based on the output of the unit delay element. In this case, the switching means switches connection / disconnection between the wiring of the unit delay elements and the load capacitance. When the load capacitance is not connected to the wiring, the delay amount of the unit delay element is small and a clock having a relatively high frequency can be obtained. In a state where the load capacitance is connected to the wiring, the delay amount of the unit delay element is large, and a clock having a relatively low frequency can be obtained. In any of these frequency bands, the dynamic range of control by the phase synchronization means is the same, and the same highly accurate phase control is possible regardless of the frequency band. Therefore, a highly accurate output clock can be obtained over a wide band.

  Further, the load capacitance is constituted by a gate capacitance of a MOS transistor.

  According to such a configuration, a load capacity can be easily configured on the semiconductor substrate.

  Further, the load capacity is constituted by a plurality of load capacities, and the switching means switches connection or non-connection of the plurality of load capacities to the wiring individually or simultaneously.

  According to such a configuration, control by the phase synchronization unit is possible for each number of bands corresponding to the number of load capacities, and more accurate phase control is possible for the output clock.

  Further, the present invention is characterized by further comprising frequency determining means for determining the frequency of the clock input to the delay unit and controlling the switching means based on the determination result.

  According to such a configuration, the frequency determination unit determines the frequency of the input clock and switches the switching unit based on the determination result. Thus, phase control is automatically performed for each optimum band according to the frequency of the input clock.

  Further, the frequency determination means outputs a determination result having a hysteresis characteristic as a determination result of the frequency of the input clock.

  According to such a configuration, frequent switching of the frequency band can be prevented, and stability can be improved.

  A clock phase adjusting circuit according to the present invention is configured using the semiconductor device.

  According to such a configuration, phase control is performed for each frequency band, so that highly accurate phase control is possible over a wide band. Thereby, a highly accurate output clock can be obtained.

  The output clock synchronized with the output data is generated using the output clock from the clock phase adjusting circuit.

  According to such a configuration, an output clock synchronized with the output data with high accuracy can be obtained even when the output data has a wide band.

  Further, the present invention is characterized in that a clock synchronized with input data is reproduced using an output clock from the clock phase adjusting circuit.

  According to such a configuration, since the output clock can be obtained with high accuracy, the received signal can be reliably captured.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a semiconductor device according to an embodiment of the present invention.

  This embodiment is applied to a clock phase adjustment circuit. 2 and 3 are block diagrams showing a receiving circuit and a transmitting circuit that employ the clock phase adjusting circuit of this embodiment, respectively.

  2, the receiving circuit 1 includes a DLL circuit 12 which is a clock phase adjusting circuit having the same configuration as that in FIG. A clock and data are input to the receiving circuit 11. The clock is input to the DLL circuit 12 and the data is input to the sampling circuit 13. The DLL circuit 12 generates a sampling clock having a predetermined period based on the input clock. The sampling circuit 13 converts serial data input using a sampling clock into parallel data. Thus, in the receiving circuit 11 of FIG. 2, even when data and a clock are transmitted via mutually different transmission paths, reliable serial-parallel conversion of data is possible.

  3, the transmission circuit 15 includes a DLL circuit 16 that is a clock phase adjustment circuit having the same configuration as that in FIG. The DLL circuit 16 generates a clock having a predetermined phase at a predetermined cycle based on the input clock. The DLL circuit 16 supplies the generated clock to the clock terminal of the output unit and outputs the input clock as an output clock. The output unit 17 latches the input data at the clock timing supplied to the clock end, and outputs n-bit data in one output clock cycle. In this manner, the transmission circuit 15 in FIG. 3 can output data of a predetermined bit synchronized with the clock.

  In the present embodiment, by using the clock phase adjustment circuit of FIG. 1 as the DLL circuit, it is possible to generate a clock whose phase is controlled with high accuracy in a wide frequency band.

  In FIG. 1, an input clock is input to the clock phase adjustment circuit 1. This input clock is input to the delay unit 2 and also to the period comparison circuit 4 and the frequency determination circuit 5. The delay unit 2 has a plurality of stages of delay elements 3-1, 3-2 (hereinafter also referred to as delay elements 3).

  FIG. 4 is a circuit diagram showing a specific configuration of each delay element of the delay unit 2.

  The delay elements 3-1, 3-2, 3-3,... Constituting the delay unit 2 are connected in cascade, and the delay amount is controlled by the control signals PB, NB, FC, BC, respectively. Yes. The received clock CK and its inverted signal CKX are input to the first delay element 3-1. The delay elements 3-1, 3-2, 3-3,... Delay the input signals by a delay amount based on the control signals PB, NB, FC, BC, respectively, and outputs O1, O2,. .. (Representatively referred to as output O) and inverted outputs XO1, XO2,... (Hereinafter, representatively referred to as inverted output XO) are respectively output to delay elements 3-2, 3-3,.

  Each delay element has the same configuration, and has P-channel transistors T1 to T3 and N-channel transistors T4 to T8 as shown in FIG. An input signal and its inverted signal are input to the gates of the P-channel transistors T1 and T2 forming a differential pair, respectively. Clocks CK and CKX are input to the transistors T1 and T2 of the delay element 3-1 in the first stage, respectively.

  The sources of the P-channel transistors T1 and T2 are connected in common and connected to the drain of the P-channel transistor T3, and a power supply voltage is applied to the source of the transistor T3. A control signal PB is supplied to the gate of the transistor T3.

  The drains of the transistors T1 and T2 are connected to the sources of the N-channel transistors T4 and T5, respectively, and are also connected to the gates of the transistors T5 and T4. The drains of the transistors T4 and T5 are connected in common and connected to the source of the N-channel transistor T6. The control signal NB is supplied to the gate of the transistor T6, and the drain is connected to the power supply terminal. The positive phase output from the drain of the transistor T2 of each delay element is output as the output O, and the negative phase output of the transistor T1 of each delay element is output as the inverted output XO.

  The amount of current flowing through each of the transistors T1 to T6 is controlled by the control signals PB and NB, and the time required for rising and falling of the normal phase output and the negative phase output is adjusted. That is, the time (delay amount) for propagating the input signal to the next stage is controlled by the control signals PB and NB.

  In the present embodiment, a band changing circuit 10 is connected between the wirings 8, 8 ′ connecting the unit delay elements 3 and the reference potential point 9. The band changing circuit 10 changes the delay amount of the unit delay element 3 relatively large. On the other hand, the delay amount control using the control signals PB and NB described above changes the delay amount relatively small.

  The delay amount control by the control signals PB and NB is the same as the method adopted in a general DLL circuit. That is, in FIG. 1, outputs O1, O2,... From each unit delay element 3 are given to the period comparison circuit 4. For example, the delay amount of each delay element 3-1, 3-2,... Of the delay unit 2 is approximately 1/16 of one cycle of the input clock CK. In this case, the period comparison circuit 4 determines whether or not the outputs O1, O2,... From the delay elements 3-1, 3-2,... Are accurately delayed by 1/16 of the input clock CK. Is detected.

  When the delay amount of each delay element 3 is larger than an appropriate value and the phase of each output O1, O2,... Is delayed from 1/16 of the input clock CK, the period comparison circuit 4 (UP) is generated and output to the bias generation circuit 6. Based on the UP signal, the bias generation circuit 6 generates control signals PB and NB having a level corresponding to the delay amount. Conversely, when the delay amount of each delay element 3 is larger than the appropriate value and the phase of each output O1, O2,... Is earlier than 1/16 of the input clock CK, the period comparison circuit 4 is down. A signal (DN) is generated and output to the bias generation circuit 6. In this case, the bias generation circuit 6 generates the control signals PB and NB at a level corresponding to the advance amount based on the DN signal. When the UP signal is generated, the level of the control signal PB becomes low and the level of the control signal NB becomes high. On the contrary, when the DN signal is generated, the level of the control signal PB rises and the level of the control signal NB falls.

  Control signals PB and NB from the bias generation circuit 6 are fed back to the delay unit 2. That is, when the delay amount of the delay element 3 of the delay unit 2 is larger than an appropriate value and the propagation of the clocks CK and CKX is delayed, the level of the control signal PB is lowered and the level of the control signal NB is decreased by the up signal. Rise. As a result, the amount of current flowing through the sources and drains of the transistors T3 and T6 constituting each delay element increases, and the delay amount of each delay element decreases. Conversely, when the delay amount of the delay element 3 becomes smaller than an appropriate value and the propagation of the clocks CK and CKX advances, the level of the control signal PB increases and the level of the control signal NB decreases due to the down signal. As a result, the amount of current flowing through the sources and drains of the transistors T3 and T6 constituting each delay element decreases, and the delay amount of each delay element increases.

  By this feedback control, the delay amount of each delay element converges to an appropriate value.

  An output clock adjustment circuit 7 as a clock generation unit is supplied with the output of each unit delay element 3 of the delay unit 2 and generates an output clock based on the output of each unit delay element 3. Assuming that the delay amount of each delay element 3 is approximately 1/16 of one cycle of the input clock CK, when the delay amount of each delay element 3 converges to an appropriate value and enters the locked state, each delay element 3 Are accurately shifted by 1/16 phase with respect to the input clock CK. Therefore, the output clock adjusting circuit 7 can output a 16-phase multiphase clock obtained by equally dividing one clock CK into 16 by using the output of each unit delay element 3. The output lock adjustment circuit 7 can generate an output clock having a desired phase with respect to the input clock by an external setting for the setting pin.

  The band changing circuit 10 includes switches SW1 and SW2 as switching means and NMOS transistors T7 and T8. The wiring 8 for transmitting the output O is connected to the base of the transistor T7 via the switch SW1, and the source and drain of the transistor T7 are connected in common and connected to the reference potential point 9. The wiring 8 'for transmitting the inverted output XO is connected to the base of the transistor T8 via the switch SW2, and the source and drain of the transistor T8 are connected in common and connected to the reference potential point 9.

  The NMOS transistors T7 and T8 constitute a load capacity by their gate capacity. The reference potential point 9 is set to a predetermined potential, for example, 0 V, by the bias generation circuit 6. The switches SW1 and SW2 are ON / OFF controlled independently of each other or in common by a control signal FC from a frequency determination circuit 5 described later. When the switch SW1 is turned on, a load capacitance by the transistor T7 is connected between the wiring 8 and the reference potential point 9, and when the switch SW2 is turned on, the wiring 8 ′ and the reference potential point are connected. 9 is connected to the load capacitance of the transistor T7. For example, when the frequency that can be generated as the output clock is 25 to 170 MHz, as the control signal FC, the switches SW1 and SW2 are turned off when the input clock frequency is about 100 MHz or more, and the input clock frequency is about 100 MHz or less. In this case, the switches SW1 and SW2 are set to values that turn on.

  That is, when the switches SW1 and SW2 are turned on, the load capacitances of the transistors T7 and T8 are added to the wiring capacitances of the wirings 8 and 8 ′ connecting the unit delay elements 3 to each other. Propagation time is significantly increased. The wiring capacity of the wiring for transmitting the outputs O and XO includes the capacity of the wirings 8 and 8 ′, the gate capacity of the differential transistor of the delay element 3 in the next stage, and the gate capacity of the inverter that outputs the outputs O and XO. Will be described as including.

  Thus, by sufficiently increasing the unit delay amount of the unit delay element 3, the bandwidth of the output clock can be sufficiently reduced. That is, by changing the unit delay amount of the unit delay element 3 relatively large by the band changing circuit 10, the frequency of the output clock can be greatly changed, and control for each of a plurality of bands is possible.

  Even in this case, the dynamic range of the delay amount by the control signals PB and NB does not change greatly. In other words, in the present embodiment, the band of the output clock is changed by the band changing circuit 10, and the phase control by the control signals PB and NB can be performed with substantially the same dynamic range for each band.

  The clock phase adjusting circuit of FIG. 1 has a frequency determination circuit 5 for automatically determining the frequency of the input clock in order to switch the frequency band of the output clock. FIG. 5 is a circuit diagram showing a specific configuration of the frequency determination circuit 5 in FIG.

  In FIG. 5, a frequency determination circuit 5 divides a frequency band into a first frequency band and a second frequency band (first frequency band <second frequency band) according to a predetermined reference frequency and is input. It is determined to which frequency band the clock belongs.

  When the input clock CK becomes faster than a predetermined second reference frequency (the second reference frequency is set to a frequency higher than the first reference frequency), the frequency determination circuit 5 When the input clock CK is determined to have changed from the first frequency band to the second frequency band and the input clock CK becomes slower than the first reference frequency, the input clock CK has changed from the second frequency band to the first frequency band. The control signal FC that is the determination result of the input clock frequency is output.

  The reference voltage output circuit 40 outputs the first reference voltage value VREF1 when the input clock currently belongs to the first frequency band, and outputs the first reference voltage value VREF1 when the input clock currently belongs to the second frequency band. The reference voltage is switched and output in accordance with the frequency band to which the input clock currently belongs so as to output the second reference voltage value VREF2.

  The control signal generation circuit 50 compares the reference value (voltage V2 in FIG. 5) output from the reference voltage output circuit 40 with the voltage value or current value (voltage V1 in FIG. 5) obtained based on the input clock or input clock. Then, the control signal FC is generated based on the comparison result.

  The reference voltage output circuit 40 outputs a reference voltage. The frequency voltage conversion circuit 30 generates and outputs an input clock conversion voltage according to the frequency of the input clock.

  The control signal generation circuit 50 compares the input clock conversion voltage V1 output from the frequency voltage conversion circuit 30 with the reference voltage V2 output from the reference voltage output circuit 10, and based on the comparison result, the control signal FC is generated. You may make it produce | generate.

  A reference voltage output by the reference voltage output circuit 40 based on the control signal FC is a first reference voltage value VREF1 (a voltage value set when the input clock belongs to the first frequency band) or a second reference voltage. It may be configured to switch to one of the values VREF2 (voltage value set when the input clock belongs to the second frequency band). Here, the first reference voltage VREF1 <the second reference voltage VREF2.

  Here, the reference voltage output circuit 40 can be configured to include a reference voltage generation circuit 42 and a switch circuit 44. The reference voltage generation circuit 42 generates a first reference voltage value VREF1 and a second reference voltage value VREF2 and outputs them to the switch circuit 44. The switch circuit 44 switches the output voltage to the first reference voltage value VREF1 or the second reference voltage value VREF2 based on the control signal FC.

  The divider circuit 20 divides the input clock and outputs a divided clock N_CK1 and a divided clock N_CK2. The frequency voltage conversion circuit 30 may generate the input clock conversion voltage V1 based on the divided clock N_CK1 and the divided clock N_CK2.

  Further, the control signal generation circuit 50 may be configured to include a comparator 52 and a D Philip flop 54. The comparator 52 compares the input clock conversion voltage V1 with the reference voltage V2 and outputs a comparison signal COMP. The D Philip flop 54 may be configured to output the control signal FC based on the comparison signal COMP and the divided clock N_CK2.

  With this configuration, when the input clock CK is in the first frequency band (low speed mode), the frequency determination circuit 5 uses the input clock CK as a predetermined second reference frequency (FDET_L in FIG. 6). ) When it is faster, it is determined that the input clock CK has changed from the first frequency band (low speed mode) to the second frequency band (high speed mode). The potential level of the control signal FC, which is the input frequency determination result, changes.

  Further, when the input clock CK is in the second frequency band (high speed mode), when the input clock CK becomes slower than the predetermined first reference frequency (FDET_H in FIG. 6), the input clock CK is 2 is changed from the frequency band (high speed mode) to the first frequency band (low speed mode), and the potential of the control signal FC which is the determination result of the input frequency along c → d → a in FIG. The level changes.

  That is, when the input clock is currently at low speed, the potential level of the control signal FC, which is the input frequency determination result, changes along a → b → c in FIG. 6, and the input clock CK is currently at high speed. In some cases, a hysteresis characteristic is obtained in which the potential level of the control signal FC changes along c → d → a in FIG.

  Next, the operation of the embodiment configured as described above will be described with reference to FIGS. 7 to 10 are timing charts showing operation timings of the frequency determination circuit of FIG. In FIG. 11, the horizontal axis represents the bias of the current source of the unit delay element, and the vertical axis represents the reciprocal (frequency) of the delay amount of the unit delay element. It is a graph which shows the relationship between the control signals PB and NB and the delay amount in each of the high speed modes.

  In the present embodiment, the clock phase can be adjusted in two modes, a low speed mode and a high speed mode. In the high speed mode, an n-phase (for example, 16-phase) output clock can be generated with respect to an input clock CK having a frequency higher than the first or second reference frequency. In the low speed mode, an n-phase (for example, 16-phase) output clock can be generated with respect to the input clock CK having a frequency lower than the first or second reference frequency.

  Furthermore, in the present embodiment, when the frequency determination circuit 5 changes the input clock, it outputs a frequency determination result having a hysteresis characteristic, so that the switching between the low speed mode and the high speed mode frequently occurs and the operation Can be prevented from becoming unstable.

  FIG. 7 is a timing chart showing the operation timing of the frequency determination circuit 5 when an input clock CK having a frequency slower than the first reference frequency is input.

  The input clock CK shown in FIG. 7 has a potential level that changes at a frequency slower than the reference frequency. Charging of the capacitor C1 of the frequency voltage conversion circuit 30 is started from the fall of the frequency-divided clock N_CK1 at time t1, and the potential V1 rises in a ramp shape. Then, the charging of the capacitor C1 is stopped by the rise of the frequency-divided clock N_CK1 at time t3, and the rise of the potential V1 is stopped. Further, the capacitor C1 is discharged by the rising of the frequency-divided clock N_CK2 at time t4, and the potential V1 becomes “L”.

  During this time, the comparator 52 compares the input clock conversion voltage V1 with the first reference voltage VREF1, and when the input clock conversion voltage V1 is greater than the first reference voltage VREF1, the comparison signal COMP is set to “L”, and the input clock conversion voltage V1. Is equal to or lower than the first reference voltage VREF1, the comparison signal COMP is set to the high level (hereinafter referred to as “H”). Here, the first reference voltage VREF1 is a voltage value set corresponding to the first reference frequency.

  Since the input clock conversion voltage V1 ≦ the first reference voltage VREF1 between the time t1 and the time t2, the comparison signal COMP is “H”. From the time t2 to the time t4, the input clock conversion voltage V1> first. Since it is the reference voltage VREF1, the comparison signal COMP becomes “L”.

  The D Philip flop 54 outputs a control signal FC as a frequency determination result based on the comparison signal COMP and the divided clock N_CK2.

  In FIG. 7, the value held in the D Philip flop 54 at the timing when the divided clock N_CK2 rises is “L” (for example, the comparison signal COMP is “L” at the timing t4 when the divided clock N_CK2 rises (reference sign). Therefore, the control signal FC that is the frequency determination result is “L”.

  The control signal FC from the frequency determination circuit 5 is supplied to each delay element 3 constituting the delay unit 2. The switches SW1 and SW2 shown in FIG. 4 are turned on when the control signal FC is “L”. That is, in this case, the load capacitance by the transistor T7 is connected to the wiring 8, and the load capacitance by the transistor T8 is connected to the wiring 8 '. Therefore, the delay amount of each unit delay element 3 is large and operates in the low speed mode.

  By control by the control signals PB and NB, as shown in FIG. 11, the bias of the current source transistor constituting each delay element 3 is adjusted within the adjustable bias range. Thereby, for example, a 16-phase clock based on the frequency of the input clock CK is output from the output clock adjustment circuit 7. The adjustable bias range has a sufficient dynamic range, and phase control of the output clock can be performed with high accuracy.

  FIG. 8 is a timing chart showing the operation timing of the frequency determination circuit 5 when the input clock CK changes from a frequency slower than the reference frequency to a frequency higher than the reference frequency.

  The potential level of the input clock CK shown in FIG. 8 changes at a frequency higher than the reference frequency. Charging of the capacitor C1 of the frequency voltage conversion circuit 30 is started from the fall of the frequency-divided clock N_CK1 at time t1, and the potential V1 rises in a ramp shape. Then, the charging of the capacitor C1 is stopped by the rise of the frequency-divided clock N_CK1 at time t2, and the rise of the potential V1 is stopped. Further, the capacitor C1 is discharged by the rise of the frequency-divided clock N_CK2 at time t3, and the potential V1 becomes “L”.

  During this time, the comparator 52 compares the input clock conversion voltage V1 with the first reference voltage VREF1, and when the input clock conversion voltage V1 is greater than the first reference voltage VREF1, the comparison signal COMP is set to “L”, and the input clock conversion voltage V1. Is equal to or lower than the first reference voltage VREF1, the comparison signal COMP is set to “H”. Here, the first reference voltage VREF1 is a voltage value set corresponding to the first reference frequency. Since the input clock conversion voltage V1 ≦ the first reference voltage VREF1 between the time t1 and the time t3, the comparison signal COMP becomes “H”.

  5 outputs a control signal FC, which is a frequency determination result, based on the comparison signal COMP and the divided clock N_CK2. In FIG. 8, the value held in the D Philip flop 54 at the timing when the divided clock N_CK2 rises is “H” (for example, the comparison signal COMP is “H” at the timing t3 when the divided clock N_CK2 rises (reference sign). Therefore, the control signal FC that is the frequency determination result is “H”.

  The control signal FC from the frequency determination circuit 5 is supplied to each delay element 3 constituting the delay unit 2. The switches SW1 and SW2 shown in FIG. 4 are turned off when the control signal FC is “H”. In this case, the load capacity due to the transistors T7 and T8 is not connected to the wirings 8 and 8 ', and the delay amount of each unit delay element 3 is small. That is, the mode is switched from the low speed mode to the high speed mode, and the output clock adjustment circuit 7 can generate a high frequency output clock based on the input clock CK.

  Even in this case, as shown in FIG. 11, the adjustable bias range of the current source transistor constituting each delay element 3 is the same as that in the low speed mode. The bias adjustment by the control signals PB and NB has a sufficient dynamic range, and the phase control of the output clock can be performed with high accuracy. Thus, for example, a 16-phase high frequency clock is output from the output clock adjusting circuit 7 based on the frequency of the input clock CK.

  FIG. 9 is a timing chart showing the operation timing of the frequency determination circuit when an input clock CK having a frequency higher than the reference frequency is input. The potential level of the input clock CK shown in FIG. 9 changes at a frequency higher than the reference frequency.

  Charging of the capacitor C1 of the frequency voltage conversion circuit 30 is started from the fall of the frequency-divided clock N_CK1 at time t1, and the potential V1 rises in a ramp shape. Then, the charging of the capacitor C1 is stopped by the rise of the frequency-divided clock N_CK1 at time t2, and the rise of the potential V1 is stopped. Further, the capacitor C1 is discharged by the rise of the frequency-divided clock N_CK2 at time t3, and the potential V1 becomes “L”.

  During this time, the comparator 52 compares the input clock conversion voltage V1 with the second reference voltage VREF2, and when the input clock conversion voltage V1 is greater than the second reference voltage VREF2, the comparison signal COMP is set to “L”, and the input clock conversion voltage V1. Is equal to or lower than the second reference voltage VREF2, the comparison signal COMP is set to “H”. Here, the second reference voltage VREF2 is a voltage value set corresponding to the second reference frequency.

  Since the input clock conversion voltage V1 ≦ the second reference voltage VREF2 between the time t1 and the time t3, the comparison signal COMP becomes “H”. The D Philip flop 54 outputs a control signal FC as a frequency determination result based on the comparison signal COMP and the divided clock N_CK2.

  In FIG. 9, the value held in the D Philip flop 54 at the timing when the divided clock N_CK2 rises is “H” (for example, the comparison signal COMP is “H” at the timing t3 when the divided clock N_CK2 rises (reference sign). Therefore, the control signal FC that is the frequency determination result is “H”.

That is, in this case, the output lock adjustment circuit 7 operates in the high speed mode shown in FIG. 11 and outputs a high frequency output clock based on the input clock CK.

  FIG. 10 is a timing chart showing the operation timing of the frequency determination circuit when the input clock CK changes from a frequency higher than the reference frequency to a frequency lower than the reference frequency. The potential level of the input clock CK shown in FIG. 10 changes at a frequency slower than the reference frequency. Charging of the capacitor C1 of the frequency voltage conversion circuit 30 is started from the fall of the frequency-divided clock N_CK1 at time t1, and the potential V1 rises in a ramp shape. Then, the charging of the capacitor C1 is stopped by the rise of the frequency-divided clock N_CK1 at time t3, and the rise of the potential V1 is stopped. Further, the capacitor C1 is discharged by the rising of the frequency-divided clock N_CK2 at time t4, and the potential V1 becomes “L”.

  During this time, the comparator 52 compares the input clock conversion voltage V1 with the second reference voltage VREF2, and when the input clock conversion voltage V1 is greater than the second reference voltage VREF2, the comparison signal COMP is set to “L”, and the input clock conversion voltage V1. Is equal to or lower than the second reference voltage VREF2, the comparison signal COMP is set to “H”. Here, the second reference voltage VREF2 is a voltage value set corresponding to the second reference frequency.

  Since the input clock conversion voltage V1 ≦ the second reference voltage VREF2 between the time t1 and the time t2, the comparison signal COMP is “H”, and the input clock conversion voltage V1> second between the time t2 and the time t4. Since it is the reference voltage VREF2, the comparison signal COMP becomes “L”. The D Philip flop 54 outputs a control signal FC as a frequency determination result based on the comparison signal COMP and the divided clock N_CK2.

  In FIG. 10, the value held in the D lip flop 54 at the timing when the divided clock N_CK2 rises is “L” (for example, the comparison signal COMP is “L” at the timing t4 when the divided clock N_CK2 rises (reference sign). Therefore, the control signal FC that is the frequency determination result is “L”.

  That is, the control signal FC does not change only when the input clock CK falls below the second reference frequency, and further changes to “L” only after the input clock CK falls below the first reference frequency. By this control signal FC, the delay unit 2 operates with a delay amount in the low speed mode, and the output lock adjustment circuit 7 outputs an output clock having a relatively low frequency based on the input clock CK.

  As described above, switching from the low speed mode to the high speed mode is when the input clock CK exceeds the second reference frequency. That is, when the input clock CK has a frequency between the first reference frequency and the second reference frequency, the mode is not switched. Thereby, stable mode switching is possible.

  As described above, in the present embodiment, the delay amount of the unit delay element is controlled with high accuracy by the bias of the current source transistor, and the delay of the unit delay element is increased or decreased by increasing or decreasing the capacitance of the wiring between the unit delay elements. The amount can be changed greatly. Accordingly, delay amount control using a sufficient dynamic range can be performed for each frequency band, and a highly accurate output clock can be output over a wide band.

  Further, by performing frequency determination having hysteresis characteristics on the input clock CK, switching of each band is performed, and it is possible to prevent the control from becoming unstable due to frequent switching of the band. .

  In the above embodiment, the control signal BC supplied to the reference potential point 9 has been described as being set to a predetermined fixed value by the bias generation circuit 6, but BC can be made variable. . In this case, the delay amount of the unit delay element can also be controlled by BC control. For example, by setting the control signal BC to a value corresponding to the input clock frequency based on the determination result of the frequency determination circuit 5, it is possible to perform phase control with a wider range and higher accuracy.

  In the above embodiment, the switches SW1 and SW2 are simultaneously turned on or off by the control signal FC. However, it is obvious that the switches SW1 and SW2 may be individually controlled. Further, the example in which the two load capacitors of the transistors T7 and T8 are connected has been described. However, three or more load capacitors may be connected, and these load capacitors may be connected or disconnected to the wiring individually or simultaneously. Good. By switching the connection and non-connection individually by increasing the load capacity to be connected, the number of band divisions can be increased and high-precision phase control becomes possible.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

1 is a block diagram illustrating a semiconductor device according to an embodiment of the present invention. The block diagram which shows the receiving circuit which employ | adopted the clock phase adjustment circuit of this Embodiment. The block diagram which shows the transmission circuit which employ | adopted the clock phase adjustment circuit of this Embodiment. FIG. 2 is a circuit diagram showing a specific configuration of each delay element of the delay unit 2 in FIG. 1. FIG. 2 is a circuit diagram showing a specific configuration of a frequency determination circuit 5 in FIG. 1. 6 is a graph showing hysteresis characteristics of the determination result of the frequency determination circuit 5. 6 is a timing chart showing the operation timing of the frequency determination circuit. 6 is a timing chart showing the operation timing of the frequency determination circuit. 6 is a timing chart showing the operation timing of the frequency determination circuit. 6 is a timing chart showing the operation timing of the frequency determination circuit. The graph for demonstrating operation | movement of embodiment.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 1 ... Clock phase adjustment circuit, 2 ... Delay part, 3 ... Delay element, 4 ... Period comparison circuit, 5 ... Frequency determination circuit, 6 ... Bias generation circuit, 7 ... Output clock phase adjustment circuit

Claims (8)

A delay unit having a plurality of unit delay elements for sequentially delaying the input clock, and outputting an output of the unit delay element of each stage;
A phase synchronization unit that feedback-controls a delay amount of the unit delay element by feeding back a control signal based on an output from the delay unit to the delay unit;
Clock generating means for generating an output clock based on the output of each unit delay element of the delay unit;
A load capacitance connected to the wiring between the unit delay elements;
A semiconductor device comprising switching means for switching connection / disconnection between the wiring of the unit delay elements and the load capacitance.   The semiconductor device according to claim 1, wherein the load capacitance is configured by a gate capacitance of a MOS transistor. The load capacity is composed of a plurality of load capacities,
The semiconductor device according to claim 1, wherein the switching unit switches connection or non-connection of the plurality of load capacitors to or from the wiring individually or simultaneously.   A semiconductor device, further comprising: a frequency determining unit that determines a frequency of a clock input to the delay unit and controls the switching unit based on a determination result.   The semiconductor device according to claim 1, wherein the frequency determination unit outputs a determination result having a hysteresis characteristic as a determination result of the frequency of the input clock.   A clock phase adjusting circuit comprising the semiconductor device according to claim 1.   7. A transmission circuit for generating an output clock synchronized with output data using an output clock from the clock phase adjustment circuit according to claim 6.   A receiving circuit for regenerating a clock synchronized with input data using an output clock from the clock phase adjusting circuit according to claim 6.

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