JP2010171826A - Controller for memory module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller for a memory module having a function of determining timing of a received clock signal and a strobe signal and outputting a result of the determination, the memory controller effectively utilizing the function. <P>SOLUTION: The present invention relates to a controller 1 for a memory module of the DDR3 standard memory, including: a master DLL 30 which outputs a delay control signal for controlling delay of a signal inputted from the memory module; a strobe signal control section 40 for delaying the strobe signal and outputting it as a delay strobe signal; and a data signal control section 50 for delaying a data signal and outputting it as a delay data signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a memory module controller and a memory module control method, and more particularly to a memory module controller having a function of judging the timing of a received clock signal and strobe signal and outputting a judgment result.

  A DRAM (Dynamic Random Access Memory) used as a main memory of an information processing apparatus such as a PC (Personal Computer) has a double data rate system such as a synchronous DDR (Double Data Rate) -SDRAM and a DDR2-SDRAM. Mainstream. DDR3-SDRAM is becoming mainstream among these memory modules.

  In the DDR3-SDRAM, a specification having a data rate of 800 Mbps or more is standardized by JEDEC (Joint Electron Engineering Engineering Council).

  A memory controller that controls such a memory module receives read data together with a read data strobe from the memory module during a read operation. At this time, in order to accurately capture the data at the rising and falling edges of the strobe signal, the strobe signal for the data within the memory control is accurately accurate by a quarter period (90 ° phase difference) of the memory operation clock. It is best to delay.

  FIG. 11 is a conventional timing control circuit, and FIG. 12 is a timing diagram of FIG. The delay control circuit 603 calculates a delay setting value corresponding to one cycle of the input clock by the phase comparison operation of the DLL 600 and outputs the delay setting value to the delay element 602 and the delay setting value calculation circuit 701 in the DLL 600.

  The delay setting value calculation circuit 701 calculates a delay setting value of the delay element 702 that delays the strobe signal from the delay setting value and the gear ratio setting value input from the delay control circuit 603 and outputs the delay setting value to the delay element 702. The delay element 702 delays the input strobe signal based on the delay setting value input from the delay setting calculation circuit 701 and outputs the delayed strobe signal to the flip-flops 707 to 710 as a corrected strobe signal.

  The minimum delay elements 703 to 706 have the same delay value as the delay value of the delay element 702 whose delay value is set to 0%. When the gear ratio setting value is 45%, the delay setting value calculation circuit 701 sets a delay value of 45% of the clock in the delay element 702, and the delay element 702 outputs the input strobe signal to the delay signal. The output is delayed by the value and output to the flip-flops 707 to 710. With such a configuration, the strobe signal is kept at a constant delay amount with respect to the data.

  Here, if the delay value control corresponding to the delay setting is configured by a digital circuit, the resolution of phase adjustment cannot be made smaller than the delay amount of the minimum delay element. Also, if the delay amount of this minimum delay element increases due to the influence of the process, power supply voltage, and temperature, the phase difference between the data and the strobe signal shifts. Therefore, when the memory transfer rate increases, the data and strobe signal It becomes difficult to ensure timing specifications.

  On the other hand, a technique has been proposed in which a timing adjustment circuit is configured by an analog DLL, and a timing adjustment circuit capable of delay control of equal phase difference with high accuracy and high resolution is realized with a small circuit scale and low power consumption (for example, Patent Document 1). The technique disclosed in Patent Document 1 is intended to generate a multi-phase clock, and has a different purpose from the present case that aims to control the phase of a signal in a controller of a memory module.

  In the DDR3-SDRAM, a write leveling function is defined, and the memory controller can perform phase correction between the clock and the strobe by feedback from the memory module. In order to enable such phase correction, a configuration for controlling the phase of the strobe signal or the like on the memory controller side is required. This configuration is not a test mode configuration but a configuration used in normal operation.

  The present invention has been made in consideration of the above circumstances, and can effectively use the function in the controller of the memory module having the function of judging the timing of the received clock signal and strobe signal and outputting the judgment result. An object of the present invention is to provide a simple memory controller.

  In order to solve the above-mentioned problem, the invention according to claim 1 is a controller of a memory module having a function of judging the timing of a received memory clock signal and strobe signal and outputting a judgment result. A delay control signal output unit for outputting a delay control signal for controlling a delay of a signal input from the memory, a strobe signal delay control unit for delaying a strobe signal input from the memory module and outputting the delayed strobe signal, and A data signal delay control unit that delays a data signal input from the memory module and outputs the delayed data signal as a delayed data signal, the delay control signal output unit delaying each other based on a reference clock input as a differential signal A delay signal output unit that outputs a plurality of delay signals having different intervals; A delay control signal generation unit that compares two signals included in the extended signal and generates the delay control signal according to a phase difference between the two signals. The delay signal output unit is a delay element having a differential configuration. A delay generation unit in which a plurality of voltage-controlled delay elements that output an input signal after being delayed by a delay interval corresponding to the delay control signal and a plurality of voltage-controlled delay elements connected in series are respectively provided. A delay signal generation unit that generates the plurality of delay signals by converting a differential signal to be output into a single-ended signal, and an output signal switching unit that switches and outputs the plurality of delay signals generated by the delay signal generation unit The delay signal generation unit converts a differential signal input to one of the plurality of voltage-controlled delay elements connected in series into a single-ended signal, and A second delay signal obtained by converting a differential signal output from a voltage control delay element provided two or more stages after a voltage control delay element that outputs one delay signal into a single-ended signal is output as the two signals. The strobe signal delay control unit generates a plurality of delay signals having different delay intervals based on the strobe signal according to the delay control signal with the same configuration as the delay signal output unit, and One of the delay signals is output as the delay strobe signal, and the data signal delay control unit has a delay interval based on the data signal in accordance with the delay control signal with the same configuration as the delay signal output unit. A plurality of delay signals having different delay intervals from the delay strobe signal among the plurality of generated delay signals. Output as.

  According to a second aspect of the present invention, in the controller of the memory module according to the first aspect, the delay generation unit includes at least four voltage-controlled delay elements connected in series, and the delay signal generation unit Converts the differential signal input to the voltage control delay element provided at the head of the four voltage control delay elements into the first delay signal, and is the fourth among the four voltage control delay elements. The differential signal output from the voltage control delay element provided is converted into the second delay signal, and the delay control signal generation unit includes a phase of the first delay signal and a phase of the second delay signal. The delay control signal is generated so that the difference between the two becomes a predetermined interval.

  According to a third aspect of the present invention, in the controller of the memory module according to the second aspect, the delay control signal generation unit is configured to output a phase of a differential signal input to the voltage control delay element provided at the head. The delay control signal is generated so that the difference between the phase of the differential signal output from the fourth voltage control delay element provided in the fourth cycle is a half cycle.

  According to a fourth aspect of the present invention, in the controller of the memory module according to the third aspect, the delay signal generation unit is based on one of the first delay signal and the second delay signal. The differential control signal is output as an inverted signal, and the delay control signal generation unit generates the delay control signal so that rising timings of the two signals coincide with each other.

  According to a fifth aspect of the present invention, in the controller of the memory module according to the third or fourth aspect, the strobe signal delay control unit is a voltage control provided secondly among the four voltage control delay elements. A signal obtained by converting the differential signal output from the delay element into a single-ended signal is output as the delayed strobe signal, and the data signal delay control unit is provided at the head of the four voltage controlled delay elements. A signal obtained by converting a differential signal input to the voltage controlled delay element into a single-ended signal is output as the delayed data signal.

  According to a sixth aspect of the present invention, in the controller of the memory module according to any of the second to fifth aspects, the delay signal generation unit further includes the same voltage in series before the four voltage controlled delay elements. A control delay element is connected.

  According to a seventh aspect of the present invention, in the controller of the memory module according to any one of the second to sixth aspects, the delay signal generation unit further includes the same voltage control in series after the four voltage control delay elements. A delay element is connected.

  According to an eighth aspect of the present invention, in the controller of the memory module according to any one of the first to seventh aspects, the delay signal generation unit outputs a difference output from each of the plurality of voltage-controlled delay elements connected in series. The plurality of delayed signals are generated by converting a moving signal into two single-ended signals whose phases are inverted from each other.

  The invention according to claim 9 is the controller of the memory module according to any one of claims 1 to 8, further comprising a reference clock output unit that outputs the reference clock, wherein the reference clock output unit includes a plurality of reference clock output units. A ring oscillator having a differential configuration including a voltage controlled delay element, a memory clock generation unit that converts a differential signal extracted from the ring oscillator into a single-ended signal and generates a memory clock signal to be input to the memory module; Based on the reference clock generation unit that outputs the differential signal extracted from the ring oscillator as the differential signal that is input to the delay control signal output unit, the generated memory clock signal, and the clock signal input from the outside A control signal for controlling a voltage control delay element included in the ring oscillator Characterized in that it comprises a force control signal generating unit.

  According to the present invention, in a controller of a memory module having a function of judging the timing of a received clock signal and strobe signal and outputting a judgment result, it is possible to perform a loopback test with a configuration similar to that during normal operation.

It is a figure which shows the structure of the memory controller which concerns on embodiment of this invention. It is a figure which shows the circuit structure of CP which concerns on embodiment of this invention. It is a figure which shows the circuit structure of the bias circuit which concerns on embodiment of this invention. It is a figure which shows the structure of VCDL which concerns on embodiment of this invention. It is a figure which shows the input-output relationship of the voltage control delay element which concerns on embodiment of this invention. It is a figure which shows the circuit structure of the voltage control delay element which concerns on embodiment of this invention. It is a figure which shows the structure of the buffer which concerns on embodiment of this invention. It is a timing chart of the signal which VCDL concerning the embodiment of the present invention outputs. It is a figure which shows the structure of the memory controller which concerns on other embodiment of this invention. It is a figure which shows the structure of PLL which concerns on other embodiment of this invention. It is a figure which shows the structure of the memory controller which concerns on a prior art. It is a timing chart which shows the timing of the signal of the memory controller which concerns on a prior art.

Embodiment 1 FIG.
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a memory controller 1 as a controller of a memory module according to the present embodiment. As shown in FIG. 1, a memory controller 1 according to the present embodiment includes a PLL (Phase-Locked Loop) 10, a plurality of single / differential converters (hereinafter referred to as SD converters) 20, a master DLL (Delay Locked). Loop) 30, a strobe signal control circuit 40, and a plurality of data signal control circuits 50 are included. Note that these configurations are portions for performing a data read operation from the memory module, and a portion for performing a data write operation to the memory module is separately provided, but is not illustrated in FIG.

  The memory controller 1 according to the present embodiment is a controller of a memory module corresponding to the DDR3-SDRAM standard. In the DDR3-SDRAM, a write leveling function is defined, and the memory controller can receive feedback from the memory module regarding the phase of the clock and the strobe. In order to make use of this function, the memory controller 1 needs to be configured to control the phase of a strobe signal, a data signal, or the like. The memory controller 1 according to the present embodiment solves such a problem.

The PLL 10 outputs a memory clock CLK _mem input to the memory module and a reference clock CLK _std for controlling the master DLL. Among the plurality of SD converter 20, SD converter 20 CLK _std is input to output is PLL10 is the CLK _std is a single-ended signal, consisting of a plus differential potential V _P and minus differential voltage V _M difference Converted to a dynamic signal CLK _DIF .

  As shown in the drawing, the master DLL 30 includes a VCDL (Voltage Control Delay Line) 100, a PFD (Phase Frequency Detector) 200, a CP (Charge Pump) 300, a loop filter 400, and a bias circuit 500. Have

The VCDL 100 generates a single-ended delay signal obtained by delaying the CLK _DIF in a plurality of stages according to the plus control signal P _cnt and the minus control signal N _cnt output from the bias circuit 500. Two F00 and F00A are output. The configuration of the VCDL 100 will be described in detail later. The PFD 200 compares the phases of the rising edges of F00 and F00A output from the VCDL 100, and outputs either the error signal UP or DN according to the phase difference.

  As shown in FIG. 2, the CP 300 includes a p-type transistor 301, an n-type transistor 302, a current source 303 and a current source 304. UP output from the PFD 200 is input to the gate of the p-type transistor 301. The source of the p-type transistor 301 is connected to a high potential via the current source 303, and the drain is connected to the output of the pulse signal CPO. As a result, when the PFD 200 outputs UP, the p-type transistor 301 is turned on, and a positive pulse is output as CPO by the current of the current source 303.

  On the other hand, DN output from the PFD 200 is input to the gate of the n-type transistor 302. The drain of the n-type transistor 302 is connected to the output of the pulse signal CPO, and the source is grounded through the current source 304. As a result, when the PFD 200 outputs DN, the n-type transistor 302 is turned on, and a negative pulse is output as CPO by the current of the current source 304.

  Loop filter 400 smoothes CPO output from CP 300 and outputs control voltage VCO. When CPO is a positive pulse, the voltage of VCO output from CPO increases. On the other hand, when CPO is a negative pulse, the voltage of VCO output from CPO decreases.

As shown in FIG. 3, the bias circuit 500 includes a variable current source 501, a p-type transistor 502, a p-type transistor 503, and an n-type transistor 504. The variable current source 501 is a current source whose current value changes according to the voltage of the VCO output from the loop filter 400. One end of the current source 501 is connected to the output of P _cnt , the gate of the p-type transistor 502, the gate of the p-type transistor 503, and the drain of the p-type transistor 502. Thereby, the current amount of P _cnt is determined according to the voltage value of the VCO.

In the p-type transistor 503, the source is connected to a high potential, the drain is connected to the output of N _cnt , the gate of the n-type transistor 504, and the drain of the n-type transistor 504. Thereby, the amount of N _cnt current is determined according to the voltage value of the VCO. That is, the bias circuit 500 outputs the P _cnt and N _cnt so that the amount of current is increased in accordance with the increase of the voltage value of the VCO, P _cnt so that the amount of current decreases according to the decrease of the voltage value of the VCO And N _cnt are output.

In this way, the master DLL 30 operates to output P _cnt and N _cnt as a whole. As described above, the VCDL 100 generates a delay signal according to P _cnt and N _cnt . That is, P _cnt and N _cnt are used as delay control signals, and the master DLL 30 functions as a delay control signal output unit. Further, the PFD 200, the CP 300, the loop filter 400, and the bias circuit 500 function as a delay control signal generation unit that generates a delay signal according to the phase difference between the two signals F00 and F00A.

  The strobe signal control circuit 40 includes a VCDL 101, delays the strobe signal DQS converted into a differential signal by the SD converter 20, and outputs the delayed signal as a single-ended signal. The VCDL 101 included in the strobe signal control circuit 40 has the same configuration as that of the VCDL 100 included in the master DLL 30, generates a single-ended delay signal obtained by delaying the DQS in a plurality of stages, and F2 among the generated delay signals is F2 Is output as a delayed strobe signal. That is, the strobe signal control circuit 40 functions as a strobe signal delay control unit.

  The SD converter 20 that generates a differential signal input to the strobe signal control circuit 40 converts the strobe signal output as a single-ended signal from the memory module into a differential signal.

  The plurality of data signal control circuits 50 are provided for each of the plurality of data signals DQ0, DQ1, DQ2,... DQ7 (hereinafter, DQ0 to DQ7 are collectively referred to as DQ). Each data signal control circuit 50 includes a VCDL 102, delays the DQ converted into a differential signal by the SD converter 20, and outputs it as a single-ended signal.

  The VCDL 102 included in the data signal control circuit 50 has a configuration similar to that of the VCDL 100 included in the master DLL 30, and generates a single-ended delay signal obtained by delaying DQ in a plurality of stages. Is output as a delayed data signal. That is, the data signal control circuit 50 functions as a data signal delay control unit.

  The SD converter 20 that generates a differential signal input to each data signal control circuit 50 converts the data signal output as a single-ended signal from the memory module into a differential signal.

  Next, the configuration of the VCDL 100 according to the present embodiment will be described. FIG. 4 is a diagram showing the configuration of the VCDL 100. As shown in FIG. The VCDL 101 and the VCDL 102 have the same configuration as that shown in FIG. As shown in FIG. 4, the VCDL 100 includes a delay signal generation circuit 110, a clock generation unit 120, and a switching circuit 130. The delay signal generation circuit 110 includes a plurality of voltage control delay elements 111a, 111b, 111c, 111d, 111e, and 111f connected in series.

The voltage control delay elements 111a, 111b, 111c, 111d, 111e, and 111f (hereinafter, any one of them is referred to as a voltage control type delay element 111) is a voltage control differential amplifier, as shown in FIG. The plus-side differential signal I + and the minus-side differential signal I- are delayed in accordance with P _cnt and N _cnt , and the plus-side and minus-side are inverted, and the minus-side differential signal O− and Output as a positive differential signal O +. That is, P _cnt and N _cnt are used as a delay control signal for controlling the delay in the voltage control delay element 111. FIG. 6 shows the configuration of the voltage controlled delay element 111.

As shown in FIG. 6, the voltage controlled delay element 111 includes a p-type transistor 112, a p-type transistor 113, an n-type transistor 114, an n-type transistor 115, and an n-type transistor 116. In the p-type transistor 112, P _cnt is input to the gate, the drain is connected to a high potential, the source is connected to the output of O−, and the drain of the n-type transistor 114.

In the p-type transistor 113, P _cnt is input to the gate, the source is connected to a high potential, the drain is connected to the O + output, and the drain of the n-type transistor 115. In the n-type transistor 114, I + is input to the gate, the drain is connected to the drain of the p-type transistor 112 and the output of O−, and the source is connected to the drain of the n-type transistor 116 and the source of the n-type transistor 115. .

In the n-type transistor 115, I− is input to the gate, the drain is connected to the source of the p-type transistor 113 and the output of O +, and the source is connected to the drain of the n-type transistor 116 and the source of the n-type transistor 114. . In the n-type transistor 116, N _cnt is input to the gate, the drain is connected to the sources of the n-type transistor 114 and the n-type transistor 115, and the source is grounded.

In the operation of the voltage controlled delay element 111 shown in FIG. 6, first, the amount of current output from the sources of the p-type transistor 112 and the p-type transistor 113 increases in accordance with the voltage value of P _cnt . The current output from the source of the p-type transistor 112 flows to the output side as O− and to the drain of the n-type transistor 114. On the other hand, the current output from the source of the p-type transistor 113 flows to the output side as O + and to the drain of the n-type transistor 115.

  Here, the amount of current flowing through the n-type transistor 114 and the n-type transistor 115 varies depending on I + and I− input to the gate, respectively, and the higher the voltage value applied to the gate, the more current flows. As the amount of current flowing through the n-type transistor 114 increases, the current flowing to the output side of O− decreases, and as a result, the voltage value of O− decreases. Further, as the amount of current flowing through the n-type transistor 115 increases, the current flowing to the output side of O + decreases, and as a result, the voltage value of O + decreases. The current flowing through each transistor refers to the current flowing from the drain to the source of each transistor, and the same applies in the following description.

  As described above, the amount of current flowing through the n-type transistor 114 is determined by I + and affects O−. Further, the amount of current flowing through the n-type transistor 115 is determined by I− and affects O +. Thereby, the differential signal on the plus side and the minus side is inverted.

Further, the amount of current flowing through the n-type transistor 114 and the n-type transistor 115 is determined by the amount of current flowing through the n-type transistor 116. As the voltage value of the N _cnt is high, the amount of current flowing in the n-type transistor 116 increases, as the voltage value of the N _cnt is high, becomes large amount of current flowing through the n-type transistor 114 and the n-type transistor 115.

Further, since the potentials of O− and O + increase as the amount of current output from the sources of the p-type transistor 112 and the p-type transistor 113 increases, changes in O− and O + corresponding to changes in I + and I− are sharp. It becomes. As a result, the larger the current amount of P _cnt and N _cnt , the smaller the delay amount of O− and O +, which are the delay signals, with respect to I + and I−.

  The delay signal generation circuit 110 can generate a differential signal delayed in a plurality of stages by connecting the voltage-controlled delay elements 111 described in FIGS. 5 and 6 in series. That is, the delay signal generation circuit 110 functions as a delay generation unit. The VCDL 100 functions as a delay signal output unit as a whole.

For example, as shown in FIG. 4, the first stage of the voltage-controlled delay element 111a delays the V _P and V _M, and outputs the O4 and O0. The second-stage voltage-controlled delay element 111b delays O4 and O0 and outputs O1 and O5. Since all the voltage controlled delay elements 111 have the same configuration, the delay amount generated in all the voltage controlled delay elements 111 is the same.

  The voltage control delay element 111f is not provided as a delay element, but is provided to make the load of the wiring driven by the voltage control delay element 111e the same as the other voltage control delay elements 111a to 111d. Thereby, the offset between the timing of the signal output from the voltage control delay element 111e and the timing of the signal output from the other voltage control delay elements 111a to 111d can be eliminated.

Delay signal generator circuit 110 according to this embodiment, as the timing of the output of the voltage controlled delay element 111a, and the timing of the output of the voltage-controlled delay element 111e as a phase difference of 180 °, P _cnt and N controlled by _cnt . Detailed operations will be described later.

  The clock generation unit 120 converts the differential signals output by the delay signal generation circuit 110 after being delayed in a plurality of stages into single-ended signals and outputs the signals as clock signals. That is, the clock generation unit 120 functions as a delay signal generation unit. A differential signal, for example, O4 and O0, output from the voltage-controlled delay element 111 in each stage included in the delay signal generation circuit 110 is converted into a differential / single conversion circuit (hereinafter referred to as a DS conversion circuit) through a differential buffer. ) And converted to a single-ended signal.

  Here, as shown in FIG. 4, two DS conversion circuits are connected to one differential buffer, and the positive side and the negative side of the differential signal are inverted and inputted. As a result, the delay signal and its inverted signal are output by the one-stage voltage-controlled delay element 111. For example, the output of the voltage controlled delay element 111a is output as the delayed signals F0 and F00 and the delayed inverted signal via the clock generator 120. The output of the voltage control type delay element 111b is output as a delay signal F1 and a delay inverted signal F5 through the clock generation unit 120.

  As shown in FIG. 4, the outputs of the DS conversion circuit that processes the outputs of the voltage controlled delay element 111a and the voltage controlled delay element 111e are divided and output by buffers 121a, 1211b, 121c, and 121d, respectively. . The buffers 121a to 121d have a configuration as shown in FIG. When F00 input to the PFD 200 and F0 used as a delay signal are connected to the same potential, the load due to the signal line changes and an offset occurs between the timings of other signals, so buffers 121a to 121d are provided.

  The switching circuit 130 switches and outputs one of the signals output from the clock generation circuit 120 other than the signals F00 and F00A according to the switching signal CNT. That is, the switching circuit 130 functions as an output signal switching unit. As described in FIG. 1, the switching circuit 130 included in the VCDL 101 outputs F2. In addition, the switching circuit 130 included in each VCDL 102 outputs F0.

  Next, the operation of the memory controller 1 according to this embodiment will be described. As described above, F00 and F00A that are outputs of the VCDL 100 are input to the PFD 200. Here, F00A is a signal generated based on the differential signals O0A and O4A obtained by further delaying the differential signals O4 and O0 that are the source of F00 by the voltage-controlled delay elements 111b to 111e. F00A is an inverted signal of a signal obtained by delaying the phase of F00 by a half cycle.

As described above, when the phase of F00A is delayed with respect to F00, the PFD 200 outputs a pulse of the phase difference between both signals from the UP. The CP 300 receives the UP pulse and outputs a positive pulse to the output CPO. The loop filter 400 smoothes the positive pulse input from the CP 300 and increases the voltage of the control voltage VCO. The bias circuit 500 outputs P _cnt and N _cnt so as to increase the amount of current supplied to the VCDL 100 as the control voltage VCO increases. As a result, the amount of delay in the voltage-controlled delay element 111 in each stage included in the delay signal generation circuit 110 is reduced.

On the other hand, when the phase of F00A is advanced with respect to F00, PFD200 outputs a pulse of a phase difference between both signals from DN. In response to the pulse of CP300DN, a negative pulse is output to the output CPO. The loop filter 400 smoothes the negative pulse input from the CP 300 and decreases the voltage of the control voltage VCO. The bias circuit 500 outputs P _cnt and N _cnt so as to reduce the amount of current supplied to the VCDL 100 by decreasing the control voltage VCO. As a result, the amount of delay in the voltage-controlled delay element 111 in each stage included in the delay signal generation circuit 110 increases.

When the master DLL 30 repeats such operations and the phases of F00 and F00A match, the PFD 200 stops outputting the UP and DN error signal pulses. In this state, the output of the CP 300 becomes high impedance, and the control voltage VCO of the loop filter 400 is held at a constant voltage. As a result, the voltages of P _cnt and N _cnt are fixed, and the delay amount in the voltage controlled delay element 111 in each stage included in the delay signal generation circuit 110 is fixed.

  Here, as described above, F00A is an inverted signal of the signal delayed by the voltage-controlled delay element 111 in four stages from F00. That is, the operation of matching the phases of F00 and F00A by the PFD 200 is synonymous with the operation of maintaining the phase difference between the signal output from the voltage controlled delay element 111a and the signal output from the voltage controlled delay element 111e at 180 °. is there.

  In this case, as described above, the delay amount in each voltage-controlled delay element 111 is equal, and from the differential signal output from the voltage-controlled delay element 111a to the differential signal output from the voltage-controlled delay element 111e, The signal is delayed by the four voltage-controlled delay elements 111b, 111c, 111d, and 111e. Therefore, the amount of delay in the voltage controlled delay elements 111b to 111e is 180 ° divided into four, which is 45 °. Therefore, F1 is a signal obtained by delaying the phase of F00 by 45 °, and F2 is a signal obtained by delaying the phase of F1 by 45 °.

  FIG. 8 shows a timing chart of each signal when the phases of F00 and F00A coincide. As shown in FIG. 8, F1 to F4 are signals obtained by delaying F0 stepwise by 45 degrees. F5, F6, F7, and F00A are signals obtained by inverting F1, F2, F3, and F4, respectively.

  Using the signals F1 to F4 generated in this way, the timing of DQS and DQ can be suitably controlled. As described with reference to FIG. 1, the data signal control circuit 50 uses F0 among the outputs of the VCDL 102. On the other hand, the strobe signal control circuit 40 uses F2 of the output of the VCDL 101. As shown in FIG. 8, since F2 is a signal whose phase is delayed by 90 ° with respect to F0, the timing of the strobe signal can be suitably maintained with respect to the data signal.

  Further, by switching the output of the switching circuit 130 to any one of F0 to F4, the timing of DQ0 to DQ7 can be adjusted up to 180 ° in units of 45 °. For example, when the timing of the data signals DQ0 to DQ7 is shifted at the stage of input to the memory controller 1, the switching signal CNT is controlled to switch the output of the switching circuit 130 to F0 to F4. The deviation between the signals can be adjusted. Such a function is particularly effective in a DDR (Double Data Rate) 3 memory module having an operating frequency as high as 800 MHz or higher.

  According to the present embodiment, among the signals output from the VCDL, the signal timing of F00 and the signal timing of F00A, which is an inverted signal of the signal delayed from F00 by a plurality of delay elements, coincide with each other. The delay amount of the delay element is controlled. As a result, a phase difference of 180 ° can be controlled by a plurality of stages of delay elements, and a high-precision and high-resolution multiphase clock can be realized with a small circuit scale and low power consumption.

  As described above, in this embodiment, delayed signals at 45 ° intervals are generated by adjusting the phase difference of the signals delayed in four stages to 180 degrees. Therefore, the delay signal generation circuit 110 needs to include at least four voltage controlled delay elements. Further, by providing the voltage controlled delay element 111f as the termination of the delay elements in a plurality of stages, the output load and the slew rate of the two signals F00 and F00A for phase comparison can be made equal, so the cause of the phase offset of both signals Can be reduced.

  Similarly, the differential signal input to the leading voltage control delay element 111a is not input to the clock generation unit 120 and converted to a single end signal, but the signal output from the voltage control delay element 111a is converted to a single end signal. By converting, it is possible to equalize the output load and slew rate of the two signals F00 and F00A for phase comparison, so that the cause of the phase offset of both signals can be reduced.

  In addition, since the circuits in which F00 and F00A are generated have the same circuit configuration, the output load and the slew rate of the two signals to be phase-compared can be made equal, so that the cause of the phase offset of both signals can be reduced. .

  Further, in the memory controller 1 according to the present embodiment, since the strobe signal control circuit 40 and the data signal control circuit 50 use the VCDLs 101 and 102 having the same configuration, it is possible to prevent a signal offset due to a difference in circuit. it can. As a result, the strobe signal can be delayed by 90 ° with respect to the data signal with high accuracy.

  Further, in the memory controller 1 according to this embodiment, as described above, the timing of each data signal DQ0 to DQ7 and the timing of the strobe signal can be adjusted. Here, when the timing of the data signal DQ is delayed by 135 ° from F0, that is, when it is adjusted using the signal of F3, it is necessary to make the timing of the strobe signal delayed by 225 ° from F0. In this case, in the configuration of the VCDL 101 according to the present embodiment, the signal cannot be delayed more than 180 °.

  However, in a signal such as a strobe signal in which “High” and “Low” are alternately repeated, a signal delayed by 225 ° is synonymous with an inverted signal of the signal delayed by 45 °. Therefore, as signals obtained by delaying the strobe signal DQS by 180 ° or more, the signals F5, F6, and F7 can be used as delayed signals of 225 °, 270 °, and 315 °, respectively. With such a configuration, it is possible to provide a suitable memory controller 1 that makes use of the write leveling function defined in the DDR3-SDRAM.

  Moreover, in the memory controller 1 according to the present embodiment, it is possible to suitably perform a loopback test. The loopback test is a circuit (hereinafter referred to as a read circuit) that performs a read operation from a memory module by using write data output from a circuit (hereinafter referred to as a write circuit) that controls a write operation to be written to the memory module. This is a test for confirming the consistency between the input data and the write data.

  In general, a write circuit included in a controller of a memory module is designed on the assumption that the phase of the strobe signal is delayed by 90 ° from the phase of the data signal and is output to the memory module. Therefore, the loopback test is executed by holding the write data in the read circuit in accordance with the strobe signal output from the write circuit.

  However, a general read circuit is designed on the assumption that the strobe signal and the data signal are input in a synchronized state. As described above, the same applies to the memory controller 1 according to the present embodiment. Therefore, in the execution of the loopback test, it is necessary to adjust the timing of the strobe signal and the data signal.

  The memory controller 1 according to the present embodiment can suitably cope with such a problem. That is, when the loopback test is executed, the data signal looped back according to the strobe signal looped back is controlled by controlling the switching signal CNT input to the switching circuit 130 and switching the output of the switching circuit 130. Can be held. Specifically, this is possible by switching the output of the VCDL 101 from F2 to F0.

  Further, when a circuit that is not related to the actual operation of the memory controller 1 is used when the loop back test is executed, the test is performed in a state different from the actual operation state of the memory controller, and the reliability of the loop back test is increased. Sex is reduced. In response to such a problem, the VCDL 101 and the VCDL 102 are circuits related to the actual operation, so that they are not greatly different from the actual operation state, and the reliability of the loopback test can be maintained.

  The problems related to the loopback test are not limited to the controller of the memory module of the DDR3 standard, but the same applies to other DDR standards such as DDR2-SDRAM and DDR-SDRAM. Therefore, by applying this case to a controller of a memory module other than the DDR3 standard, the same effect as described above can be obtained.

Embodiment 2. FIG.
In the present embodiment, an example of the memory controller 1 in which the input mode of the differential signal CLK _DIF to the master DLL 30 is different from that in the first embodiment will be described. In addition, about the structure which attaches | subjects the code | symbol similar to Embodiment 1, it shall show the same or an equivalent part, and abbreviate | omits detailed description.

FIG. 9 is a block diagram showing a configuration of the memory controller 1 according to the present embodiment. As shown in FIG. 9, the memory controller 1 according to the present embodiment includes a PLL 60 instead of the PLL 10, and the PLL 60 generates a differential signal CLK _DIF and inputs it to the master DLL 30. That is, the PLL 60 functions as a reference clock output unit.

  FIG. 10 shows the configuration of the PLL 60 according to this embodiment. As shown in FIG. 10, the PLL 60 has the same circuit configuration as the master DLL 30. The PLL 60 includes a differential ring oscillator 61, a DS conversion circuit 62, a buffer 63, and a frequency divider circuit 64.

The PFD 200, CP 300, loop filter 400, and bias circuit 500 included in the PLL 60 function in the same manner as those included in the master DLL 30 described in the first embodiment. Here, the PFD 200 is different from the first embodiment in that the input clock CLK _IN input to the PLL 60 and the output of the frequency dividing circuit 64 are compared to output either the error signal UP or DN. The PFD 200 compares CLK _IN and the output of the frequency dividing circuit 64, and outputs an error signal UP if the phase of CLK _IN is advanced. On the other hand, if the phase of the output of the frequency dividing circuit 64 is advanced, an error signal DN is output. That is, the PFD 200, the CP 300, the loop filter 400, and the bias circuit 500 function as a control signal generation unit that outputs a control signal.

The differential ring oscillator 61 is an oscillation circuit that outputs a differential signal according to the voltage values of P _cnt and N _cnt output from the bias circuit 500. The differential ring oscillator 61 is configured by connecting a plurality of delay elements identical to the voltage control delay element 111 described in FIG. 5 and FIG. 6 of the first embodiment in series, and the output of the final stage is the delay element of the front stage. It has a loop structure that is input to.

The DS converter 62 converts the differential signal output from the differential ring oscillator 61 into a single-ended signal and outputs it as CLK _MEM . That is, the DS converter 62 functions as a memory clock generation unit. The CLK _MEM output from the DS converter 62 is input to the frequency divider circuit 64 in addition to being output to the outside. The buffer 63 is provided to prevent the load of the differential signal output from the differential ring oscillator 61 from increasing and the transition time of CLK _DIF output to the outside from becoming long. That is, the buffer 63 functions as a reference clock generation unit. When the buffer 63 is omitted, an output wiring for extracting CLK _DIF functions as a reference clock generation unit.

The frequency dividing circuit 64 outputs a signal obtained by dividing the frequency of the output signal of the DS converter 62 in accordance with the set frequency dividing ratio. For example, when the frequency of the output signal of the DS converter 62 is 100 (MHz) and the frequency dividing ratio is 1/10, the frequency dividing circuit 64 outputs a signal having a frequency of 10 (MHz). With such a configuration, the PLL 60 outputs CLK _MEM that is a single-ended signal and CLK _DIF that is a differential signal at a frequency corresponding to the frequency dividing ratio of the frequency dividing circuit 64.

  With such a configuration, since the clock supplied from the PLL 60 to the master DLL 30 is supplied as a differential signal, noise resistance against common mode noise such as power supply voltage fluctuation is improved, and the jitter of the reference clock that is the source of delay control is increased. As a result, delay control can be performed with higher accuracy.

  The present invention is not limited to the above embodiment. That is, various modifications can be made without departing from the scope of the present invention.

1 Memory controller 10 PLL
20 Single / differential converter 30 Master DLL
40 Strobe signal control circuit 50 Data signal control circuit 60 PLL
100, 101, 102 VCDL
110 Delay signal generation circuit 111, 111a, 111b, 111c, 111d, 111e, 111f Voltage control delay element 112, 113 p-type transistor 114, 115, 116 n-type transistor 120 Clock generator 121a, 121b, 121c, 121d buffer 200 PFD
300 CP
301 p-type transistor 302 n-type transistor 303 current source 304 current source,
400 loop filter 500 bias circuit 501 variable current source 502, 503 p-type transistor 504 n-type transistor

JP 2008-236064 A

Claims (9)

A controller of a memory module having a function of judging a timing of a received memory clock signal and a strobe signal and outputting a judgment result;
A delay control signal output unit for outputting a delay control signal for controlling a delay of a signal input from the memory module;
A strobe signal delay control unit that delays the strobe signal input from the memory module and outputs the delayed strobe signal;
A data signal delay control unit that delays a data signal input from the memory module and outputs the delayed data signal as a delayed data signal;
The delay control signal output unit is
A delay signal output unit that outputs a plurality of delay signals having different delay intervals based on a reference clock input as a differential signal;
A delay control signal generation unit that compares two signals included in the plurality of delay signals and generates the delay control signal according to a phase difference between the two signals;
The delayed signal output unit is
A delay generation unit having a plurality of voltage-controlled delay elements connected in series, each of which is a delay element having a differential configuration and outputs an input signal with a delay interval corresponding to the delay control signal;
A delay signal generation unit configured to generate the plurality of delay signals by converting the differential signals output from the plurality of voltage-controlled delay elements connected in series to single-ended signals;
An output signal switching unit that switches and outputs the plurality of delay signals generated by the delay signal generation unit,
The delay signal generation unit includes: a first delay signal obtained by converting a differential signal input to one of the plurality of voltage-controlled delay elements connected in series into a single-ended signal; and the first delay signal. A second delay signal obtained by converting a differential signal output from a voltage control delay element provided two or more stages later than a voltage control delay element that outputs a single-ended signal as the two signals,
The strobe signal delay control unit generates a plurality of delay signals having different delay intervals based on the strobe signal according to the delay control signal with the same configuration as the delay signal output unit, and generates the plurality of delay signals One of them as the delayed strobe signal,
The data signal delay control unit generates a plurality of delay signals having different delay intervals based on the data signal according to the delay control signal with the same configuration as the delay signal output unit, and generates the plurality of delay signals A controller for a memory module that outputs a signal having a delay interval different from that of the delayed strobe signal as the delayed data signal. The delay generation unit includes at least four voltage-controlled delay elements connected in series,
The delay signal generation unit converts a differential signal input to a voltage control delay element provided at the head of the four voltage control delay elements into the first delay signal, and the four voltage control delay elements A differential signal output from a voltage control delay element provided in the fourth is converted to the second delay signal,
The delay control signal generation unit generates the delay control signal so that a difference between a phase of the first delay signal and a phase of the second delay signal becomes a predetermined interval. The controller of the memory module according to Item 1.   The delay control signal generation unit is configured to detect a difference between a phase of the differential signal input to the voltage control delay element provided at the head and a phase of the differential signal output from the fourth voltage control delay element. The controller of the memory module according to claim 2, wherein the delay control signal is generated so as to have a half cycle. The delay signal generation unit outputs one of the first delay signal and the second delay signal as a signal obtained by inverting the phase of the original differential signal,
The controller of the memory module according to claim 3, wherein the delay control signal generation unit generates the delay control signal so that rising timings of the two signals coincide with each other. The strobe signal delay control unit converts a signal obtained by converting a differential signal output from a voltage control delay element provided second among the four voltage control delay elements into a single-ended signal, as the delay strobe signal. Output as
The data signal delay control unit converts a signal obtained by converting a differential signal input to a voltage control delay element provided at the head of the four voltage control delay elements into a single-end signal. The memory module controller according to claim 3, wherein the controller of the memory module is output as:   6. The memory module controller according to claim 2, wherein the delay signal generation unit further includes the same voltage control delay element connected in series before the four voltage control delay elements. .   7. The memory module controller according to claim 2, wherein the delay signal generation unit further includes the same voltage control delay element connected in series after the four voltage control delay elements.   The delay signal generation unit converts the differential signals respectively output from the plurality of voltage-controlled delay elements connected in series into two single-ended signals whose phases are inverted to generate the plurality of delay signals. 8. The memory module controller according to claim 1, wherein the controller is a memory module. A reference clock output unit for outputting the reference clock;
The reference clock output unit is
A differential ring oscillator including a plurality of voltage controlled delay elements;
A memory clock generator for converting a differential signal extracted from the ring oscillator into a single-ended signal and generating a memory clock signal to be input to the memory module;
A reference clock generation unit that outputs the differential signal extracted from the ring oscillator as the differential signal that is input to the delay control signal output unit;
A control signal generator for outputting a control signal for controlling a voltage control delay element included in the ring oscillator based on the generated memory clock signal and a clock signal input from the outside, The memory module controller according to claim 1.

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