KR20110012770A - Delay locked loop and operating method thereof - Google Patents

Delay locked loop and operating method thereof Download PDF

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KR20110012770A
KR20110012770A KR1020090070632A KR20090070632A KR20110012770A KR 20110012770 A KR20110012770 A KR 20110012770A KR 1020090070632 A KR1020090070632 A KR 1020090070632A KR 20090070632 A KR20090070632 A KR 20090070632A KR 20110012770 A KR20110012770 A KR 20110012770A
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South Korea
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clock signal
delay
signal
external clock
unit
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KR1020090070632A
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Korean (ko)
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김경훈
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주식회사 하이닉스반도체
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Publication of KR20110012770A publication Critical patent/KR20110012770A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The present invention relates to a delay locked loop (DLL) for generating an internal clock signal for use in a semiconductor memory device. The present invention relates to an input buffering means for receiving and buffering an external clock signal and an output of the input buffering means. Variable delay means for delaying and outputting a signal by a time corresponding to a delay control signal, Output driving means for receiving the output signal of the variable delay means and outputting it as a DLL clock signal, Transmission path of the output signal of the variable delay means A delay replication modeling means for delaying the output signal of the variable delay means as a modeled time and outputting it as a feedback clock signal, a phase comparison means for comparing a phase difference between the external clock signal and the feedback clock signal, and A retarder for generating the delay control signal in response to an output signal of the phase comparing means It provides a delay lock loop and means.

Delay Locked Loop, Jitter, and Delayed Replication Modeling

Description

DELAY LOCKED LOOP AND OPERATING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a delay locked loop (DLL) for generating an internal clock signal for use in a semiconductor memory device and a method of operating the same.

In general, a semiconductor memory device including DDR SDRAM (Double Data Rate Synchronous DRAM) generates an internal clock signal by receiving an external clock signal, and uses it as a reference for adjusting various operation timings in the semiconductor memory device. Therefore, an internal clock signal generation circuit for generating an internal clock signal is provided in the semiconductor memory device, and a typical delay locked loop (DLL) and a phase locked loop (PLL) are included in the circuit.

1 is a block diagram illustrating a conventional delay locked loop.

Referring to FIG. 1, the delay locked loop includes an input buffering unit 110, a variable delay unit 120, an output driving unit 130, a delay replication modeling unit 140, a phase comparison unit 150, And a delay control unit 160.

The input buffering unit 110 buffers the external clock signal CLK_EXT and outputs the buffered signal to the variable delay unit 120 and the phase comparator 150. The variable delay unit 120 delays the output signal of the input buffering unit 110 by a time corresponding to the delay control signal CTR_DLY and outputs the delayed signal. The output driving unit 130 receives the output signal of the variable delay unit 120 and outputs it as a DLL clock signal CLK_DLL.

On the other hand, the output signal of the variable delay unit 120 is input to the delay replication modeling unit 140. The delay replication modeling unit 140 models a clock path and a data path inside the semiconductor memory device, and the output signal of the variable delay unit 120 is delayed by the modeled time of the delay replication modeling unit 140. And output as a feedback clock signal CLK_FED. In this case, the delay replication modeling unit 140 is designed by modeling the input buffering unit 110, the output driving unit 130, the transmission path of the DLL clock signal CLK_DLL, and the transmission path of data reflected when the data is output. do.

Subsequently, the phase comparison unit 150 compares the phase of the output signal of the input buffering unit 110 with the feedback clock signal CLK_FED and generates an output signal corresponding thereto. The delay controller 160 generates a delay control signal CTR_DLY in response to the output signal of the phase comparator 150.

The delay lock loop generates a delay control signal CTR_DLY that allows the output signal of the input buffering unit 110 and the phase of the feedback clock signal CLK_FED to be in phase with each other, and the corresponding DLL is generated. Generates a clock signal CLK_DLL. Create Here, a state in which these two phases are equal to each other is called 'locking'. In the delay locked loop, the locked DLL clock signal CLK_DLL is transmitted to a circuit for outputting data, and the data is output in synchronization with the transferred DLL clock signal CLK_DLL. The semiconductor memory device outputs data in response to the DLL clock signal CLK_DLL, which is an internal clock signal. As a result of the locking operation, the data is synchronized with the external clock signal CLK_EXT.

As shown in the figure, the external clock signal CLK_EXT is output as the DLL clock signal CLK_DLL through the input buffering unit 110, the variable delay unit 120, and the output driving unit 130. That is, the delay time of the input buffering unit 110, the delay time of the variable delay unit 120, and the delay time of the output driving unit 130 are outputted when the external clock signal CLK_EXT is output as the DLL clock signal CLK_DLL. This is reflected. Here, the delay time of the input buffering unit 110 and the output driving unit 130 is fixed while the delay time of the variable delay unit 120 is variable according to the circuit configuration and state. At this time, the delay amount of the variable delay unit 120 is defined as the delay amount of n × 1 tck-delayed replication modeling unit 140. Here, n is a natural number and 1tck is one period of the external clock signal CLK_EXT. The delay amount of the variable delay unit 120 should always be positive, so the n value of the variable delay unit 120 varies according to the delay amount of the delay replication modeling unit 140. The delay amount of the delay replication modeling unit 140 may vary depending on the circuit configuration to be modeled, and may also vary according to a process, a voltage, and a temperature.

If 1tck is 3ns and the delay amount of the delay replication modeling unit 140 is 2.1ns, the variable delay unit 120 controls the delay time within a range where n corresponds to 1. However, when the delay amount of the delay replication modeling unit 140 is 3.1n exceeding 1 tck, the variable delay unit 120 controls the delay time within a range where n corresponds to 2. The change range of the n value of the variable delay unit 120 is proportional to the range where jitter occurs. In recent years, when the operating frequency of the semiconductor memory device is designed to be increasingly high frequency, the range of change of the n value of the variable delay unit 120 becomes wider, and thus, the range of jitter also increases. When jitter occurs in the DLL clock signal CLK_DLL, the semiconductor memory device may not guarantee stable synchronization with data.

The present invention has been proposed to solve the above problems, and an object thereof is to provide a delay locked loop capable of minimizing a circuit configuration modeled in the delay locked loop.

In addition, an object of the present invention is to provide a delay locked loop capable of minimizing a time that an external clock signal is output as a DLL clock signal.

According to an aspect of the present invention, a delay locked loop includes: an input buffering means for receiving and buffering an external clock signal; Variable delay means for delaying and outputting the output signal of the input buffering means by a time corresponding to a delay control signal; Output driving means for receiving the output signal of the variable delay means and outputting it as a DLL clock signal; Delay replication modeling means for modeling a transmission path of the output signal of the variable delay means and delaying the output signal of the variable delay means as a modeled time and outputting it as a feedback clock signal; Phase comparison means for comparing a phase difference between the external clock signal and the feedback clock signal; And delay control means for generating the delay control signal in response to the output signal of the phase comparing means.

According to another aspect of the present invention, there is provided a method of driving a delay locked loop, the method including: outputting a DLL clock signal by reflecting only a time corresponding to a delay control signal to a signal buffered with an external clock signal; Generating a feedback clock signal by reflecting the modeled time corresponding to the transmission path of the DLL clock signal to the DLL clock signal; And directly comparing the feedback clock signal with an external clock signal to be compared, and generating the delay control signal according to the result.

In the delay lock loop according to the embodiment of the present invention, it is possible to minimize the chip size and the power consumption of the semiconductor memory device by minimizing the modeling circuit designed in the circuit. In addition, it is possible to improve the jitter characteristic of the DLL clock signal by minimizing the time that the external clock signal is output as the DLL clock signal.

According to the present invention, by minimizing the time that the external clock signal is output as the DLL clock signal, the jitter range generated in the DLL clock signal can be reduced. In addition, the present invention can reduce the jitter range of the DLL clock signal, it is possible to obtain an effect that can ensure a stable synchronization operation of the DLL clock signal and data.

In addition, the present invention can minimize the chip size and power consumption of the semiconductor memory device by minimizing the modeling circuit designed in the delay lock loop.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2 is a block diagram illustrating a delay locked loop according to a first embodiment of the present invention.

Referring to FIG. 2, the delay locked loop may include an input buffering unit 210, a variable delay unit 220, an output driving unit 230, a delay replication modeling unit 240, a phase comparison unit 250, And a delay control unit 260.

The input buffering unit 210 buffers the external clock signal CLK_EXT and outputs the buffered signal to the variable delay unit 220. The variable delay unit 22 delays and outputs the output signal of the input buffering unit 210 by a time corresponding to the delay control signal CTR_DLY, and the output driving unit 230 outputs the output signal of the variable delay unit 220. It receives the input and outputs it as a DLL clock signal (CLK_DLL). Detailed circuit configurations of the input buffering unit 210 and the variable delay unit 220 will be described later with reference to FIG. 3.

On the other hand, the output signal of the variable delay unit 220 is input to the delay replication modeling unit 240. The delay replication modeling unit 240 models a clock path and a data path inside the semiconductor memory device, and the output signal of the variable delay unit 220 is delayed by the modeled time of the delay replication modeling unit 240 to feed back the feedback clock. It is output as a signal CLK_FED. The delay replication modeling unit 240 according to an exemplary embodiment of the present invention is designed by modeling the output driving unit 230, the transmission path of the DLL clock signal CLK_DLL, and the transmission path of data reflected when outputting data. That is, the delay replication modeling unit 240 does not include a modeling circuit corresponding to the input buffering unit 210, thereby reducing the chip size and power consumption of the semiconductor memory device.

Next, the phase comparator 250 compares the phases of the external clock signal CLK_EXT and the feedback clock signal CLK_FED and generates an output signal corresponding thereto. In the delay lock loop according to the exemplary embodiment of the present invention, the external clock signal CLK_EXT input to the input buffering unit 210 is directly input to the phase comparator 250. Therefore, the configuration that is modeled in the delay replication modeling unit 240 does not need to include the input buffering unit 210, and changes the range of n value of the variable delay unit 220 relative to the delay amount of the delay replication modeling unit 240. It is possible to reduce. Decreasing the n value of the variable delay unit 220 means that the time for which the external clock signal CLK_EXT is output as the DLL clock signal CLK_DLL after locking is reduced, which means that the jitter generated in the DLL clock signal CLK_DLL is reduced. It means that the range is reduced.

3 is a circuit diagram illustrating the input buffering unit 210 and the variable delay unit 220 of FIG. 2.

Referring to FIG. 3, first, the input buffering unit 210 includes a loading unit 310A, an input unit 310B, and a current sourcing unit 310C.

The loading unit 310A includes a resistor connected between a power supply voltage VDD terminal and an input terminal 310B, the input unit 310B includes a transistor for receiving external clock signals CLK_EXT and / CLK_EXT, and a current sourcing unit The 310C includes a transistor for receiving the power down mode signal PWM and the bias voltage V_BIS. Here, the external clock signals CLK_EXT and / CLK_EXT are externally applied signals and are divided into a positive external clock signal CLK_EXT and a negative external clock signal / CLK_EXT. The positive external clock signal CLK_EXT and the negative external clock signal / CLK_EXT are signals that are out of phase with each other, and the input buffering unit 210 differentials the positive external clock signal CLK_EXT and the negative external clock signal / CLK_EXT. Receives the signal and performs the differential amplification operation. The power down mode signal PWD is a mode for reducing power consumption in the semiconductor memory device. When the power down mode signal is entered, the power down mode signal PWD is activated to turn off the corresponding transistor. The buffering operation of the input buffering unit 210 is deactivated. For reference, the bias voltage V_BIS has a predetermined voltage level.

In general, the positive / negative external clock signals CLK_EXT and / CLK_EXT applied from the outside have a current mode logic (CML) level, and most of them operate at a complementary metal oxide semiconductor (CMOS) level in a semiconductor memory device. The input buffering unit 210 converts the positive / negative external clock signals CLK_EXT and / CLK_EXT applied to the CML level to the CMOS level.

Next, the variable delay unit 220 includes first to fourth delay cells 330, 350, 370, and 390. Each of the first to fourth delay cells 330, 350, 370, and 390 is similar to each other, and the first delay cell 330 will be described below.

The first delay cell 330 includes a loading unit 330A, an input unit 330B, and a current sourcing unit 330C.

The loading unit 330A includes a resistor and a transistor connected between a power supply voltage VDD terminal and an input terminal 330B. Here, each transistor receives the delay control signal CTR_DLY and varies the resistance of the loading unit 330A according to the voltage level of the delay control signal CTR_DLY. Here, the change in the resistance value of the loading unit 330A means the change in the delay amount of the first delay cell 330.

Meanwhile, the input unit 310B includes a transistor configured to receive an output signal of the input buffering unit 210 to the first input terminal IN and the second input terminal / IN. The current source 320C includes a transistor for receiving the power down mode signal PWM and the bias voltage V_BIS.

The first delay cell 330 delays the signal output from the input buffering unit 210 by a time corresponding to the delay control signal CTR_DLY and outputs the first and second output terminals OUT and / OUT. The signal output from the first delay cell 330 is output through the second to third delay cells 350, 370, and 390. The first to fourth delay cells 330, 350, 370, and 390 also control the delay operation in response to the power down mode signal PWM. Here, the delay control signal CTR_DLY has a voltage level corresponding to the signal output from the phase comparator 250.

Referring back to FIG. 2, the external clock signal CLK_EXT is output as a DLL clock signal CLK_DLL through the input buffering unit 210, the variable delay unit 220, and the output driver 230. It can be said that the path is the same as before when the external clock signal CLK_EXT is transmitted. However, in the delay lock loop according to the exemplary embodiment of the present invention, since the external clock signal CLK_EXT input to the phase comparator 250 is also input to the input buffering unit 210, the delay lock loop may be modeled in the delay replication modeling unit 240. It is not necessary to design the input buffering unit 210 in the configuration. This means that the amount of delay reflected by the delay replication modeling unit 240 is reduced.

As described above, the delay amount of the variable delay unit 220 is defined as the delay amount of the n × 1 tck-delay replication modeling unit 240. Therefore, reducing the amount of delay reflected by the delay replication modeling unit 240 means that the amount of delay reflected by the variable delay unit 220 can be reduced by that much.

In the description of FIG. 1, a case in which 1 tck is 3 ns and a delay amount of 2.1 ns and 3.1 ns including the delay amount of the input buffering unit is described. For convenience of explanation, a case where the delay amount of the input buffering unit 210 is 0.4 ns will be described as an example. Since the delay replication modeling unit 240 according to the embodiment of the present invention does not have to consider the delay amount of the input buffering unit 210, the delay amounts of the delay replication modeling unit 240 are 1.7 ns and 1 in the same situation as above. 2.7ns.

First, when the delay amount of the delay replication modeling unit 240 is 1.7 ns, the delay time is controlled in the variable delay unit 220 within a range where n corresponds to one. Subsequently, when the delay amount of the delay replication modeling unit 240 is 2.7 ns, the variable delay unit 220 also controls the delay time within a range where n value corresponds to 1. As can be seen, in the delay locked loop according to the embodiment of the present invention, the n value of the variable delay unit 220 does not change. That is, even if the circuit modeled by the delay replication modeling unit 240 increases by a predetermined amount as much as the input buffering unit 210, the n value may be maintained at 1. Therefore, the time for which the external clock signal CLK_EXT is output as the DLL clock signal CLK_DLL is reduced, and the range in which jitter occurs in the DLL clock signal CLK_DLL is reduced.

4 is a block diagram illustrating a delay locked loop according to a second embodiment of the present invention. Compared to the first embodiment, the second embodiment further includes a level converter 410 and a delay unit 430. For convenience of description, only added components will be described. In the case of the second embodiment, the phase comparator 450 may be applied when operating at a CMOS level.

Referring to FIG. 4, the level converter 410 converts the external clock signal CLK_EXT applied to the CML level to the CMOS level, and the delay unit 430 is the external clock signal CLK_EXT by the level converter 410. The delayed feedback clock signal CLK_FED is delayed by the delay time reflected by the output. Here, the circuit configuration of the delay unit 430 may be various, but preferably has the same structure as the level converter 410.

For reference, although the configuration of the level converter 410 and the delay unit 430 is increased compared to the first embodiment, the additional circuit of the delay replication modeling unit 470 is not necessary, and the delay control signal CTR_DLY is required. It is also output at the same value as in the first embodiment.

As described above, in the delay lock loop according to the exemplary embodiment of the present invention, the input buffering unit may be removed from the circuit configuration modeled by the delay replication modeling unit by directly comparing the external clock signal with the feedback clock signal. Therefore, the area of the input buffering unit designed in the delay replication modeling unit can be reduced compared to the existing configuration, and the power consumed by the input buffering unit can be reduced.

In addition, it is possible to reduce the change in the n value of the variable delay unit corresponding to the circuit configuration modeled by the delay replication modeling unit, thereby reducing the range in which jitter occurs in the DLL clock signal CLK_DLL. Therefore, it is possible to generate a stable DLL clock signal (CLK_DLL), it is possible to ensure a stable data synchronization operation.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

In the above-described embodiment, the delay control signal CTR_DLY has an example of a voltage level corresponding to a phase difference between the external clock signal and the feedback clock signal, that is, an analog value. However, the present invention can be applied to the case where the delay control signal CTR_DLY has a digital value instead of an analog value, and in this case, the delay control signal CTR_DLY can be a plurality of delay control signals having a digital value. Subsequently, the variable delay unit may be configured of a plurality of unit delay cells in which a delay operation is activated by receiving a plurality of delay control signals, respectively.

In addition, the position and type of the logic gate and the transistor illustrated in the above-described embodiment should be implemented differently according to the polarity of the input signal.

1 is a block diagram illustrating a conventional delay locked loop.

2 is a block diagram illustrating a delay locked loop according to a first embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating the input buffering unit 210 and the variable delay unit 220 of FIG. 2.

4 is a block diagram illustrating a delay locked loop according to a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

210: input buffering unit 220: variable delay unit

230: output driving unit 240: delayed replication modeling unit

250: phase comparison unit 260: delay control unit

Claims (13)

Input buffering means for receiving and buffering an external clock signal; Variable delay means for delaying and outputting the output signal of the input buffering means by a time corresponding to a delay control signal; Output driving means for receiving the output signal of the variable delay means and outputting it as a DLL clock signal; Delay replication modeling means for modeling a transmission path of the output signal of the variable delay means and delaying the output signal of the variable delay means as a modeled time and outputting it as a feedback clock signal; Phase comparison means for comparing a phase difference between the external clock signal and the feedback clock signal; And Delay control means for generating the delay control signal in response to the output signal of the phase comparing means A delay locked loop comprising: The method of claim 1, Level converting means for converting the external clock signal applied at a current mode logic (CML) level to a complementary metal oxide semiconductor (CMOS) level; And And a delay means for delaying and outputting the feedback clock signal by a delay time reflected by the external clock signal by the level converting means. The method of claim 2, And the delay means has the same configuration as the level converting means. The method of claim 1, The external clock signal includes a positive external clock signal and a negative external clock signal, the phase of which is opposite to the positive external clock signal. And the input buffering means receives the positive / negative external clock signal differentially and performs a differential amplification operation. The method of claim 1, The variable delay means, And a delay cell whose delay amount is determined in response to the analog delay control signal. The method of claim 1, The variable delay means, And a plurality of unit delay cells in which a delay operation is activated in response to the delay control signal of the digital type. Outputting a DLL clock signal by reflecting the external clock signal buffered by the time corresponding to the delay control signal; Generating a feedback clock signal by reflecting the modeled time corresponding to the transmission path of the DLL clock signal to the DLL clock signal; And Directly comparing the feedback clock signal with an external clock signal to be compared and generating the delay control signal according to the result; Method of driving a delay locked loop comprising a. The method of claim 7, wherein And driving the signal delayed by the time corresponding to the delay control signal to the DLL clock signal. The method of claim 8, And a delay time reflected in the driving step is included in the modeled time of generating the feedback clock signal. The method of claim 7, wherein Converting the external clock signal applied at a current mode logic (CML) level to a complementary metal oxide semiconductor (CMOS) level; And And delaying the feedback clock signal by a delay time reflected in the converting step. The method of claim 7, wherein The external clock signal includes a positive external clock signal and a negative external clock signal, the phase of which is opposite to the positive external clock signal. And receiving the positive / negative external clock signal differentially and performing a differential amplification operation. The method of claim 7, wherein The outputting of the DLL clock signal may include a delay amount reflected in a signal buffering the external clock signal in response to the analog control delay control signal. The method of claim 7, wherein The outputting of the DLL clock signal may include determining a delay amount reflected in a signal buffering the external clock signal in response to the digital delay control signal.
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