JPH11112485A - Device and method adjusting delay time between plural transmitting lines - Google Patents

Abstract

PROBLEM TO BE SOLVED: To satisfactorily adjust the phase deviation of signals between all the transmission lines even when the signal propagation delay time exceeds one period of a clock signal by detecting a delay quantity between the signals of the respective transmission lines within a set synchronizing cycle and adjusting the signal propagation delay time of the respective transmission lines. SOLUTION: A synchronizing event generating means 16 outputs a synchronizing cycle signal and a synchronizing signal generating means 17 generates a synchronizing signal. A data generating means 4 generates data A to D for a test and data A to D and the synchronizing signal is transmitted from a data outputting means 5 to transmission lines 1a to 1e. A synchronization detecting means 18 calculates time τ1 to τ4 from the receiving time of the synchronizing signal to the reaching time of each data A to D. A master 15 calculates difference between its maximum time and each time τ1 to τ4 and phase deviation between the respective obtained data A to D is set as τA to τD. A delay value setting means 19 controls timing adjusting mechanisms 10a to 10d to this delay time τA to τD to insert.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention adjusts a different delay time for each transmission line when a plurality of transmission lines are used to transmit signals simultaneously using a plurality of transmission lines. The present invention relates to an improvement of a delay time adjusting device between a plurality of transmission lines and an improved delay time adjusting method.

[0002]

2. Description of the Related Art Generally, a plurality of signal transmission lines have different signal propagation delay times, so that a skew occurs in a signal to be propagated. For example,
When a plurality of data are transmitted to the same receiving unit, a difference occurs when these data reach the receiving unit. Also, when transmitting the same signal (for example, a clock signal) to a plurality of receiving units, there is a difference between each receiving unit when the receiving unit receives the signal. This skew is 1
This occurs both when a signal is transmitted inside one LSI and when a signal is transmitted between a plurality of LSIs. When skew occurs, a malfunction of the LSI may occur.

For this reason, conventionally, for example, Japanese Patent Application Laid-Open No. 7-7
As disclosed in Japanese Patent No. 3118, a synchronous circuit is provided, and when a phase shift occurs between signals received through a plurality of transmission lines, another signal is transmitted based on the signal of one transmission line with the longest delay. By arranging a predetermined delay element on the transmission line to absorb the phase shift, the phase shift between these signals is adjusted.

[0004] Conventionally, for example, Japanese Patent Laid-Open No. 6-54016
In the technique disclosed in Japanese Patent Application Laid-Open Publication No. H11-264, when a plurality of data are transmitted using the same number of transmission lines, the data fetch timing in a receiving unit (flip-flop) of these data, that is, to these flip-flops The input timing of the clock signal is adjustable, and a clock signal is input after all the data is received, so that a plurality of data are received by the receiving unit at the same time.

[0005]

The recent LS
When data is transferred in parallel using a plurality of transmission lines with the increase in the speed of operations such as I, the transfer rate is 550 M
Some require a high-speed signal transmission of B / sec (that is, 250 MHz) or more.
In one signal transmission, one cycle is 2 nanoseconds or less.

However, such a high-speed operating L
When adjusting a phase shift due to signal skew in SI or the like, the above-described conventional technique cannot be applied.

That is, in the former prior art, since the phase difference between the signal waveforms received at a plurality of locations is detected, if one cycle of the clock signal is T, the phase shift between the received signal waveforms is T / T. If it is less than 2, the phase shift can be adjusted, but for example, as shown in FIG. 14A, of the three signals A, B, and C, the phase shift between two signals A and C is T / C. 2, the signal C is shifted by one period T with respect to the signal A as shown in FIG. In such a situation, for example, if there is a shift of 10 cm between the transmission lines, a phase shift of 2 nanoseconds occurs at a load of 40 pF, and the phase shift is 5 ns.
Since the signal transmission of 00 MHz is one cycle or more,
It turns out that it can be easily assumed.

In the latter prior art, the reception timing of the clock signal is adjusted so that the clock signal is received after the reception of a plurality of data. Therefore, the phase delay of any data exceeds one cycle. In this case, at the time of receiving this data, other data may have already changed to the value of the next cycle, and therefore, it is impossible to adjust the data fetch time to each flip-flop at the same time. . As described above, it is impossible to solve the signal skew in the LSI or the like that operates at a high speed with the above two conventional techniques.

An object of the present invention is to solve the above-mentioned conventional drawbacks. An object of the present invention is to provide a method for transmitting a signal to each transmission line simultaneously using a plurality of transmission lines in an LSI or the like operating at high speed. Even if the propagation delay time of a signal on any of the transmission lines exceeds one cycle, the phase skew of the signal between all the transmission lines is adjusted well, and the signal skew is adjusted to the cycle of the same cycle. is there.

[0010]

In order to achieve the above object, according to the present invention, when a plurality of transmission lines are used to transmit a signal in parallel to each transmission line, an original signal necessary for circuit operation and the like is required. Temporarily stops transmission, executes a predetermined synchronization cycle, and detects a phase shift of a signal between the transmission lines based on a predetermined point in time, thereby forming one cycle between signals received through the transmission lines. Even if the phase shift exceeds, the phase shift is appropriately adjusted to match the signal skew to the cycle of the same cycle.

That is, according to the first aspect of the present invention, there is provided an apparatus for adjusting a delay time between a plurality of transmission lines, wherein the plurality of signal output units are connected to the signal output unit, and output signals of the signal output unit are simultaneously transmitted. A transmission line, a signal receiving unit that receives a signal of each transmission line, and a signal propagation delay of each transmission line that is arranged in the middle of a path from the signal output unit to the signal reception unit via the plurality of transmission lines. Timing adjustment means for adjusting time, synchronization cycle setting means for setting a predetermined synchronization cycle, and within the synchronization cycle set by the synchronization cycle setting means, the signal output section simultaneously outputs and the signal reception section Delay amount detecting means for detecting a delay amount between received signals on each transmission line, and the timing adjustment based on a delay amount between signals on each transmission line detected by the delay amount detecting means Characterized in that a control means for controlling the stage.

According to a second aspect of the present invention, in the device for adjusting a delay time between a plurality of transmission lines according to the first aspect, the control means includes a delay between signals of each transmission line detected by the delay amount detection means. A delay amount determining means for determining a delay amount to be inserted into each transmission line, so that the signal receiving unit simultaneously receives the signals of the respective transmission lines, based on the amount, and each of the delay amounts determined by the delay amount determining means. A delay value setting unit that controls the timing adjustment unit so that the delay amount is inserted into a corresponding transmission line.

According to a third aspect of the present invention, in the device for adjusting a delay time between a plurality of transmission lines according to the first aspect, the synchronization cycle setting means sets a synchronization cycle at a predetermined time interval. I do.

According to a fourth aspect of the present invention, in the apparatus for adjusting a delay time between a plurality of transmission lines according to the first aspect, transmission of a signal to each transmission line is performed by adding a parity, and the synchronization cycle setting is performed. The means detects a transmission error of the signal received by the signal receiving unit based on the parity, and sets a synchronization cycle when the transmission error is detected.

According to a fifth aspect of the present invention, in the device for adjusting a delay time between a plurality of transmission lines according to the first aspect, a temperature sensor is provided in at least one of the signal output unit, the signal reception unit, and the plurality of transmission lines. The synchronous cycle setting means is arranged to set a synchronous cycle when the temperature sensor detects a change over a predetermined temperature.

According to a sixth aspect of the present invention, in the device for adjusting a delay time between a plurality of transmission lines according to the first aspect, the setting of the synchronization cycle by the synchronization cycle setting means is performed on a dedicated transmission line separately added. This is performed by transmitting a synchronization signal.

According to a seventh aspect of the present invention, in the device for adjusting a delay time between a plurality of transmission lines according to the first aspect, the setting of the synchronization cycle by the synchronization cycle setting means is simultaneously transmitted to each of the transmission lines. Signal for a predetermined period of time
This is performed by fixing the potential to a predetermined potential level.

According to an eighth aspect of the present invention, in the device for adjusting a delay time between a plurality of transmission lines according to the first aspect, the signal transmission between the signal output section and the signal receiving section is performed based on a predetermined protocol. The setting of the synchronization cycle by the synchronization cycle setting means is performed by the output of the protocol.

According to a ninth aspect of the present invention, in the device for adjusting a delay time between a plurality of transmission lines according to the first aspect, the timing adjusting means includes a plurality of delay elements and a combination of these delay elements. And a selection circuit for selecting.

According to a tenth aspect of the present invention, in the device for adjusting a delay time between a plurality of transmission lines according to the first aspect, the number of the timing adjustment units is equal to the number of the plurality of transmission lines. , Are arranged in the middle of the corresponding transmission line.

According to an eleventh aspect of the present invention, in the device for adjusting a delay time between a plurality of transmission lines according to the first aspect, the delay amount detecting means is simultaneously output from the signal output unit within a synchronous cycle, and The delay amount between the reference signal and the signal on the other transmission line with reference to the signal on one transmission line received by the signal receiving unit at the latest among the signals received by the signal receiving unit via each transmission line. Is detected.

According to a twelfth aspect of the present invention, in the device for adjusting a delay time between a plurality of transmission lines according to the first aspect, the output of the plurality of signals from the signal output unit is performed based on a clock signal, and The period of the synchronization cycle set by the cycle setting means exceeds one cycle of the clock signal.

According to a thirteenth aspect of the present invention, in the method for adjusting a delay time between a plurality of transmission lines, a synchronization cycle is set as a cycle for synchronizing signals on the plurality of transmission lines, The output signal of the output unit is simultaneously transmitted to a plurality of transmission lines, the signals of the plurality of transmission lines are received by a signal reception unit, and the signals of the transmission lines received by the signal reception unit in the synchronization cycle are output. Detecting the amount of delay, based on the detected amount of delay, so that the signal of each of the transmission lines simultaneously output from the signal output unit is received simultaneously by the signal receiving unit, the amount of delay of each transmission line, It is characterized by adjusting.

The invention according to claim 14 is the invention according to claim 13.
In the method of adjusting the delay time between a plurality of transmission lines described,
The period of the synchronization cycle may be longer than one cycle of the clock signal.

With the above configuration, according to the present invention, when one or a plurality of signals are transmitted in parallel using a plurality of transmission lines, a predetermined synchronization cycle is executed, and a plurality of transmission lines are transmitted within the synchronization cycle. Each signal is transmitted from the signal output at the same time. In the signal receiving section, the signal passing through each of the transmission lines is received, and the delay amount detecting means detects the delay amount between the signals received through these transmission lines. Here, since the period of the synchronization cycle is set to a period exceeding one cycle of the clock signal (for example, a plurality of cycles of the clock signal), the amount of delay between signals transmitted to each transmission line in the synchronization cycle is detected. , The propagation delay amount of the signal of any transmission line is 1
Even if the delay amount is longer than the period, it is possible to synchronize the signals received via the plurality of transmission lines with the cycle of the same period.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an apparatus for adjusting a delay time between a plurality of transmission lines according to an embodiment of the present invention.

In FIG. 1, 1a to 1e denote first to fifth five transmission lines, and 2 and 3 denote the transmission lines 1a to 1a.
e, a first and a second LSI connected to each other via an e. The first LSI 2 includes, for example, a processor or D
Data generating means 4 which is composed of SPs and generates four data at the same time, and outputs data (signals) generated by the data generating means 4 to four of the five transmission lines except the fifth transmission line 1e And data output means (signal output unit) 5 for outputting to the transmission lines 1a to 1d. The data output means 5 outputs a synchronization signal to the fifth transmission line 1e, as described later.

On the other hand, the second LSI 3 has the first LSI
And a data input means (data receiving unit) 6 for receiving the data transmitted to the fourth transmission lines 1a to 1d and the synchronization signal transmitted to the fifth transmission line 1e, and holding the received four data. Data holding means 7 is provided. The data holding means 7 is composed of, for example, a memory.

As can be seen from the figure, the transmission lines 1a to 1e extend rightward in the figure and then bend downward in the figure, so that the transmission lines 1a to 1e have a mutual line length. different. The transmission lines 1a to 1e have a timing adjustment mechanism (timing adjustment means) 10a to 10e, respectively.
e is arranged. These timing adjustment mechanisms 10a-
10e changes the signal propagation delay time of the corresponding transmission line. The timing adjusting units 10a to 10e have the same configuration, and the internal configuration is illustrated in FIG. In FIG. 1A, six inverter delay circuits (delay elements) 20a to 20f having a delay time τ are connected in series, and a line 2 that bypasses these six delay circuits 20a to 20f is used.
0g and the line 20 passing only through the first-stage delay circuit 20a.
h, a line 20i passing through the first and second delay circuits 20a and 20b, and delay circuits 20a to 20
c and a delay circuit 20a up to the fourth stage
20d passing through the delay circuits 20a through 20d, the line 201 passing through the delay circuits 20a through 20e up to the fifth stage, and all the delay circuits 2
0a to 20f, and any one of these seven lines 20g to 20m is connected to a selector (selection circuit) 2.
1, the delay amount of the corresponding transmission line is adjusted in seven stages. The selector 21 is controlled by a delay value setting signal from a delay value setting unit 19 described later. Note that the number of delay circuits is not limited to six. In addition, the configuration of the timing adjusting units 10a to 10e is not limited to FIG. 2A, and for example, as shown in FIG.
A plurality of lines (delay elements) having different lengths are selected by a plurality of (four in the figure) selectors (selection circuits) 22, and the selected lines are connected in series, and the transmission line is selected according to the length of the line. May be adjusted. Further, as shown in FIG. 3C, a plurality of (three in the figure) delay elements 23, a line bypassing them, and a plurality of (three in the figure) selectors for selecting these. (Selection circuit) 24
And the delay amount of the transmission line may be adjusted by the number of delay elements 23 connected in series.

In FIG. 1, reference numeral 15 denotes a master (synchronization cycle setting means) to which the data input means 6 is connected. Based on the data from 1d or periodically, it is determined whether or not to shift to the synchronization cycle to adjust the phase shift of each data, and when it is determined to shift to the synchronization cycle, a synchronization cycle determination signal is output. .

Further, reference numeral 16 denotes a synchronization event generating means, which generates a synchronization cycle signal in response to the synchronization cycle determination signal when the master 15 determines to shift to a synchronization cycle. 17 is a synchronizing signal generating means,
In response to the synchronization cycle signal generated by the synchronization event generation means 16, the synchronization signal shown in FIG.
Output to In the present embodiment, as shown in FIG.
A period in which the synchronization signal is at the L level is a synchronization cycle. The data output means 5 outputs the synchronization signal to the fifth transmission line 1.
e. The data generator 4 receives the synchronization cycle signal generated by the synchronization event generator 16 and simultaneously generates signals A to D shown in FIG. As shown in FIG. 6, the time points at which these signals A to D occur are delayed by a predetermined period from the time points at which the synchronization signal occurs. The generated signals A to D are transmitted by the data output means 5 to the first to fourth transmission lines 1a to 1d.

In addition, reference numeral 18 denotes synchronization detecting means. The synchronization detecting means 18 receives the data and synchronization signals transmitted to the transmission lines 1a to 1e via the data input means 6 in the synchronization cycle. Then, the synchronization signal is detected, and delay amounts τ1 to τ4 of the four received data are calculated based on the detection time. FIG. 3 shows the configuration of the synchronization detecting means (delay amount detecting means) 18. It should be noted that FIG. 2 shows only the configuration for data A,
The configuration for .about.D is omitted. In the figure, the synchronization detecting means 18 has six delay units 60a to 60f having a predetermined delay time τ connected in series, and a synchronization signal is input to the first stage delay unit 60a. The synchronization detecting means 18 includes seven two-input type AND circuits 71a to 71a.
1g, and the first AND circuit 71a receives the synchronization signal and the data A. The second to seventh AND circuits 71b to 71g include first to sixth stage delay units 60a.
60f, the output of the corresponding delay unit and the data A are input, respectively. Therefore, in the example of FIG. 4, the data A is output between the outputs of the third-stage and fourth-stage delay units 60c and 60d, that is, between the falling edges of both signals obtained by delaying the synchronization signal by the time 3τ and the time 4τ. AND circuits 71a to 71g
, And as shown in FIG.
Output of only the AND circuits 71a to 71d is at "H" level, and the remaining fifth to seventh AND circuits 71a to 71d
Becomes "L" level, and the combination (1111000) of the output states of these seven AND circuits indicates that the delay time of data A with respect to the synchronization signal is 3τ. Similarly, for example, when the combination is (1111100), the delay time is 4τ, and when the combination is (110000), 2τ, (1100
000), the delay time is (1,000,000)
0 "is detected.

Returning to FIG. 1, the master (delay value determining means) 15 receives the data delay amounts τ1 to τ4 of the transmission lines 1a to 1e detected by the synchronization detecting means 18,
Based on these delay amounts τ1 to τ4, the first to fourth
The delay values τA to τD to be inserted into the transmission lines 1a to 1d are determined respectively. Details of the operation of the master 15 will be described later using the flowchart shown in FIG.

Reference numeral 19 denotes a delay value setting means which receives the delay values τA to τD determined by the master 15 and inserts these delay values τA to τD into the corresponding transmission lines 1a to 1d. , Each of the timing adjusting means 10a-1
A delay value setting signal of several bits is output to 0d. As shown in FIG. 2A, when the delay value setting signal instructs the setting of the delay amount of 2τ, for example, as shown in FIG. The selector 21 performs a selecting operation by the delay value setting signal so as to select 20i. The master (delay value determining means) 15 and the delay value setting means 19 constitute a control means 50 of the present invention.

Next, the synchronization detecting means 18, the master 1
5 and the operation of the delay value setting means 19 will be described in detail with reference to the flowchart of FIG.

In FIG. 5, in step S1, it is determined that the master 15 enters a synchronization cycle. This decision
For example, it is performed every elapse of a predetermined time. At this time,
The synchronization event generating means 16 outputs a synchronization cycle signal, and a synchronization event is started. In step S2, a synchronization cycle is started by the start of a synchronization event.
That is, the synchronizing signal generating means 17 generates a "LOW" level synchronizing signal shown in FIG. The "LOW" level period is a period exceeding one cycle of the clock signal, specifically, four cycles of the clock signal as shown in FIG. 6, and this period is a synchronization cycle. Further, the data generating means 4
After a lapse of a predetermined period (for example, a period of one cycle of a clock signal) after the output of the “LOW” level synchronization signal,
The test data A to D shown in FIG. 1 are generated, and these data A to D and the synchronization signal are output from the data output means 5 to the first to the first data.
The signal is transmitted to the fifth transmission lines 1a to 1e.

Thereafter, at step S3, the synchronization detecting means 18 determines whether or not the "LOW" level synchronization signal has been received via the fifth transmission line 1e and the data input means 6, and this synchronization signal is detected. When the reception is detected, in step S4, the time when the synchronization signal is received is determined by the transmission lines 1a to 1a.
The reference point τo for calculating the signal delay amount at d.

Subsequently, in steps S5 to S8, the synchronization detecting means 18 determines whether or not the four data A, B, C, and D that have passed through the first to fourth transmission lines 1a to 1d have reached inside. If it is detected and each data arrives, steps S9-S
In step 12, the times τ1 to τ4 from the reception of the synchronization signal τo to the arrival of each data are calculated.

After step S12, step S1 is executed.
In step 3, the master (delay amount determining means) 15
Τ4, the longest time (time τ1 in FIG. 6) is extracted, and this time τ1 is set as the maximum time τmax. Next, in steps 14 to S17, the master 15
The difference between max and each of the times τ1 to τ4 is calculated, and the resulting phase shift between the data A to D is calculated as τA
(= Τmax-τ1 = 0), τB (= τmax-τ2), τC
(= Τmax−τ3) and τD (= τmax−τ4). Subsequently, in steps S18 to S21, the delay value setting unit 19
Sets the obtained phase shifts τA, τB, τC, and τD as delay times to be inserted into the first to fourth transmission lines 1a to 1d, and sets the phase shifts of the first to fourth transmission lines 1a to 1d. After resetting the delay value to "0" once, the timing adjusting mechanisms 10a to 10d are controlled to the delay times τA to τD to be inserted, and the timing is adjusted so as to adjust the reference point τo of the synchronization signal as necessary. By controlling the adjusting mechanism 10e, the delay amount of the fifth transmission line 1e is adjusted. Thereafter, the synchronization cycle ends.

Next, the details of how the master 15 determines the transition to the synchronous cycle will be described. As described above, the master 15 measures a predetermined period, that is, a predetermined period of time, and determines that a synchronization cycle is started each time the period elapses. For example, for an LSI with 1 W power, 100 ms
Since ec may change by 1 ° C., a synchronization cycle is executed every 100 msec. The master 15 can also judge as follows. That is, when a parity is added to a plurality of bits of data on the transmission lines 1a to 1d, a transfer error of the bit is detected, and it is determined that the process shifts to a synchronous cycle. In this case, after the execution of the synchronization cycle, it is necessary to retransmit the data in which the transfer error has occurred. As another determination method, the master 15 is provided with a parity function capable of correcting a bit, and when a bit transfer error is detected, it is determined that the bit in which the transfer error has occurred is corrected, and then the operation shifts to a synchronous cycle. In this case, it is not necessary to retransmit the data in which the transfer error has occurred. Further, as another judging method, a temperature sensor is arranged in at least one of the first and second LSIs 2 and 3 and the transmission lines 1a to 1e, and a synchronization cycle is executed when a predetermined temperature changes. For example, if the temperature changes by 10 ° C., the signal skew will shift by several nanoseconds, so a synchronization cycle is performed every 10 ° C. temperature change.

Therefore, in this embodiment, a synchronous cycle is set, and the period of the synchronous cycle is set to one of the clock signals.
Period exceeding the period (for example, multiple periods of the clock signal)
In this synchronous cycle, the difference in the propagation delay time between the signals A to D passing through the transmission lines 1a to 1d can be detected, and the delay value equal to the delay time difference is set to the corresponding transmission line 1a to 1d. 7D, the signal B has a delay time shorter than one cycle of the clock signal and the signal C has a delay time longer than one cycle of the clock signal, for example, as shown in FIG. Even if you have
As shown in FIG. 2B, both the signal B and the signal C can be adjusted within the same clock cycle as the signal A.

When the first LSI 2 is a memory controller and the second LSI 3 is a memory, the timing adjustment mechanisms 10a to 10e, the master 15, the synchronization event generation means 16, the synchronization signal generation means 17, the synchronization If the detection unit 18 and the delay value setting unit 19 are integrated on one LSI side (for example, the memory controller side), the configuration of the other LSI side (for example, the memory side) is simplified. In this case, a signal return path is required separately.

In the present embodiment, the timing adjusting mechanisms 10a to 10e are provided in the transmission lines 1a to 1e. However, the timing adjusting mechanisms 10a to 10e may be built in the first LSI 2, or may be provided in the second LSI.
Needless to say, it may be built in the I3, and may be built in both the first and second LSIs 2 and 3. Further, in the present embodiment, the timing adjustment mechanism 1 is connected to the fifth transmission line 1e.
Although the transmission line 1e is disposed, the transmission line 1e is a synchronization signal (that is, a signal different from the original signal whose phase shift should be adjusted).
, The timing adjustment mechanism 10e may be omitted.

Further, in the present embodiment, the case where a plurality of signals are transmitted between the first and second LSIs 2 and 3 has been described, but the signal receiving unit and the signal receiving unit are provided in the same LSI (one chip). Even when an output section is provided, the present invention can be applied to transmission of a signal between the output section and the output section.

FIG. 8 shows a synchronous cycle, test data output in this synchronous cycle, and a modification of this data. In the above embodiment, the synchronization cycle is the output period of the "LOW" level synchronization signal shown in FIG. 6, but in FIG. 8, the synchronization cycle is always output to the fifth transmission line 1e. The period is set to a total period of a period during which the HIGH synchronization signal becomes “LOW” (a period corresponding to two cycles of the clock signal) and a subsequent period corresponding to two cycles of the clock signal. When the synchronizing signal falls from "HIGH" to "LOW" (at the start of a synchronizing cycle), the data generating means 4 generates a signal having the same waveform as the synchronizing signal. Is transmitted to the transmission lines 1a to 1d (in FIG. 1, only the signals of the transmission lines 1a and 1b are illustrated). Therefore, the synchronization signal changes from “LOW” to “HIG”.
At the time of rising to "H", at this time (synchronous edge), signals that transition from "LOW" to "HIGH" are simultaneously transmitted to the transmission lines 1a to 1d. (That is, during the two periods of the clock signal after the synchronous edge), the transmission lines 1a to 1d are respectively provided during the period of one period of the clock signal before and after the synchronous edge (margin period). If there is no change in the signal, and the synchronization detecting means 18 detects the reception time of each of the signals on the transmission lines 1a to 1d within the synchronization cycle, if the phase shift between the two signals exceeds one cycle of the clock signal, Even if the phase shift between these signals can be detected, if the margin is set to a period of two or more cycles of the clock signal, the phase shift between the signals exceeds two cycles of the clock signal. It can also detect the delay amount between the signals.

FIG. 9 shows another example of the synchronization cycle. In the figure, when the synchronous event generating means 16 generates a synchronous cycle signal, the data generating means 4 generates an "L" level signal. The “L” level state of this signal continues for a predetermined period of the clock signal (six periods in the figure). This signal is transmitted to the transmission lines 1a to 1d by the data output means 5. The synchronization detecting means 18 detects that the "L" level state of the signal has continued for six cycles, and recognizes this detection time as the start time of the synchronization cycle. In this example, the synchronization cycle is a period corresponding to three periods of the clock signal. In this synchronous cycle, the data generating means 4 generates a signal of "H" level at the synchronous edge of the second cycle of the clock signal, and the data output means 5 transmits this signal to each of the transmission lines 1a to 1a.
1d. An advantage of this example is that a special transmission line 1e for transmitting a synchronization signal as in the above embodiment is not required.

FIG. 10 shows still another example of the synchronization cycle. FIG. 1 shows a case where the first and second LSIs 2 and 3 transmit and receive signals in accordance with a predetermined protocol.
Enters a synchronization cycle. LS to output protocol
One of I2 and LSI3, or another circuit may output.

FIG. 11 shows a modification of the above embodiment.
In the figure, a function of transmitting a signal from the second LSI 3 ′ to the first LSI 2 ′ is added to the delay time adjusting device of FIG. That is, the first and second LS
I2 'and 3' have data processing means 25 and 26 for generating and holding data, and data input / output means 27,
28. Other configurations are the same as those in FIG. 1 described above, and thus, the same portions are denoted by the same reference characters and description thereof will be omitted.

FIG. 12 shows a second modification of the above embodiment. This figure shows the delay time adjusting device of FIG.
Further, a third LSI 30 is added, and the third LSI 3
0 is connected to the first to fifth transmission lines 1a to 1e in parallel with the LSI 2 on the signal output side. The third LSI 30 has a data generation unit 31 and a data output unit 32, like the first LSI 2. Third LS
Synchronous event generating means 16 and synchronizing signal generating means 17 are added corresponding to I30. Other configurations are the same as those of the above embodiment.

FIG. 13 shows a third modification of the above embodiment. This figure shows the delay time adjusting device of FIG.
Further, a fourth LSI 40 is added, and the fourth LSI 3
0 is connected to the first to fifth transmission lines 1a to 1e in parallel with the LSI 3 on the signal input side. The fourth LSI 30 has a data input unit 41 and a data holding unit 42 like the second LSI 3. 4th L
In addition to the SI 40, the synchronization detecting means 18 is added, and the five lines connecting the fourth LSI 40 to the transmission lines 1a to 1e are separately provided with the timing adjustment mechanism 1 respectively.
0a to 10e are arranged, and the delay values of these timing adjusting mechanisms 10a to 10e are adjusted by newly provided delay value determining means 19 corresponding thereto. Other configurations are the same as those of the first embodiment.

In the above description, the case where data is transmitted as a signal to each transmission line has been described.
As the data transmitted to each transmission line, both cases where the same data or a plurality of different data are used are included, and, of course, the case where the same clock signal is used as the signal transmitted to each transmission line is also included. .

[0053]

As described above, according to the apparatus and method for adjusting the delay time between a plurality of transmission lines according to the present invention, when a signal is transmitted in parallel to each transmission line using a plurality of transmission lines, A predetermined synchronization cycle is executed, the period of the synchronization cycle is set to a period exceeding one cycle of the clock signal (for example, a plurality of cycles of the clock signal), and the signal is transmitted to a plurality of transmission lines within the synchronization cycle. Since this transmitted signal is received, the amount of delay (phase shift) between each signal
However, even if the delay amount is longer than one cycle of the clock signal, these delay amounts can be detected satisfactorily, and the signals received via the plurality of transmission lines are synchronized with the cycle of the same cycle. It is possible.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an overall configuration of a device for adjusting a delay time between a plurality of transmission lines according to an embodiment of the present invention.

2A is a diagram illustrating a configuration of a timing adjustment mechanism according to the embodiment, FIG. 2B is a diagram illustrating another configuration of the timing adjustment mechanism, and FIG. FIG. 11 is a view showing still another configuration of FIG.

FIG. 3 is a diagram showing an internal configuration of a synchronization detecting unit of the embodiment.

FIG. 4 is an explanatory diagram of the operation of the synchronization detecting means of the embodiment.

FIG. 5 is a diagram showing a flowchart of a specific example of detection of a delay amount between a plurality of signals within a synchronization cycle and determination of a delay amount to be inserted according to the embodiment;

FIG. 6 is a diagram illustrating a state of detecting a delay amount between a plurality of signals within a synchronization cycle and determining a delay amount to be inserted according to the embodiment.

7A is a diagram for explaining a state of a phase shift of signals A, B, and C, and FIG. 7B is a diagram for explaining an effect of the present embodiment.

FIG. 8 is a diagram showing a modification of the synchronization cycle.

FIG. 9 is a diagram showing another modification of the synchronization cycle.

FIG. 10 is a diagram showing still another modification of the synchronization cycle.

FIG. 11 is a diagram showing a first modification of the present embodiment.

FIG. 12 is a diagram showing a second modification of the present embodiment.

FIG. 13 is a diagram showing a third modification of the present embodiment.

14A is a diagram illustrating a state of a phase shift of signals A, B, and C, and FIG. 14B is a diagram illustrating a state of a conventional skew adjustment.

[Explanation of symbols]

1a to 1e Transmission line 2, 2 'First LSI 3, 3' Second LSI 4 Data generation means 5 Data output means (signal output unit) 6 Data input means (signal reception unit) 7 Data holding means 10a to 10e Timing adjustment means 15 Master (synchronization cycle setting means) 16 Synchronization event generation means 17 Synchronization signal generation means 18 Synchronization detection means 19 Delay value setting means 21, 22, 24 Selector (selection circuit) 23 Delay elements 25, 26 Data processing means 27 , 28 data input / output means 30 third LSI 31 data generation means 32 data output means 40 fourth LSI 41 data input means 42 data holding means 50 control means

Claims (14)

[Claims] A signal output unit; a plurality of transmission lines connected to the signal output unit, the output signals of the signal output unit being transmitted simultaneously; a signal reception unit receiving signals of the transmission lines; Timing adjustment means arranged on a path from the signal output unit to the signal reception unit via the plurality of transmission lines to adjust the signal propagation delay time of each transmission line; and a synchronization cycle setting for setting a predetermined synchronization cycle. Means, within a synchronization cycle set by the synchronization cycle setting means, a delay amount detection means for detecting a delay amount between signals of the respective transmission lines simultaneously output from the signal output unit and received by the signal reception unit. Control means for controlling the timing adjusting means based on a delay amount between signals of the respective transmission lines detected by the delay amount detecting means. Adjustment device for delay time between. 2. The method according to claim 1, wherein the control unit controls each of the transmission units so that the signal receiving unit receives the signals of the transmission lines simultaneously based on a delay amount between the signals of the transmission lines detected by the delay amount detection unit. Delay amount determining means for determining a delay amount to be inserted into a line; delay value setting for controlling the timing adjusting means so as to insert each delay amount determined by the delay amount determining means into a corresponding transmission line. 2. The apparatus for adjusting a delay time between a plurality of transmission lines according to claim 1, further comprising: 3. The apparatus for adjusting a delay time between a plurality of transmission lines according to claim 1, wherein said synchronization cycle setting means sets a synchronization cycle at a predetermined time interval. 4. A transmission of a signal to each transmission line is performed by adding a parity. The synchronization cycle setting unit detects a transmission error of a signal received by a signal receiving unit based on the parity. 2. The apparatus for adjusting a delay time between a plurality of transmission lines according to claim 1, wherein a synchronization cycle is set when a transmission error is detected. 5. A signal output unit, a signal reception unit, and a temperature sensor are disposed at least at one of a plurality of transmission lines. The synchronization cycle setting unit detects when the temperature sensor detects a change of a predetermined temperature or more.
The apparatus for adjusting a delay time between a plurality of transmission lines according to claim 1, wherein a synchronization cycle is set. 6. The method according to claim 1, wherein the setting of the synchronization cycle by the synchronization cycle setting means is performed by transmitting a synchronization signal to a dedicated transmission line separately added. Delay time adjustment device. 7. The setting of the synchronization cycle by the synchronization cycle setting means is performed by fixing a signal simultaneously transmitted to each of the transmission lines to a predetermined potential level for a predetermined period. The apparatus for adjusting a delay time between a plurality of transmission lines according to claim 1. 8. A signal transmission between a signal output unit and a signal reception unit is performed based on a predetermined protocol, and the setting of a synchronization cycle by the synchronization cycle setting unit is performed by an output of the protocol. The apparatus for adjusting a delay time between a plurality of transmission lines according to claim 1. 9. The delay time between a plurality of transmission lines according to claim 1, wherein said timing adjusting means comprises a plurality of delay elements and a selection circuit for selecting a combination of these delay elements. Adjustment device. 10. The multiple transmission line according to claim 1, wherein the number of the timing adjustment units is equal to the number of the plurality of transmission lines, and each timing adjustment unit is arranged in the middle of the corresponding transmission line. Adjustment device for delay time between. 11. The delay amount detection means, wherein, among the signals simultaneously output from the signal output unit and received by the signal reception unit via the respective transmission lines within the synchronization cycle, the signal reception unit receives the latest signal. 2. The apparatus for adjusting a delay time between a plurality of transmission lines according to claim 1, wherein a delay amount between the reference signal and a signal on another transmission line is detected based on a signal on one transmission line. 12. The output of a plurality of signals from the signal output unit,
2. The delay time adjusting device according to claim 1, wherein a period of the synchronization cycle set by the synchronization cycle setting means exceeds one cycle of the clock signal. . 13. A synchronizing cycle is set as a cycle for synchronizing signals of a plurality of transmission lines. In the synchronizing cycle, an output signal of a signal output unit is simultaneously transmitted to a plurality of transmission lines, and the plurality of transmissions are performed. A signal of a line is received by a signal receiving unit, a delay amount between signals of each transmission line received by the signal receiving unit within the synchronization cycle is detected, and based on the detected delay amount, a signal is output from the signal output unit. A method of adjusting a delay time between a plurality of transmission lines, wherein the delay amount of each transmission line is adjusted such that the signals of the transmission lines output at the same time are simultaneously received by the signal receiving unit. 14. The method according to claim 13, wherein the period of the synchronization cycle exceeds one cycle of a clock signal.