JPH10336008A - Clock generating circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale of a clock generating circuit without changing any adjusting unit when precisely adjusted clocks are generated from one clock in a very small adjusting unit. SOLUTION: When a clock generating circuit generates a plurality of clocks FCLK adjusted to the optimum phase at every one of a plurality of objects based on a received clock CLK, the circuit is provided with a first DLL circuit 21 which outputs a roughly adjusted clock RCLK by adjusting the delaying amount of the received clock CLK and a plurality of second DLL circuits 22-0 to 22-n which are respectively provided for each object and output a plurality of clocks FCLK by adjusting stepwise the delaying amount of the roughly adjusted clock RCLK. The first DLL circuit 21 changes the phase adjusting amount by discriminating whether the clock RCLK leads or lags the optimum phase within a prescribed phase difference and the second DLL circuits 22-0 to 22-n change the phase adjusting amount by discriminating whether the plurality of clocks FCLK lead or lag the optimum phase.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit for generating a plurality of clocks whose phases are independently adjusted from a received external clock, and a semiconductor device having such a clock generation circuit therein, and more particularly to an external clock. The present invention relates to a semiconductor device for correcting the variation of each input data with respect to the data fetch edge.

[0002]

2. Description of the Related Art In a large-scale semiconductor device system such as a computer using a semiconductor device, each part of the system is configured to operate in synchronization with a clock, and inputs and outputs of signals such as data signals and address signals. The output is performed in synchronization with the clock signal. FIG. 1 is a diagram showing the basic configuration and operation of such a semiconductor device system. FIG.
As shown in (1), the system includes a driving semiconductor device 101 for transmitting a signal and a receiving semiconductor device 102 for receiving a signal. Drive-side semiconductor device 101
From the clock signal CLK together with the clock signal CLK.
Output signals D0 to Dn are output in synchronization with the clock signal CLK, and the receiving-side semiconductor device 102 converts the signals transmitted from the driving-side semiconductor device 101 into the input signals Q0 to
Import as Qn. In FIG. 1, the receiving-side semiconductor device 10
2 is one, but a plurality of receiving-side semiconductor devices 102 may exist. In addition, a semiconductor device included in a semiconductor device system often transmits and receives signals to and from another semiconductor device. In such a case, the semiconductor device becomes a driving side or a receiving side according to operation.

FIG. 1B is a diagram showing a clock CLK and a signal on a bus in the semiconductor device system of FIG. 1A. A clock CL output from the driving side is shown on the upper side.
The lower side shows the state when K and the output signals D0 to Dn are fetched as the clock CLK and the input signals Q0 to Qn on the receiving side. The driving-side semiconductor device 101 includes:
The output signals D0 to D0 are synchronized with the fall of the clock CLK.
Dn is changed. The receiving side semiconductor device 102 synchronizes the signal D0 with the rising edge of the received clock signal CLK.
To Dn as input signals Q0 to Qn.

In (2) of FIG. 1, the output signal changes in synchronization with the falling edge of the clock CLK, and the clock CL changes.
Although the input signal is taken in synchronization with the rise of K, the output signal may change at a phase shifted from the fall or rise of the clock CLK and be taken into the semiconductor device in some cases. In the following example, for the sake of simplicity, it is assumed that the input signal changes in synchronization with the falling edge of the clock CLK and is taken in synchronization with the rising edge of the clock CLK, but the present invention is not limited to this. It is not something that can be done.

As shown in FIG. 1B, the driving-side semiconductor device 101 changes the output signals D0 to Dn in synchronization with the falling edge of the output clock CLK, but actually changes the characteristics of the output circuit. Due to the difference and the phase difference between the output timing signals, the changing edge of each output signal varies as shown in the figure with respect to the falling edge of the clock CLK. The signal wiring from the driving-side semiconductor device 101 to the receiving-side semiconductor device 102 has a different wiring length or a different load connected to the wiring. There is a difference in the transmission time of Therefore, the variation of the changing edge of the input signal received by the receiving-side semiconductor device 102 with respect to the falling edge of the clock CLK is further increased as illustrated. This variation period is an uncertain period during which input signals cannot be captured because all input signals are not determined. Such phase variation between signals is called skew. Since the skew is caused by the length of the signal wiring and the load, it cannot be reduced to zero.

When a semiconductor device takes in an input signal by a latch circuit, the latch circuit necessarily has a set-up time tSI and a hold time tHI which are necessary due to the operation, and the input signal is determined before and after the rising edge of the clock CLK. The time you need to do is defined.
Therefore, even if there is a skew in the input signal received by the receiving semiconductor device 102, before and after the rising edge of the clock CLK, the setup time tSI and the hold time tSI
During HI, the input signal needs to be fixed. A period obtained by subtracting the indefinite period of the input signal from the clock cycle is the definite period of the input signal. In a low-speed system, the uncertainty period of the input signal as described above is relatively small compared to the clock cycle, which is not a problem, but in a high-speed system, the clock cycle is very short. Is relatively large in the clock cycle, and the determination period is reduced accordingly, which is a major problem. For this reason, a situation has arisen in which the skew defines the operation speed of the semiconductor device.

The applicant of the present application discloses a technique for solving such a problem in Japanese Patent Application No. 8-334208. FIG. 2 is disclosed in Japanese Patent Application No. 8-334208.
FIG. 9 is a diagram illustrating a configuration of a conventional example for taking measures against skew of an input signal. As shown in FIG. 2, input signal acquisition timing adjustment circuits 12-0 to 12-n are provided for each of the input signals D0 to Dn. Each input signal acquisition timing adjustment circuit includes an input buffer 13, an input latch circuit 14, and a DLL (dela
y locked loop) circuit 15. The DLL circuit 15 delays the clock output from the clock buffer 11 and changes the delay amount in a stepwise manner. The DLL circuit 15 selects the optimum phase for the delayed clock to capture the input signal output from the input buffer 13. This is a circuit that is configured by a phase comparison circuit that determines whether the delay time is equal to or less than that, and adjusts the delay amount until an optimum phase is reached. As a result, a clock having a phase optimal for capturing an input signal is output from the DLL circuit 15, and the input signal output from the input buffer 13 is latched by the input latch 14 according to the clock. As shown in the figure, since such an input signal capture timing adjustment circuit is provided for each input signal,
Each input signal is taken in at an optimal timing regardless of the skew.

Since the fetch timings of the input latches 14 are independently adjusted, the input signals fetched as described above are out of phase with each other, and there is a problem when they are simultaneously processed internally. Therefore, the resynchronization latches 16-0 to 16-0
16-n are provided to make the phases of input signals having different phases output from the input latches 14 uniform. With such a configuration, each input signal is taken in at an optimal timing, and is output as an input signal having the same phase.

[0009]

The delay circuit constituting the DLL circuit shown in FIG. 2 has a delay line in which a number of delay elements that generate a delay amount for one stage are connected in series. Therefore, when the delay amount per stage is reduced to enable precise phase adjustment, it is necessary to perform the phase adjustment more than expected skew, and the number of stages becomes extremely large.
Therefore, the circuit scale of the delay circuit is large. Moreover,
It is necessary to provide such a delay circuit for each input signal, and the entire circuit for countermeasures for the skew of the input signal shown in FIG. 2 has a very large circuit size, greatly affects the chip area, and reduces the chip area. Contribute to increase.

The present invention has been made to solve such a problem, and has as its object to reduce the area occupied by a skew countermeasure circuit. However, the present invention is not limited to the skew countermeasure circuit, and can be applied to any circuit having a DLL circuit.

[0011]

FIG. 3 is a block diagram showing the principle of a clock generation circuit according to the present invention. As shown in FIG. 3, in the clock generation circuit of the present invention, the DLL circuit has a hierarchical structure, and the first DLL circuit 21, which is a parent hierarchy, is commonly used.
The second DLL circuits 22-0 to 22-n, which are child layers, are provided for each input signal. Thus, the first DLL circuit 21 can be used in common, so that the circuit scale can be reduced. Even if hierarchization is performed, providing individual circuits for each input has a large area and is ineffective, so it is necessary to share the parent hierarchy.

That is, the clock generation circuit of the present invention comprises:
A plurality of clocks FCLK <b> 0 to FCLK <b> 0 adjusted to an optimal phase for each of a plurality of targets based on the received reception clock CLK
A first DLL circuit 21 that generates a coarsely adjusted clock RCLK by adjusting the phase of the received clock by stepwise adjusting a delay amount for delaying the received clock CLK; The phase of the coarse adjustment clock RCLK is adjusted by stepwise adjusting the delay amount for delaying the coarse adjustment clock RCLK, and the plurality of clocks FCLK0 to FCLK0 are provided.
A plurality of second DLL circuits 22-0 to 22 which output FCLKn
22-n, and the first DLL circuit 21 proceeds when at least one of the plurality of clocks is within a predetermined phase difference range with respect to the optimum phase or is not within the predetermined phase difference range. Is determined, and the phase adjustment amount is changed based on the determination result.
The L circuits 22-0 to 22-n output a plurality of clocks FCLK
It is characterized in that it is determined whether each of 0 to FCLKn is ahead or behind the optimum phase, and the phase adjustment amount is changed based on the determination result.

The delay amount of one stage of the first DLL circuit is calculated by the second D
It is desirable to make the delay amount larger than the delay amount of one stage of the LL circuit. As described above, if the delay amount for one stage of the delay circuit is increased, the circuit scale can be reduced, but precise phase adjustment cannot be performed. However, by adopting such a configuration, the circuit scale is reduced and precise adjustment is performed. Can be performed. The above configuration is based on the difference between the clock CLK and the signal path of the input signal group, etc.
This is applicable when there is a skew greater than the skew between the input signals between the clock CLK and the input signal group. The skew between the clock CLK and the input signal group is adjusted by the first DLL circuit, and the skew between the input signals is reduced by the second DLL. Adjust with the circuit.

In order to use a common delay circuit, the same delay line can be used, and a clock can be selectively extracted from each stage of the delay line for each target. Applying this idea to the above-described configuration, the first DLL circuit 21 can output a plurality of coarsely adjusted clocks whose delay amounts are independently adjusted, and all of the plurality of clocks can be output with respect to the optimum phase. If it is within the predetermined phase difference range or not within the predetermined phase difference range, it is determined whether it is advanced or delayed, and based on the determination result, each 2D
A coarse adjustment clock whose delay amount is independently adjusted for each LL circuit is output. In this case, the adjustment range for the reception clock for each object is the same as the first DLL circuit 21 and the second DLL circuit.
This is the range to which the adjustment range of the DLL circuit is added, and these adjustment ranges are independent for each target. Therefore, it is possible to adjust the skew between the targets as long as the skew between the targets is within the adjustment range of the first DLL circuit 21 and the second DLL circuit.

For this purpose, the first DLL circuit is composed of a delay circuit for delaying the received clock in a stepwise manner and a switch array for switching whether or not to output the output of each stage of the delay circuit to each of the second DLL circuits. And selecting a switch to be turned on in the switch row based on the determination result for each clock. In the clock generation circuit, in order to determine whether the phase is optimal in the first and second DLL circuits, it is desirable that the target be in a state suitable for performing such a determination operation. However, if the target is in such a state, normal operation cannot be performed. Therefore, a calibration mode for adjusting the delay amount of the first and second DLL circuits is provided, and after the calibration mode, the first and second DLLs are set. It is desirable that the circuit can hold the delay amount at the end of the calibration mode. For that purpose, it is desirable that the first and second DLL circuits have a latch function of holding the adjusted delay amount.

Furthermore, a clock distribution circuit for distributing an internal clock generated based on a reception clock input from the outside, and a local clock generation circuit for generating a plurality of local clocks from the internal clock supplied from the clock distribution circuit Although a semiconductor device including the following is known, the circuit scale of the local clock generation circuit can be reduced by applying the clock generation circuit of the present invention to the local clock generation circuit. In particular, the present invention is preferably applied to a local clock generation circuit that generates a clock signal for capturing input data input to a semiconductor device. This is because there is a skew between the input signals and between the local clock and the input signal group, which is a problem in increasing the speed.

Also, since there is a skew between the input signals fetched in synchronization with the plurality of local clocks generated in this way, the input data fetched in synchronization with the edges of the plurality of local clocks, respectively. It is desirable to provide a resynchronization circuit for resynchronizing with a common resynchronization clock. It is desirable that the clock distribution circuit that distributes the internal clock to each local clock generation circuit does not cause skew in the distributed internal clock,
A clock distribution circuit composed of H-tree-shaped wiring having the same wiring distance and load as the distribution destination, a reciprocating wiring for transmitting and reciprocating the internal clock, and a reciprocating internal clock provided along the reciprocating wiring for receiving the reciprocating internal clock A clock distribution circuit includes a local clock buffer that generates a corrected internal clock having an intermediate phase between reciprocating internal clocks.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described with reference to a synchronous dynamic random access memory (SDRAM).
An example in which the present invention is applied to an input signal capturing portion will be described, but the present invention is not limited to this.
The present invention can be applied to any device that uses a DLL circuit for generating a clock signal having an optimum phase for each signal, such as an output portion for outputting an output signal of a DRAM in synchronization with a clock.

FIG. 4 shows an SDRAM according to a first embodiment of the present invention.
FIG. 2 is a diagram showing an overall configuration of the embodiment. As shown in the figure, a memory core 30 composed of a cell array / sense amplifier is arranged along the long side of the chip, and a peripheral circuit part composed of an address buffer / decoder is arranged in the center. Pads 31 to 35 are arranged in a row in the center of the peripheral circuit section, and peripheral circuits are arranged on both sides thereof. The pads are data signal pads 31 and 34 arranged on both sides.
, A control signal pad 32 and an address signal pad 33.
5 is provided in the control signal pad 32. The external clock input to the clock pad 35 is input to the clock buffer 36 and taken into the chip. The internal clock output from the clock buffer 36 is supplied to the entire chip by a clock distribution circuit.

It is desirable that the clock distribution circuit supplies an internal clock CLK having the same phase to each section in the chip. As such a clock distribution circuit, H
Although a tree-shaped clock distribution circuit is known, the present applicant has proposed a new clock distribution circuit in Japanese Patent Application No. 9-83050, which is used in the first embodiment. As shown in the figure, this clock distribution circuit is provided with a clock signal line for a forward path so as to run in a chip from a clock driver 37, and a delay circuit 38 is provided at the end. Then, a return clock signal line is provided from the delay circuit 38 in parallel with the forward clock signal line, and the clock supplied from the forward clock signal line to the delay circuit 38 is delayed by a certain amount. Apply. Here, a main clock signal line is further provided in parallel with the forward and return clock signal lines. A local CLK buffer 39 is arranged along these clock signal lines, and supplies an internal clock to a peripheral area therefrom. The intermediate phase between the forward clock transmitting the forward clock signal line and the backward clock transmitting the backward clock signal line is the same at any point along the clock signal line. Therefore, each local CLK buffer 39 delays the internal clock supplied from the main clock signal line by の of the phase difference between the forward clock and the backward clock, and generates the internal clock C.
LK is generated and output. Without the delay circuit 38, the phase difference between the forward clock and the backward clock is small near the terminal end, and it is difficult to accurately detect and correct the phase difference. This is so that
Further, since the internal clock has a very high frequency, it becomes difficult to determine the phase to be compared when the wiring distance is long. Therefore, a clock having a long cycle for detecting a phase difference is transmitted between the forward clock signal line and the return clock signal line, and an internal clock is transmitted using the main clock signal line.

As described above, the local CLK buffers 39 connected to the left and right clock signal lines respectively generate the internal clock CLK having the same phase. However, if the lengths and loads of the left and right clock signal lines are different, the left and right clock signals are left and right. Local C
The internal clock CLK generated by the LK buffer 39 does not always have the same phase. Therefore, clock driver 3
7, a phase comparison circuit 90 is provided. This circuit compares the phases of the return clocks transmitted through the return clock signal line, and adjusts one of the delays (here, the left side of the left side, so that the phases of the left and right return clocks coincide. (Delay) 38 is adjusted. As a result, the internal clocks CLK generated by the left and right local CLK buffers 39 have the same phase.

As described above, in the first embodiment, the internal clock CLK having the same phase is output from each local CLK buffer 39 regardless of the position. The internal clock CLK output from the local CLK buffer 39 is supplied to the variation correction input circuit 40.
In the first embodiment, the variation correction input circuit 40 has a latch circuit that captures an input signal, and generates a local clock that specifies the timing of the capture supplied thereto. There is also a portion where the internal clock is directly supplied from the local CLK buffer 39 to the inside of the chip.

As described above, the input signal has a skew with respect to the clock, and there is a skew between the input signals. Since the internal clock is distributed as described above, the internal clock CLK output from each local CLK buffer has the same phase, but a signal path from the clock pad to the clock driver 37 via the clock buffer 36, Since the paths of other input signals are greatly different, the skew between the input signal group and the internal clock is generally larger than the skew between the input signals. In order to capture such an input signal into the chip, it is necessary to make the local clock supplied to the latch circuit that captures each input signal an optimal phase with respect to the phase of each input signal. The circuit 40 generates a local clock optimal for capturing each input signal from the internal clock CLK.

FIG. 5 is a block diagram showing a configuration of the variation correction input circuit 40. As shown, the variation correction input circuit 40 includes a coarse delay circuit 41 for delaying the internal clock CLK supplied from the local CLK buffer 39 by a selected delay amount, and a coarse delay clock output from the coarse delay circuit 41. A precision delay circuit 42 that delays by the selected delay amount, a phase of each input signal input from the input buffer 48 and divided by the frequency divider 47 and a local clock output from the precision delay circuit 42 are compared, The input buffer 4 according to the local clock output from the coarse comparison circuit 43, the fine comparison circuit 44, and the fine delay circuit 42 for determining whether or not the phase is optimal.
An input latch 45 which latches and takes in an input signal output from the input latch 8; a resynchronization latch 46 which latches the output of the input latch 45 again according to the internal clock CLK and synchronizes the phase of each input signal with the internal clock CLK Having.
The frequency dividing circuit is provided so that the comparing operation can be performed accurately. As shown in FIG.
2. Coarse comparison circuit 43, precision comparison circuit 44, input latch 4
5, the resynchronization latch 46, the frequency dividing circuit 47, and the input buffer 48 are provided by the number of input signals, respectively, but the number of the coarse delay circuit 41 is one and is shared by each input signal. The coarse delay circuit 41 and the coarse comparison circuit 43 constitute a coarse DLL circuit, and the precision delay circuit 42 and the precision comparison circuit 4
4 constitutes a precision DLL circuit. As is apparent from comparison with FIG. 2, the circuit of this embodiment has a configuration similar to that of the conventional example of FIG. 2, and is different from the conventional example in that the DLL circuit is a coarse DLL circuit and a precision DLL circuit. It is composed of
Hereinafter, these portions and the frequency dividing circuit, which are different from the conventional example, will be described.

Coarse delay circuit 41 and precision delay circuit 4
2 both have a basic configuration as shown in FIG. 6, and are each composed of a delay line 51 and a delay control circuit 52. As described above, a DLL circuit is configured by combining these with the phase comparison circuit. The DLL circuit will be briefly described. The delay line 51 connects the same delay elements in series, and selects the stage from which the output is to be taken out so that the delay amount can be selected. The output is taken out by a control signal from the delay control circuit 52. The step is determined. The phase comparison circuit compares the phase of the delayed clock output from the delay line 51 with the phase of the input signal, and if the phase difference is within a predetermined range or not within the predetermined range, the clock is applied to the input signal. It is determined whether the vehicle is ahead or behind. The delay control circuit 52 determines the delay line 51 based on the determination result.
Is maintained, increased or decreased. By repeating such an operation, the phase difference between the clock and the input signal is converged within a predetermined range.

FIG. 7 shows the configuration of the delay control circuit of the coarse delay circuit 41 and the fine delay circuit 42, FIG. 8 shows the configuration of the delay line of the coarse delay circuit 41, and FIG. 10 shows the configuration of the coarse comparison circuit 43, FIG. 11 shows the configuration of the precision comparison circuit 44, and FIG. 12 shows the configuration of the frequency dividing circuit 47. The basic operation of these circuits is described in Japanese Patent Application No.
This is described in detail in Japanese Patent Application No. 334208 and Japanese Patent Application No. 9-83050.

The delay control circuit shown in FIG. 7 shows only a part of the delay control circuit, and outputs only P0 to P5 as control signals. Similar circuits are connected.
The delay control circuit sets only one of the output control signals to “high (H)” and sets the other outputs to “low (L)”,
The selection position of the delay amount of the delay line is determined by the output position that becomes “H”. The delay control circuit moves the output position which becomes “H” according to the determination results A to D from the phase comparison circuit. When A and B alternately go to the “high (H)” level, the output position that goes “H” is shifted to the right. When C and D alternately go to the “high (H)” level, the output position goes to “H”. Is shifted to the left. When the reset signal is input, the output of the first stage becomes “H”. Such a delay control circuit is provided in each of the coarse delay circuit 41 and the fine delay circuit 42 for the number of input signals. Here, further description is omitted. In the delay control circuit shown in FIG. 7, since the control signal does not change when the determination results A to D are the determination results that the delay amount is held, the phase comparison is performed by stopping a frequency dividing circuit described later. Otherwise, the control signal output from the delay control circuit is held. Further, in order to hold the output control signal, there is a method of providing a latch gate which normally passes the control signal and latches and holds the control signal at that time when the state changes to the stop state.

As shown in FIG. 8, in the delay line of the coarse delay circuit 41, one inverter and one NAND gate are connected.
A large number of delay elements as stages are connected in series, and the output of the inverter at each stage is taken out from the transfer gate. The delay amount differs depending on which stage the signal is taken out from. The transfer gates are provided for the number of input signals for each output of the inverter of each stage. The outputs of the transfer gates of all stages corresponding to each input signal are connected in common, and the corresponding delay of the precision delay circuit 42 is Input to the line. The transfer gates of all stages corresponding to each input signal are output signals RP00, RP0n,..., RPm0, RPmn of the corresponding control circuit.
And so on. As described above, since only one of the output signals of the control circuit becomes “H”, the transfer gate to which it is applied becomes conductive, and the coarse delay clock RCLK is output from that stage. As described above, since the portion of the delay line of the coarse DLL circuit 41 of the first embodiment is shared, even if there are a plurality of input signals, the delay line is one.
Therefore, the circuit scale can be reduced accordingly. For example, FIG.
In this circuit, the number of elements can be further reduced because two elements can be reduced per stage and some elements can be shared.

As shown in FIG. 9, each precision delay circuit 4
In the second delay line, two rows of delay lines in which a number of delay elements each having an inverter and a NAND gate as one stage are provided in series, an intermediate NAND gate is provided for each stage therebetween, and the output of the upper inverter is provided. This intermediate N
The signal is input to the AND gate, and the output is input to the lower NAND gate. The output of the DLL control circuit of the precision DLL circuit is input to the other input of the intermediate NAND gate, and only one intermediate NAND gate transmits the clock output from the upper inverter to the lower side, and the other intermediate NAND gates The output of the gate is fixed at "H". That is, the clock transmitted on the upper side is transmitted to the lower side at the portion of the intermediate NAND gate where the output of the DLL control circuit becomes "H", and transmitted on the lower side as it is to become the local clock FCLK. On the upper side, the output of the inverter is input to the next-stage NAND gate and the intermediate NAN
Although the signal is also input to the D gate, the output of the inverter is only input to the next-stage NAND gate on the lower side, and the load on the inverter is smaller on the lower side, so that the clock transmission speed is lower. Is slightly faster. That is, this delay line uses the difference between the transmission speeds on the upper side and the lower side as the delay amount of one stage. In a precision delay line, the amount of delay per stage needs to be very small, and such a circuit configuration is used.

Each coarse comparison circuit 43 shown in FIG. 10 includes a local clock FCLK output from a delay line of a precision delay circuit 42 and a signal DS divided by a frequency division circuit 47.
Are compared. This circuit uses the local clock FC
When the signal DS has already risen when the LK rises, that is, when the local clock FCLK is
When the signal DS is later than S, the outputs RA and RB alternately become “H”, and when the signal DS has already risen after a first predetermined time or more from the time when the local clock FCLK rises, that is, when the local clock FCLK
Is advanced from the signal DS, and when the phase difference is equal to or more than the first predetermined amount, the outputs RC and RD alternately become “H”,
From the time when the local clock FCLK rises, the first
When the signal DS has already risen within a predetermined time, that is, when the local clock FCLK is ahead of the signal DS and the phase difference is within a first predetermined amount, the output R
A, RB, RC, and RD all become “L”. As shown in the figure, the signal DS is directly input to two flip-flops of the input unit constituted by the NAND gate, but the local clock FCLK is input to one of the flip-flops with a delay of the NAND gate and the inverter. It has become. The amount of delay in the NAND gate and the inverter defines the first predetermined amount. The determination result of each coarse comparison circuit 43 is applied as A, B, C, D of the delay control circuit shown in FIG. 7 of the coarse DLL circuit.

Each precision comparison circuit 44 shown in FIG.
0 has almost the same configuration as the coarse comparison circuit 43 shown in FIG.
The signal DS and the local clock FCLK are both delayed by the NAND gate and the inverter and input to one of the flip-flops in the input section. In addition, since there is a difference in the number of gates driven by the inverter, the difference in the second delay amount that defines a state in which the outputs FA, FB, FC, and FD are all "L" is small. As a result, the phase difference between the signal DS and the local clock FCLK becomes larger than the coarse comparison circuit 43 in FIG.
In the case where it is determined that the local clock FCLK is within the predetermined amount range, a more precise comparison is performed, and it is determined whether the local clock FCLK is ahead of or behind the signal DS, or is within the second predetermined amount. Output the judgment result. Similarly, the judgment result of each precision comparison circuit 44 is applied as A, B, C, D of the delay control circuit shown in FIG. 7 of the precision DLL circuit.

The frequency dividing circuit 47 shown in FIG. 12 divides an input signal by eight. Here, the necessity of dividing the input signal will be described. The semiconductor device is required to operate in a predetermined clock frequency range. Therefore, the DLL circuits described so far are required to operate in these frequency ranges. If the clock becomes too high in frequency, the output of each gate will change to the next state before changing sufficiently to one state. Therefore, there is a difference in the comparison result between the case where the clock frequency is high and the case where the clock frequency is low,
There is a problem that desired phase matching cannot be performed. In order to solve such a problem, the frequency of the input signal is divided and the period for performing the phase comparison and the feedback control based on the determination result is lengthened. The input section of the frequency dividing circuit 47 is provided with a NAND gate to which the input signal S and the stop signal are input. When the stop signal is set to “L”, the input signal S to the frequency dividing circuit 47 is reduced. Input can be stopped. As a result, the output of the frequency dividing circuit 47 is fixed, the phase comparison operation is stopped, and the control value of the delay control circuit is held.

The input latch 45 and the resynchronization latch 46 of FIG.
Is a latch circuit that has been widely used in the past, and description thereof is omitted here. As described above, in the first embodiment, the phase of the internal clock CLK output from the local clock buffer 39 is adjusted so as to be the local clock FCLK at the optimum timing for capturing each input signal, and the phase is adjusted by the input latch 45. At the optimal timing. However, since the input signals thus fetched have variations in phase, they are changed by the resynchronization latch 46 to signals synchronized with the internal clock CLK.

The circuit of the first embodiment described above requires time until the control value of the delay control circuit is stabilized.
A predetermined time after the power is turned on is set as a calibration period for phase adjustment, during which the phase adjustment ends. Since the time until the phase adjustment ends is different depending on the initial phase difference, the calibration period is set to the time when the phase adjustment ends regardless of the initial phase difference. Further, in order to perform the phase adjustment, the clock and the input signal need to change, and during the calibration period, the input signal changes at a predetermined cycle.
It is necessary to output such a signal from the driving LSI chip.

In a normal operation, the clock is a signal that changes at a constant cycle. However, the change of the input signal is not constant, and the same state may occur for a long time. In such a case, phase comparison cannot be performed. When the input signal does not change, the circuit of the first embodiment outputs a phase determination result instructing to maintain the previous state, so that the feedback control can be performed as it is during a normal operation. Generally, the change characteristics of a signal of a semiconductor device change with temperature or the like. Therefore, if the circuit of the first embodiment is operated as it is during a normal operation, it is controlled so that an input signal is always taken in at an optimal timing. become.

However, when some input signals are changed and feedback control is performed, and other input signals are not changed for a long period of time, the feedback control is not performed. Control is performed so that the input timing is reached. However, other input signals may be greatly deviated from the optimal input timing. Since such a thing is not preferable, a calibration period may be provided periodically.
In this case, as shown in FIG. 13, the phase adjustment is performed only during the calibration period, and after the calibration period, the control signals of the delay control circuits of the coarse delay circuit 41 and the fine delay circuit 42 shown in FIG. 7 are maintained. To do it.

In the first embodiment, the coarse delay circuit 4
1, a delay line is shared, but by providing a large number of transfer gates for selecting the output of each stage of the delay line, a coarse delay clock corresponding to each input signal can be taken out. Thus, the phase adjustment between the internal clock and each input signal can be performed independently over the entire adjustment range. However, for this purpose, transfer gates for the number of input signals are provided for each stage, and there is a problem that the circuit scale is large. As described above, the internal clock CLK and the input signal group generally have a skew larger than the skew between the input signals between the clock CLK and the input signal group due to a difference in a signal path or the like. Therefore, in the second embodiment, the internal clock CL
The skew between K and the input signal group is adjusted by the first DLL circuit, and the skew between the input signals is adjusted by the second DLL circuit.

FIG. 14 is a block diagram showing the configuration of the variation correction circuit according to the second embodiment. As shown in the figure, the variation correction circuit of the second embodiment has substantially the same configuration as the variation correction circuit of the first embodiment, except that a number determination circuit 69 is newly provided, and a coarse delay circuit 61 is provided. Are different in the configuration of the delay line. Hereinafter, these parts will be described.

FIG. 15 shows a coarse delay circuit 6 according to the second embodiment.
FIG. 3 is a diagram illustrating a configuration of one delay line. As shown, a large number of delay elements having a NAND gate and an inverter as one stage are connected in series, and a coarse delay clock RCL is connected from the last stage.
K is taken out. Which stage receives the internal clock CLK depends on the output signals RP0,.
The delay amount is controlled by RPm and differs depending on which stage the internal clock CLK is input. Accordingly, the coarse delay clock R output from the coarse delay circuit 61 of the second embodiment
CLK is one, and this is supplied to each precision delay circuit 62.

In order to perform such adjustment, in the second embodiment, as shown in FIG. 16, the calibration mode for performing phase adjustment is divided into two periods, and the coarse DL is used in the first half.
The adjustment of the L circuit is performed, and the adjustment of the precision DLL circuit is performed in the latter half. While the adjustment of the first half coarse DLL circuit is being performed, the precision DLL circuit does not perform feedback control, and the delay amount of the delay line of the precision delay circuit is held at the initial value. After the adjustment of the coarse DLL circuit is completed, the control signal of the delay control circuit of the coarse delay circuit 61 is held. At the same time as the adjustment of the coarse DLL circuit is completed, the adjustment of each precision DLL circuit is started. After the adjustment of each precision DLL circuit is completed, the control signal of the delay control circuit of the precision delay circuit 62 at that time is similarly held. Is done. Note that, as described above, since the precision DLL circuit can perform feedback control even during normal operation, only the precision DLL circuit may be configured to always perform the adjustment operation even during normal operation.

The amount of delay in the coarse delay circuit 61 is adjusted so that the intermediate phase of a plurality of input signals and the clock phase match. As shown in FIG. 14, the coarse comparison circuits 63 are provided for the number of input signals, and the determination results of each of the coarse comparison circuits 63 are input to the number determination circuit 69. In the number determination circuit 69, the determination results of each coarse comparison circuit 63 are totaled,
If the number of coarse comparison circuits 63 determined to be behind the signal DS is greater than the number of coarse comparison circuits 63 determined to be advanced, the delay amount of the delay line is increased, Clock FCLK
Coarse comparison circuit 6 that has determined that
If the number of delay lines 3 is larger than the number of coarse comparison circuits 63 determined to be delayed, a determination result is output that reduces the delay amount of the delay line. Then, the coarse comparison circuit 63 that determines that the local clock FCLK is within a predetermined amount of phase difference with respect to all the signals DS or is advanced.
When the difference between the number of the coarse comparison circuits 63 determined to be late and the number of the coarse comparison circuits 63 is less than one, the determination result is held.

As a modification of the second embodiment, a coarse comparison circuit 63 is provided only for one representative input signal.
The determination result may be supplied to the coarse delay circuit 61. In this case, the number determination circuit 69 is not required. Thereby, the circuit scale can be significantly reduced. In the first embodiment, a clock distribution circuit is disclosed in Japanese Patent Application No. 9-830.
Although the circuit disclosed in No. 50 is used, an H-tree clock distribution circuit may be used instead. FIG. 17 is a diagram showing a basic configuration of the H-tree clock distribution circuit. The internal clock output from the clock driver 71 is transmitted to the terminal clock buffer 72 through a path as shown in FIG. 17, but all the signal paths and loads on the way are configured to be equal. Therefore,
The internal clocks transmitted to all clock buffers 72 have the same phase.

FIG. 18 is a diagram showing the entire structure of the SDRAM of the third embodiment, which is disclosed in Japanese Patent Application No. 9-83050 in that an H-tree clock distribution circuit is used instead of the clock distribution circuit. This is the same as the first embodiment except for the above. Therefore, further description is omitted. As described above, the embodiment in which the present invention is applied to an input signal input portion of an SDRAM has been described. However, the present invention is not limited to this, and it is possible to precisely adjust output timing for a plurality of output signals in an SDRAM, The present invention can be applied to other LSI chips other than SDRAM. Further, the example of the two steps of the coarse adjustment and the fine adjustment has been described, but it is also possible to have three or more steps.

[0044]

As described above, according to the present invention,
In the case of generating clocks that are precisely adjusted from a single clock in a very small amount of adjustment units, the adjustment unit is the same, the circuit scale can be reduced, and the size and cost of the chip can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration and operation of a clock synchronization system.

FIG. 2 is a diagram showing a configuration of a conventional example for taking measures against skew of an input signal.

FIG. 3 is a diagram illustrating the principle of the present invention;

FIG. 4 is a diagram showing an overall configuration of the SDRAM of the first embodiment.

FIG. 5 is a block diagram illustrating a configuration of a variation correction input circuit according to the first embodiment.

FIG. 6 is a block diagram illustrating a configuration of a delay circuit.

FIG. 7 is a diagram illustrating a configuration of a delay control circuit according to the first embodiment.

FIG. 8 is a diagram illustrating a delay line of the coarse DLL circuit according to the first embodiment.

FIG. 9 is a diagram illustrating a delay line of the precision DLL circuit according to the first embodiment.

FIG. 10 is a diagram illustrating a coarse comparison circuit according to the first embodiment.

FIG. 11 is a diagram illustrating a precision comparison circuit according to the first embodiment.

FIG. 12 is a diagram illustrating a frequency dividing circuit according to the first embodiment.

FIG. 13 is a diagram illustrating an operation mode of the first embodiment.

FIG. 14 is a block diagram illustrating a configuration of a variation correction input circuit according to a second embodiment.

FIG. 15 is a diagram illustrating a delay line of a coarse DLL circuit according to a second embodiment.

FIG. 16 is a diagram showing an operation mode of the second embodiment.

FIG. 17 is a diagram illustrating a configuration of an H-tree clock distribution circuit.

FIG. 18 is a diagram illustrating an overall configuration of an SDRAM of a third embodiment.

[Explanation of symbols]

 21 First DLL Circuit 22-0 to 22-n Second DLL Circuit 35 Clock Input Pad 36 Clock Buffer 37 Clock Driver 38 Delay 39 Local CLK Buffer 40 Variation Correction Input Circuit 41 Coarse Delay Circuit 42 Precision delay circuit 43 ... Coarse comparison circuit 44 ... Precision comparison circuit 45 ... Input latch 46 ... Resynchronization latch 47 ... Division circuit 48 ... Input buffer

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H03K 5/13 G11C 11/34 354C 5/15 362S H03K 5/15 G

Claims (16)

[Claims] 1. A clock generation circuit for generating a plurality of clocks adjusted to an optimum phase for each of a plurality of targets based on a received reception clock, wherein a delay amount for delaying the reception clock is adjusted stepwise. A first DLL circuit that adjusts the phase of the reception clock to output a coarse adjustment clock and adjusts a delay amount that is provided for each of the plurality of targets and delays the coarse adjustment clock in a stepwise manner. And a plurality of second DLL circuits for adjusting the phase of the coarse adjustment clock to output the plurality of clocks, wherein the first DLL circuit is configured such that at least one of the plurality of clocks has an optimum phase. If it is within the predetermined phase difference range or not within the predetermined phase difference range, it is determined whether the vehicle is advanced or delayed, and the phase adjustment is performed based on the determination result. Each second DLL circuit determines whether each of the plurality of clocks is advanced or delayed with respect to an optimal phase,
A clock generation circuit for changing a phase adjustment amount based on a result of the determination. 2. The clock generation circuit according to claim 1, wherein a delay amount of one stage of said first DLL circuit is equal to said plurality of second DLL circuits.
A clock generation circuit larger than the delay amount of one stage of the DLL circuit. 3. The clock generation circuit according to claim 1, wherein the first DLL circuit is capable of outputting a plurality of coarsely adjusted clocks whose delay amounts are independently adjusted. It is determined whether all of the plurality of clocks are within a predetermined phase difference range with respect to the optimum phase, respectively, or are advanced or delayed when not within the predetermined phase difference range, and based on the determination result, A clock generation circuit that outputs a coarse adjustment clock whose delay amount is independently adjusted for each second DLL circuit. 4. The clock generation circuit according to claim 3, wherein the first DLL circuit delays the reception clock in a stepwise manner, and outputs an output of each stage of the delay circuit to a second DLL. And a switch train for switching whether to output to the circuit or not. A clock generation circuit for selecting a switch to be turned on in the switch train based on a determination result for all of the plurality of clocks. 5. The clock generation circuit according to claim 1, wherein the first DLL circuit and the second DLL circuit have a latch function of holding an adjusted delay amount. circuit. 6. A clock distribution circuit for distributing an internal clock generated based on a received clock input from the outside, and a local clock for generating a plurality of local clocks from the internal clock supplied from the clock distribution circuit A local clock generating circuit that adjusts a phase of the internal clock by adjusting a delay amount for delaying the internal clock in a stepwise manner and outputs a coarsely adjusted clock. A first DLL circuit, and a plurality of second DLLs for adjusting the phase of the coarse adjustment clock to output the plurality of local clocks by adjusting a delay amount for delaying the coarse adjustment clock stepwise.
A first DLL circuit, when at least one local clock of the plurality of local clocks is within a predetermined phase difference range with respect to an optimum phase or is not within the predetermined phase difference range. Determine whether it is ahead or behind,
The phase adjustment amount is changed based on the determination result, and each second DLL circuit determines whether each of the plurality of clocks is advanced or delayed with respect to the optimal phase,
A semiconductor device, wherein a phase adjustment amount is changed based on a result of the determination. 7. The semiconductor device according to claim 6, wherein said first DLL circuit is capable of outputting a plurality of coarsely adjusted clocks whose delay amounts are independently adjusted, and wherein said plurality of clocks are output. Are determined to be within a predetermined phase difference range with respect to the optimum phase, respectively, or to be advanced or delayed when not within the predetermined phase difference range. Based on the determination result, each second DLL circuit A semiconductor device that outputs a coarse adjustment clock whose delay amount is independently adjusted for each. 8. The semiconductor device according to claim 6, wherein said semiconductor device takes in input data in synchronization with edges of said plurality of local clocks. 9. The semiconductor device according to claim 8, wherein a resynchronization circuit for resynchronizing the input data respectively taken in synchronization with edges of the plurality of local clocks by a common resynchronization clock is provided. Semiconductor device. 10. The semiconductor device according to claim 6, wherein said clock distribution circuit has an H tree-shaped wiring having a load equal to a wiring distance to a distribution destination of said internal clock. 11. The semiconductor device according to claim 6, wherein the clock distribution circuit includes a reciprocating wiring for transmitting and reciprocating the internal clock, and the internal clock provided along the reciprocating wiring and reciprocating. And a local clock buffer for generating a corrected internal clock having an intermediate phase between the internal clocks which reciprocates the received internal clock. 12. The semiconductor device according to claim 6, wherein a delay amount of one stage of said first DLL circuit is equal to said plurality of second DLL circuits.
A semiconductor device larger than the delay amount of one stage of the DLL circuit. 13. The semiconductor device according to claim 6, wherein said first DLL circuit is capable of outputting a plurality of coarsely adjusted clocks whose delay amounts are independently adjusted, and wherein said plurality of clocks are output. Are determined to be within a predetermined phase difference range with respect to the optimum phase, respectively, or to be advanced or delayed when not within the predetermined phase difference range. Based on the determination result, each second DLL circuit A semiconductor device that outputs a coarse adjustment clock whose delay amount is independently adjusted for each. 14. The semiconductor device according to claim 13, wherein said first DLL circuit delays said reception clock stepwise, and outputs each stage of said delay circuit to a second DLL circuit. And a switch array for switching whether or not to output to the plurality of clocks, and selecting a switch to be turned on in the switch array based on a determination result for all of the plurality of clocks. 15. The semiconductor device according to claim 6, wherein said first DLL circuit and said second DLL circuit have a latch function of holding an adjusted delay amount. 16. The semiconductor device according to claim 15, further comprising: a calibration mode for adjusting a delay amount of said first and second DLL circuits; A semiconductor device in which first and second DLL circuits hold a delay amount when the calibration mode ends.