JP3786540B2 - Timing control circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly to a timing control circuit that generates, transmits, or distributes a synchronization signal.
[0002]
[Prior art]
In a semiconductor integrated circuit device, a phase locked loop (PLL) and a delay locked loop (DLL) are mainly used as devices for generating a clock. 1995 International Solid-State Circuits Conference Digest of Technical Papers (1995), pages 112-113 (1995 International Solid-State Circuits Conference, Digest of Technical Papers, pp. 112-113) As described above, the PLL requires a long time (several tens of microseconds) for the settling time required for generating a stable signal output in synchronization with the clock signal. Similarly, 1998 International Solid-State Circuits Conference, Digest of Technical Papers, pp.158-159 (1998 International Solid-State Circuits Conference, Digest of Technical Papers, pp.158) -159), the DLL has a long settling time (locking time) of about 100 clock cycles. Normally, when a system using a semiconductor integrated circuit device enters a standby state, the PLL or DLL is stopped, and the power consumed by the PLL or DLL is reduced. However, as described above, a long settling time is required to return the PLL and DLL from the standby state to the operating state. For this reason, in order to avoid this long settling time, some systems have a sleep mode that does not stop the PLL or DLL even during standby. In this sleep mode, power is consumed by the PLL or DLL.
[0003]
As a method of solving the above-mentioned drawbacks inherent to PLLs and DLLs, 1997 Symposium on VLSI Circuits, 1997 Symposium on VLSI Circuits, 1997 Symposium on VSI Circuits Digest of Technical Papers (1997) Digest of Technical Papers, pp. 109-110), a synchronous mirror delay (SMD) is proposed. SMD has a short settling time of 2 clock cycles. In SMD, a dummy delay circuit simulating the output load is prepared, and the clock signal is synchronized using this dummy delay circuit. For this reason, when the output load is unknown or changes, it cannot be handled. Proceedings of the 1998 Custom Integrated Circuits Conference, pp. 511-514 (Proceedings of the 1998 Custom Integrated Circuits Conference), pp. 511-514), Direct SMD (D-SMD) was proposed. However, in either SMD, only an extreme signal having a duty ratio of about 1/10 of the output clock signal can be obtained, and it cannot be used in a system that uses both rising and falling edges of the clock signal.
[0004]
[Problems to be solved by the invention]
In Japanese Patent Application No. 10-250728, the applicants have developed a timing control circuit device that overcomes all the disadvantages existing in the PLL, DLL, SMD, and D-SMD. With this device, the settling time is as short as 2 to 3 cycles of the clock signal, the clock signal can be synchronized regardless of changes in the output load, and the duty ratio of the output clock signal can be set to 1/1. .
[0005]
FIG. 3 or FIG. 4 shows the configuration of the timing control circuit device proposed by the applicants in Japanese Patent Application No. 10-250728. The input clock signal clkin31 is output as the delayed clock signal dclk31 via the buffer circuit BUF31 and the delay control circuit array DCL31, and becomes the output clock signal clkout31 via the clock driver DRV31 and the capacitive load LD31, and supplies the clock signal to the system and the like. When the period of the input clock signal clkin31 is Tin and the delay time of the clock driver DRV31 is Tdrv, the forward delay circuit array FDA31, the control circuit MCC31, and the control signal storage circuit REG31 detect the phase difference between the delayed clock signal dclk31 and the output clock signal clkout31. Then, the delay element position in the forward delay circuit array FDA31 where Tfda = Tin−Tdrv is determined. This position is transmitted to the delay control circuit array DCL31, and a position where the delay time Tdcl = Tfda = Tin−Tdrv is selected in the DCL31. Then, the delay time from the input clock signal clkin31 to the output clock signal clkout31 is Tout = Tdcl + Tdrv = Tin, and a clock signal delayed by one cycle from the input is output.
[0006]
In this way, in the timing control circuit that synchronizes the clock signal, the settling time is as short as 2 to 3 cycles, and the synchronization signal can be generated even if the output load (DRV31 or LD31 in this case) changes. As for the duty ratio, the duty ratio of the input clock signal can be transmitted as it is. Alternatively, a signal having an arbitrary duty ratio can be output by adjusting the delay element DEL31. The minimum clock frequency at which this timing control circuit device can operate can be given by Fmin = 1 / (n × Tdel). Further, the maximum value of the skew with the input signal indicated by the clock signal generated by this apparatus is Smax = Tdel. Here, n is the number of stages of the delay elements DEL31 in the delay control circuit array DCL31, and Tdel is the delay time of the delay elements DEL31 per stage. As can be seen from these relationships, in this timing control circuit device, in order to reduce the skew Smax without changing the minimum operating frequency Fmin, it is necessary to reduce the delay time Tdel per delay element of one stage, in which case the delay The number of element stages n increases. On the contrary, if the number n of delay elements is reduced without changing the minimum operating frequency Fmin, the skew Smax increases. Since the circuit area and power consumption depend on the number n of delay elements, there is a trade-off between the skew representing the performance of the device and the area / power consumption.
[0007]
An object of the present invention is to further improve the timing control circuit device proposed in the above-mentioned Japanese Patent Application No. 10-250728, and to provide a timing control circuit device with low skew, small area and low power consumption.
[0008]
That is, in the timing control circuit device, the settling time is short, the synchronization is possible even when the load such as the clock buffer changes, the duty ratio of the output clock signal can be adjusted, and the skew and area of the output clock signal can be adjusted. It is an object of the present invention to provide a timing control circuit device that can simultaneously reduce power consumption.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, a reference clock signal is input to the timing control circuit device, an internal clock signal is generated using the reference clock signal, and an output clock signal is generated via a load circuit such as a clock driver circuit. At this time, the output clock signal is fed back to the timing control circuit device and an internal clock signal is generated so that the output clock signal and the reference clock signal are in phase.
[0010]
The timing control circuit internal device includes a circuit for detecting the phase difference between the internal clock and the output clock and a delay circuit whose delay amount can be controlled. The delay circuit can change the delay amount by the detected phase difference. It has become. As a result, the output clock signal and the reference clock signal can be in phase.
[0011]
The timing control circuit device consists of a coarse timing control circuit and a fine timing control circuit. The coarse timing control circuit synchronizes the phases of the output clock signal and the reference clock signal with low accuracy, and the fine timing control circuit outputs with high accuracy. Synchronize the phase of the clock signal and the reference clock signal. The skew of the generated output clock signal is determined by a delay element in the fine timing control circuit, and the skew can be reduced by reducing the delay amount per delay element. The circuit scale of the timing control circuit can be arbitrarily increased or decreased depending on the delay amount ratio between the delay element in the coarse timing control circuit and the delay element in the fine timing control circuit. By using the optimal ratio, the circuit scale, area, and power consumption Can be reduced.
[0012]
According to the embodiment of the present invention, the settling time during which the clock signal output is stabilized is short, and as a result, it is possible to reduce the power consumption by operating it only when necessary in the semiconductor circuit device, and the output due to a decrease in the power supply voltage, etc. It has the characteristics of the timing control circuit device of Japanese Patent Application No. 10-250728 that can suppress signal control accuracy degradation and can respond to load changes in the clock output load circuit, and also has low skew, low area, and low consumption. A timing control circuit device capable of simultaneously realizing power can be provided.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0014]
FIG. 2 is a diagram showing an embodiment of the present invention.
[0015]
In the following description, it is assumed that the delay time of the buffer circuit, offset circuit, n-input NOR circuit, and divider circuit is small compared to the delay time of other components and can be ignored for convenience of explanation. To explain.
[0016]
The input clock signal clkin21 is input to the coarse timing control circuit CDLL21, and generates a delayed clock signal dclk23 and control signals cntsig21 and cntsig22. The coarse / fine adjustment converter CONV21 receives the control signals cntsig21 and cntsig22 output from the coarse adjustment timing control circuit CDLL21, and generates and transmits a delay clock signal dclk22 for the fine adjustment timing control circuit. The fine timing control circuit FDLL21 receives the delayed clock signals dclk22 and dclk23, and newly generates and outputs the delayed clock signal dclk21. The clock driver DRV21 receives the delayed clock signal dclk21 and distributes the clock signal to the capacitive load LD21 as the output clock signal clkout21. The output clock signal clkout21 is fed back to the coarse timing control circuit CDLL21 again. The coarse timing control circuit CDLL21 includes a delay control circuit array DCL22, a forward delay circuit array FDA22, a control circuit MCC22, a control signal storage circuit REG22, and further a buffer circuit BUF21, BUF24, BUF25, an n-input NOR circuit NNOR22, and a frequency divider circuit DIV22. The offset adjustment circuit offset21 is used. When the delay time of the clock driver is Tdrv, the delay time between the delayed clock signal dclk21 and the output clock signal clkout21 is Tdrv. In the coarse timing control circuit CDLL21, the output clock signal clkout21 is input to the forward delay circuit array FDA22 after being received by the offset circuit offset21, and the delayed clock signal dclk21 is input to the control circuit MCC22 after being received by the buffer circuit BUF25. When the clock cycle of the input clock signal clkin21 is Tin, the control circuit MCC22 detects a position where the delay clock signal of the forward delay circuit array FDA22 has a delay time Tfda = Tin−Tdrv. The control signal storage circuit REG22 stores the position detected by the control circuit MCC22.
[0017]
The timing of storing is based on the timing at which the delayed clock signal dclk21 is divided by the frequency dividing circuit DIV22. The frequency dividing circuit DIV22 generates an internal clock signal inclk22, gives a signal to the control signal storage circuit REG22 via the buffer circuit BUF24, and stores the detection position of the control circuit MCC22. The stored control signal cntsig22 determines the delay transmission position of the delay control circuit array DCL22, and causes the input clock signal clkin21 input via the buffer circuit BUF21 to be sent by a delay time of Tdcl = Tfda = Tin−Tdrv. Output as dclk23. When this delay signal dclk23 passes through the delay control circuit array DCL21 in the fine timing control circuit FDLL21 without delay, the delay time of the output clock signal clkout21 becomes Tout = Tdcl + Tdrv = Tin, which is exactly the same as the input clock signals clkin21 and 1 A signal delayed in cycle is transmitted, and the phases of the input signal and the output signal are synchronized. The n-input NOR circuit NNOR22 can transmit the input clock signal clkin21 as the delayed clock signal dclk23 without going through the delay control circuit row when no delay position is selected at the time of circuit activation or the like. The offset circuit offset21 is a delay element for guaranteeing the self-delay existing inside the timing control circuit device.
[0018]
However, the delay time actually selected by the delay control circuit array DCL22 is a discontinuous digital quantity, and the delay time per delay element constituting the delay control circuit array DCL22 is a phase error (skew) between input and output signals. ) Remains as. Therefore, this phase error is adjusted by the fine adjustment timing control circuit FDLL21. The coarse / fine adjustment circuit CONV21 receives the delayed clock signal transmitted to the position selected by the forward delay circuit array FDA22 as the control signal cntsig21 and transmits it as the delayed clock signal dclk22 to the forward delay circuit array FDA21 in the fine adjustment timing control circuit FDLL21.
[0019]
Similarly, the delay signal dclk23 obtained by roughly adjusting the input clock signal clkin21 by the delay control circuit array DCL22 is transmitted to the delay control circuit array DCL21 in the fine timing control circuit FDLL21. In the fine adjustment timing control circuit FDLL21, timing control similar to that of the coarse adjustment timing control circuit CDLL21 is performed, and a finely adjusted delay signal dclk21 is output. With the above operation, the input clock signal clkin21 and the output clock signal clkout21 can be synchronized within the delay time of one stage of the delay elements constituting the delay control circuit array DCL21 in the fine timing control circuit FDLL21.
[0020]
For example, the period of the input clock signal is 10 ns (frequency 100 MHz). Assuming that the delay time of one stage of delay elements constituting the delay control circuit array DCL22 in the fine timing control circuit CDLL21 is 1 ns, in order to synchronize this input clock signal without depending on the load circuit or the clock driver, 10 A stage delay element is required, and the maximum skew Smax = 1 ns at this time. In the fine adjustment timing control circuit FDLL21, assuming that the delay time of one stage of the delay elements constituting the delay control circuit array DCL21 is 100 ps, 10 stages of delay elements are required, and the maximum skew Smax = 100 ps. The number of stages of delay elements can be configured with a total of 20 stages. On the other hand, when trying to synchronize the 10ns input clock signal with the timing control circuit device of Japanese Patent Application No. 10-250728, if the number of delay elements is set to 20, the maximum skew Smax increases to 500ps. To do. Alternatively, to achieve the maximum skew Smax = 100 ps, 100 delay elements are required, which increases the circuit scale, area, and power consumption. Therefore, using the circuit in this embodiment, while maintaining the same characteristics as the timing control circuit device of Japanese Patent Application No. 10-250728, it is possible to further reduce the skew and the circuit size, area and power consumption at the same time. .
[0021]
FIG. 1 is a diagram showing a detailed embodiment of the present invention.
[0022]
  The forward delay circuit arrays FDA11, 12 can be formed by AND circuits. The control circuits MCC11 and MCC12 include an RS flip-flop circuit RSFF11, an inverter circuit, and a NOR circuit. The control signal storage circuits REG11 and REG12 are configured by a D-type flip-flop circuit DFF11. The delay control circuit arrays DCL11 and DCL12 are composed of AND circuits and NAND circuits. Further, the coarse / fine adjustment circuit CONV11 can be configured by a switch using a MOS transistor. FIG. 5 shows an example of buffer circuits BUF11, 12, 13, 14, and 15, FIG. 6 shows an example of an n-input NOR circuit NNOR11, 12, and FIG. 7 shows an example of a D-type flip-flop circuit DFF11. FIG. 8 shows an embodiment of the RS flip-flop circuit RSFF11, FIG. 9 shows an embodiment of the frequency dividing circuits DIV11 and 12, and FIG. 10 shows an embodiment of the offset circuit offset11.Here, the coarse timing control circuit CDLL11 , CDLL21 Is an example of the first timing control circuit in the present invention, and the fine timing control circuit FDLL11 , FDLL21 Is an example of the second timing control circuit in the present invention. The above clock driver circuit DRV11 , DRV21 Is an example of the clock driver circuit in the present invention, CONV11 , CONV21 Is an example of the conversion circuit in the present invention. Forward delay circuit train FDA12 , twenty two , The control circuit MCC12 , MCC22 The first delay circuit row in the present invention is formed. The delay control circuit array DCL12 , DCL22 Is an example of the second delay circuit row in the present invention. Forward delay circuit train FDA11 , twenty one , The control circuit MCC11 , MCC21 The third delay circuit row in the present invention is formed. The delay control circuit array DCL11 , DCL21 Is an example of the fourth delay circuit row in the present invention. Forward delay circuit train FDA12 , twenty two Is an example of the first forward delay circuit in the present invention, and the forward delay circuit row FDA11 , twenty one Is an example of the second forward delay circuit in the present invention, and the control circuit MCC12 , MCC22 Is an example of the first control circuit in the present invention, and the control circuit MCC11 , MCC21 Is an example of the second control circuit in the present invention.
[0023]
FIG. 11 is a diagram showing another embodiment of the present invention.
[0024]
The n-input NOR circuit existing in the coarse timing control circuit and the fine timing control circuit can be configured as NNOR 111 in FIG. In this case, although the delay time increases as the n-input NOR, an OR circuit can be arranged at each output of the control signal storage circuit, the arrangement becomes simple at the time of layout design, and the layout area can also be reduced.
[0025]
FIG. 13 is a diagram showing another embodiment of the present invention.
[0026]
The coarse / fine adjustment circuit can be configured by a MOS transistor switch as in CONV121 in FIG. 12, but when configured using a tristate buffer circuit as in CONV131 in FIG. 13, the delayed clock signals fda131 to 136 from the forward delay circuit are provided. Can reduce the load. FIG. 14 shows an embodiment of the tristate buffer circuit TSB141.
[0027]
FIG. 15 is a diagram showing another embodiment of the present invention.
[0028]
When the / Q output cntsig151 of the D-type flip-flop circuit that constitutes the control signal storage circuit REG151 is connected to the input of the AND circuit that constitutes the forward delay circuit array FDA151, the control signal storage circuit REG151 is selected after the position selected (in the figure) The clock signal is not transmitted to the AND circuit in the forward delay circuit array FDA151 on the left side. Thereby, the operating power can be reduced.
[0029]
FIG. 16 is a diagram showing another embodiment of the present invention.
[0030]
When an AND circuit is configured as shown in the figure at the output of the D-type flip-flop circuit that constitutes the control signal storage circuit REG161, when any one D-type flip-flop is selected, the latter stage (left in the figure) All D-type flip-flops are not selected. That is, the control signal storage circuit REG161 does not select two locations at the same time. If two locations are selected at the same time, two locations are selected in the delay control circuit array, and synchronization may be lost and a through current may flow, which is prevented.
[0031]
FIG. 17 is a diagram showing another embodiment of the present invention.
[0032]
In the timing control circuit device, the delay control circuit array DCL172 in the coarse adjustment timing control circuit CDLL171 is configured with m delay elements, and the delay control circuit array DCL171 in the fine adjustment timing control circuit FDLL171 is configured with j delay elements. And First, it is assumed that the k-th stage of the delay control circuit array DCL172 and the first stage of the delay control circuit array DCL171 are selected as a combination for achieving synchronization during the operation of the apparatus. During operation, the delay time of the load circuit such as the clock driver changes due to temperature rise, etc., and the position of the delay element selected in the delay control circuit array DCL171 increases from the first stage to the second stage and the third stage. In this case, it is necessary to move the selection position of the delay control circuit string DCL172 from the k-th stage to the (k + 1) -th stage in order to move to the j-th stage and move further. At this time, if the position selected by the delay control circuit array DCL171 remains at the j-th stage, the delay time corresponding to one delay element of the delay control circuit array DCL172 having a large delay time appears as a skew. In order to prevent this, when the delay element selection position of the DCL 172 changes, the delay element selection position of the DCL 171 is forcibly determined. For example, when the number of delay elements in the DCL 172 increases from the k-th stage to the (k + 1) th stage, the DCL 171 forcibly selects the first-stage delay element. Examples of a circuit that realizes this function are shown in the FMDE, CMD, and CMDH circuits of FIGS. When the delay element of DCL172 (delay element in CMD in FIG. 22) is changed by the fdmax, fdmin, and fix signals generated by FMDE, CMD, and CMDH, the delay element of DCL171 (in FMD in FIG. 22) Delay element) Forcibly determines the selected position.
[0033]
FIG. 18 is a diagram showing another embodiment of the present invention.
[0034]
The delay control circuit array DCL11 shown in FIG. 1 includes an AND circuit delay array and a NAND circuit selector. If the selector is configured with a NAND circuit in this way, a hazard may occur when the delay selection position changes. FIG. 19 is a timing chart showing the relationship between the clock signals. As shown in the chart of FIG. 19A, when the rising edge of the internal clock inclk 191 occurs while the input clock signal clkin 191 is in the high period, a hazard is generated in the output clock signal clkout 191 when the delay selection position changes here. As shown in FIG. 19 (b), when the rising edge of the internal clock inclk192 occurs while the input clock signal clkout192 is in the low period, the hazard cannot be generated. As shown in FIG. 18, when the selector circuit is configured by the tristate buffer circuit TSB181, no hazard occurs as shown in FIGS. 19 (c) and 19 (d).
[0035]
FIG. 21 is a diagram showing another embodiment of the present invention.
[0036]
In the timing control circuit device having the configuration of FIG. 20, the input clock signal clk201 first passes through the buffer circuit BUF201, and then passes through the selector SEL201 consisting of the tristate buffer circuit in the delay control circuit string DCL201, and then the delay element string consisting of AND of the DCL201. To be a delayed signal dclk201. This signal is frequency-divided by the frequency dividing circuit DIV201 to become an internal clock signal inclk201. In this case, since the relationship between the timing of the clock signal transmitted through the selector SEL201 and the timing at which the output of the control signal storage circuit REG201 is determined by the internal clock signal inclk201 changes depending on the selection position of the selector SEL201, the timing relationship is indefinite. Thus, there is a possibility that a problem such as a hazard may occur as shown in FIG. In order to solve this problem, the delay control circuit array DCL211 may be configured as shown in FIG. The DCL 211 receives an input clock signal clkin211 and a delay sequence by an AND circuit first, transmits it to a selected position, and outputs a delay signal dclk211 via a selector SEL 211 by a tri-state buffer circuit. In this case, there is almost no deviation in timing from the selection position of the selector SEL211 until the frequency dividing circuit DIV211 generates a signal, so that the timing relationship can be determined.
[0037]
FIG. 22 is a diagram showing another embodiment of the present invention.
[0038]
The timing control circuit device shown in FIG. 22 has a circuit configuration that incorporates all the embodiments described above. With this circuit, a clock synchronization circuit with low skew and low power consumption can be realized. For the elements constituting FIG. 22, FIG. 23 shows an example of FMDH, FMD, and FMDE circuits, FIG. 24 shows an example of CMDH and a CMD circuit, FIG. 25 shows an example of a CG circuit, FIG. FIG. 27 shows an embodiment of the SCE circuit, FIG. 27 shows an embodiment of the FF circuit, and FIG. 28 shows an embodiment of the DV2 circuit.
[0039]
【The invention's effect】
As described above, the present invention has the following effects. That is, in a timing control circuit device that generates an output clock signal that is synchronized with an input clock signal, the synchronous clock signal is stably generated in a short time, and the synchronization signal is supplied without depending on the load such as the output buffer of the clock signal. it can. Therefore, it is possible to design even if the clock distribution buffer circuit is unknown, and it is possible to cope with changes in the load of the clock distribution buffer after design, etc., and to change the characteristics of the load circuit due to manufacturing process variations, temperature changes, etc. Adaptable. Furthermore, by optimizing the delay amount of the delay elements in the coarse timing control circuit and the fine timing control circuit, it is possible to reduce the circuit scale, area, and power consumption while reducing the skew of the generated clock signal. It becomes.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an embodiment of the present invention.
FIG. 2 is a configuration diagram of an embodiment of the present invention.
FIG. 3 is a configuration diagram of a timing control circuit device developed in Japanese Patent Application No. 10-250728.
FIG. 4 is a configuration diagram of a timing control circuit device developed in Japanese Patent Application No. 10-250728.
FIG. 5 is a buffer circuit diagram.
FIG. 6 is an n-input NOR circuit diagram.
FIG. 7 is a D-type flip-flop circuit diagram.
FIG. 8 is an RS-type flip-flop circuit diagram.
FIG. 9 is a frequency dividing circuit diagram.
FIG. 10 is an offset circuit diagram.
FIG. 11 is an n-input NOR circuit diagram.
FIG. 12 is a coarse / fine adjustment conversion circuit diagram.
FIG. 13 is a coarse / fine adjustment conversion circuit diagram.
FIG. 14 is a circuit diagram of a tristate buffer.
FIG. 15 is a configuration diagram of another embodiment of the present invention.
FIG. 16 is a configuration diagram of another embodiment of the present invention.
FIG. 17 is an operational relationship diagram of another embodiment of the present invention.
FIG. 18 is a configuration diagram of another embodiment of the present invention.
FIG. 19 is an operation waveform of another embodiment of the present invention.
FIG. 20 is a configuration diagram of another embodiment of the present invention.
FIG. 21 is a configuration diagram of another embodiment of the present invention.
FIG. 22 is a configuration diagram of another embodiment of the present invention.
FIG. 23 is a configuration diagram of an embodiment of an FMDH, FMD, and FMDE circuit.
FIG. 24 is a configuration diagram of an embodiment of a CMDH and CMD circuit.
FIG. 25 is a configuration diagram of an embodiment of a CG circuit.
FIG. 26 is a configuration diagram of an embodiment of an SC and SCE circuit.
FIG. 27 is a configuration diagram of an embodiment of an FF circuit.
FIG. 28 is a configuration diagram of an embodiment of a DV2 circuit.
[Explanation of symbols]
BUF11, BUF12, BUF13, BUF14, BUF15, BUF21, BUF22, BUF23, BUF24, BUF25, BUF31, BUF32, BUF33, BUF41, BUF42, BUF43, BUF51, BUF201, BUF202, BUF203, BUF211, BUF212, BUF213: Buffer circuit
CDLL11, CDLL21, CDLL171, CDLL221: Coarse timing control circuit
CONV11, CONV21, CONV121, CONV131: Coarse / Fine adjustment circuit
DCL11, DCL12, DCL21, DCL22, DCL31, DCL41, DCL171, DCL172, DCL181, DCL201, DCL211: Delay control circuit array
DFF11, DFF31, DFF71: D-type flip-flop circuit
DIV11, DIV12, DIV21, DIV22, DIV31, DIV41, DIV91: Divider
DRV11, DRV21, DRV31, DRV41, DRV201, DRV211 and DRV221: Clock driver circuit
FDA11, FDA12, FDA21, FDA22, FDA31, FDA41, FDA151, FDA201, FDA211: Forward delay circuit string
FDLL11, FDLL21, FDLL171, FDLL221: Fine timing control circuit
LD11, LD21, LD31, LD41, LD201, LD211: Capacitive load
MCC11, MCC12, MCC21, MCC22, MCC31, MCC41, MCC151, MCC201, MCC211: Control circuit
NNOR11, NNOR12, NNOR21, NNOR22, NNOR31, NNOR41, NNOR61, NNOR111: n-input NOR circuit
offset11, offset21, offset31, offset41, offset101: Offset circuit
REG11, REG12, REG21, REG22, REG31, REG41, REG151, REG161, REG171, REG172, REG181, REG201, REG211: Control signal storage circuit
RSFF11, RSFF31, RSFF81: RS flip-flop circuit
SEL201, SEL211: Selector
TSB131, TSB141, TSB181: Tristate buffer
cntsig21, cntsig22, cntsig151: Control signal
clkin11, clkin21, clkin31, clkin41, clkin191, clkin192, clkin193, clkin194, clkin201, clkin221, clkin221: Input clock signal
clkout11, clkout21, clkout31, clkout41, clkout191, clkout192, clkout193, clkout194, clkout221: Output clock signal
dclk11, dclk12, dclk13, dclk21, dclk22, dclk23, dclk31, dclk41, dclk151, dclk221: Delayed clock signal
fda121, fda122, fda123, fda124, fda125, fda126, fda131, fda132, fda133, fda134, fda135, fda136: Forward delay circuit string output signal
inclk11, inclk21, inclk22, inclk191, inclk192, inclk193, inclk194: Internal clock signal
reg121, reg122, reg123, reg124, reg125, reg126, reg131, reg132, reg133, reg134, reg135, reg136: Control signal storage circuit output signal
CG, CMD, CMDH, FMD, FMDE, FMDH, FF, DIV2, SC, SCE: circuit elements constituting the embodiment of FIG.

Claims (12)

A first timing control circuit for inputting a first transmission signal and outputting a second transmission signal;
A second timing control circuit for inputting the second transmission signal and outputting a third transmission signal;
A clock driver circuit for inputting the third transmission signal and outputting a fourth transmission signal;
A conversion circuit for transmitting a fifth transmission signal between the first timing control circuit and the second timing control circuit;
The first timing control circuit feeds back the fourth transmission signal so that the phase of the first transmission signal and the fourth transmission signal is synchronized with the first accuracy. Produces
The second timing control circuit includes the third transmission signal so that the phases of the first transmission signal and the fourth transmission signal are synchronized with a second accuracy higher than the first accuracy. Generate a signal,
The first timing control circuit detects a first phase difference between the fourth transmission signal and the third transmission signal, and generates a first control signal based on the first phase difference. A first delay circuit array, and a second delay circuit array capable of changing a delay time of the first transmission signal by the first control signal,
The second timing control circuit detects a second phase difference between the fifth transmission signal and the third transmission signal, and generates a second control signal based on the second phase difference. A third delay circuit array, and a fourth delay circuit array capable of changing a delay time of the second transmission signal by the second control signal,
The conversion circuit is configured to be capable of transmitting the fifth transmission signal from the first timing control circuit to the second timing control circuit,
The first delay circuit array includes a first forward delay circuit that allows delay signals to be output from a plurality of positions in a delay path while gradually delaying the fourth transmission signal and transmitting the fourth transmission signal in one direction. A plurality of first control signals corresponding to the phase difference between each of the delayed signals output from the forward delay circuit and the third transmission signal, and the phase difference among the generated first control signals. A control signal that is regarded as having no output includes a first control circuit that indicates an output position of the delay signal corresponding to the control signal so as to be distinguishable from other output positions;
The second delay circuit row receives the plurality of first control signals, and the first forward delay circuit to an output position that can be distinguished from the other output positions by the first control signal. A delay in response to the delay time of the fourth transmission signal is applied to the first transmission signal to generate the second transmission signal;
The third delay circuit row includes a second forward delay circuit that allows a delay signal to be output from a plurality of positions in a delay path while gradually delaying the fifth transmission signal and transmitting the fifth transmission signal in one direction. A plurality of second control signals corresponding to the phase difference between each of the delayed signals output from the forward delay circuit and the third transmission signal, and the phase difference among the generated second control signals. A control signal which is regarded as having no output includes a second control circuit which indicates the output position of the delay signal corresponding to the control signal so as to be distinguishable from other output positions;
The fourth delay circuit row receives the plurality of second control signals, and the second forward delay circuit to an output position that can be distinguished from the other output positions by the second control signal. A timing control circuit device for generating the third transmission signal by applying a delay in response to the delay time of the fifth transmission signal to the second transmission signal. In claim 1,
Each of the first and second forward delay circuits includes an inverter, an AND circuit, or an OR circuit,
Each of the first and second detection circuits includes an inverter, a NOR circuit, and a flip-flop circuit,
Each of the second and fourth delay circuit rows includes an inverter, a NAND circuit, an AND circuit, a NAND circuit, an OR circuit, and a NOR circuit,
The conversion circuit is a timing control circuit device configured by a switch of a MOS transistor. In claim 1 or 2,
The first transmission signal and the fourth transmission signal are composed of synchronous signal pulses having a fixed period, and the phase of the fourth transmission signal is delayed by a desired number of pulses from the first transmission signal. Timing control circuit device. In any one of Claims 1 thru | or 3,
The third transmission signal is fed back to the first timing control circuit as the fourth transmission signal via the clock driver circuit, and the load of the clock driver circuit changes statically or dynamically. A timing control circuit device in which the phases of the first transmission signal and the fourth transmission signal are synchronized even if the delay time between the third transmission signal and the fourth transmission signal changes. In any one of Claims 1 thru | or 4,
A timing control circuit device in which phases of the first transmission signal and the fourth transmission signal are synchronized after a desired number of pulses. In claim 2,
The delay amount of the delay element constituting the second forward delay circuit in the third delay circuit row is greater than the delay amount of the delay element constituting the first forward delay circuit in the first delay circuit row. Is a small timing control circuit device. In any one of Claims 1 thru | or 6.
A timing control circuit device, wherein the conversion circuit comprises a tristate buffer circuit. In claim 2,
In each of the first and third delay circuit rows, a storage signal generated by the control signal storage circuit is given to the forward delay circuit, and the delay elements constituting the forward delay circuit are arranged at a stage subsequent to an arbitrary position. A timing control circuit device that stops transmission of a transmission signal. In claim 2,
In the first and third delay circuit arrays, a timing control circuit device that outputs a selection signal only at an arbitrary one of the storage signals generated by the control signal storage circuit, and outputs a non-selection signal otherwise. . In claim 1,
As the load of the clock driver circuit changes statically or dynamically, the delay time of the third transmission signal and the fourth transmission signal changes accordingly, and is selected in the second delay circuit row. A timing control circuit device in which a position of a delay element selected in the fourth delay circuit array is determined at an arbitrary position when the position of the delay element changes. In claim 1,
A timing control circuit device in which the second and fourth delay circuit rows are composed of an inverter, a tristate buffer, an AND circuit, a tristate buffer, an OR circuit, and a tristate buffer circuit. In claim 1,
In the second and fourth delay circuit trains, the first and second transmission signals are input to a delay train composed of an inverter, an AND circuit, or an OR circuit, and are output by a NAND circuit, a NOR circuit, or a tristate buffer circuit. A timing control circuit device which is output as second and third clock signals via a configured selector.

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