JP3932396B2 - Mixed delay locked loop circuit and clock signal synchronization method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a mixed delay locked loop circuit (DLL), and more particularly to a mixed delay locked loop circuit that synchronizes an external reference signal and an output clock signal.
[0002]
[Prior art]
Regardless of whether the local clock signal is leading or lagging relative to the reference signal, the problem of providing a clock regeneration system to a semiconductor memory device that attempts to perform stable locking within the shortest time is It has become a very important issue in the field of high-speed computers. Regeneration must be done at every location in the computer so that all regenerated clock signals are generated with minimal skew. Graphic applications such as pixel clock generation require high resolution, fast locking time and a wide frequency range. Further, the DDR DRAM circuit is required to have a minimum phase delay time smaller than a half cycle of the reference signal.
[0003]
Delay locked loop (DLL) circuits have become an important part in solving such timing problems in electronic systems. In particular, the DLL allows the designer to monitor the phase difference between the reference signal and the internal clock signal in relation to the reference signal. Such a phase difference between the reference signal and the internal clock signal results in a corresponding response delay in the semiconductor memory device. As a result, the DLL has been used to align the reference signal with the internal clock signal. There are three types of DLLs: digital, analog and hybrid (or mixed).
[0004]
A mixed DLL is disclosed in US Pat. No. 6,242,955 B1 (Assignee: Silicon Magic Corporation, Appl. No .: 09/399, 116, Fielded: Sep. 20, 1999). As disclosed in the above-mentioned patent publication, such a mixed DLL has advantages such as a faster locking time, a wide frequency range, and a high resolution, but covers the clock frequency to be used. A one cycle delay line is required. When such a one-cycle delay line is used, there is a problem that the delay change due to the influence of noise is very large. Furthermore, there is a problem that power consumption increases due to the delay line, and the required area for installation increases.
In addition, in the digital DLL, since the delay line is composed of unit delay, the movement due to the influence of noise after locking also moves due to the unit delay, so the clock jitter is very large. There is a problem that it is big.
[0005]
[Problems to be solved by the invention]
Therefore, the present invention has been made in view of the problems in the above conventional mixed delay locked loop circuit and its clock signal synchronization method, and the object of the present invention is to provide a mixture in which the delay change due to the influence of noise is not large. It is an object to provide a type delay locked loop circuit and a clock signal synchronization method thereof.
[0006]
Another object of the present invention is to provide a mixed delay locked loop circuit and a clock signal synchronization method thereof that consumes less power and requires a small area.
Furthermore, another object of the present invention is to provide a mixed delay locked loop circuit and a clock signal synchronization method thereof in which the clock jitter is not large due to the movement caused by the influence of noise after locking.
[0007]
[Means for Solving the Problems]
A mixed delay locked loop circuit according to the present invention, which has been made to achieve the above object, is a mixed delay locked loop circuit , which uses a reference clock signal input from the outside, to the mixed delay locked loop circuit. A digital half delay comprising an input buffer for outputting a first internal clock signal having a suitable signal level and a second internal clock signal having a phase difference of 180 ° from the first internal clock signal, and a plurality of unit delay units with a line, it said digital half than the phases of the output clock signal obtained by feeding the output signal from the analog delay line of the first internal clock signal input from the input buffer and the mixture delay locked loop circuit one of the internal clock signal in said delay line first internal clock signal and the second internal clock signal There controlling a delay amount internal clock signal provided selectively is delayed, the locking (locking) is performed between the first internal clock signal and the output clock signal, with the digital half delay line A digital delay unit for fixing the delay amount of the analog signal, and the analog delay line, and comparing the phase of the first internal clock signal and the output clock signal and converting the comparison result into an analog signal, and then the analog signal. And an analog delay unit that controls a delay amount by which the output signal of the digital half delay line is delayed by the analog delay line, and the digital delay unit includes the first internal clock signal and the output clock signal. A first phase comparator that compares the phase and outputs a first phase comparison signal indicating a comparison result; and receives the first phase comparison signal. A first delay controller for generating a first delay control signal for controlling a delay amount in the digital half delay line, and receiving the first phase comparison signal to receive the first internal clock signal and the output clock. A locking detector for fixing the first delay control signal when it is determined that the first internal clock signal is locked to the digital half delay line according to the first phase comparison signal. Any one of the second internal clock signals is selectively provided, and an output signal of the analog delay line is provided as the output clock signal of the mixed delay locked loop circuit. To do.
[0008]
The first delay controller includes a counter that operates according to the first phase comparison signal. When the locking detector determines that the first internal clock signal and the output clock signal are locked, the counter Is characterized by being fixed.
The analog delay unit compares a phase of the first internal clock signal and the output clock signal, outputs a second phase comparison signal indicating a comparison result, and receives the second phase comparison signal. A second delay controller for generating a second delay control signal for controlling a delay amount in the analog delay line; and converting the second delay control signal into an analog signal to control the analog delay line. And a digital / analog converter provided to the analog delay line.
A clock divider for dividing the reference clock signal and providing it to the first delay controller and the second delay controller is further provided.
An output duplicating delay unit that feeds back the output clock signal to the first phase comparator and the second phase comparator is further provided .
[0009]
Also, a mixed delay locked loop circuit according to the present invention made to achieve the above object is a mixed delay locked loop circuit , which uses the input clock signal input from the outside and uses the mixed delay locked loop. An input buffer for outputting a first internal clock signal having a signal level suitable for a circuit, a second internal clock signal having a phase difference of 180 ° from the first internal clock signal, and a plurality of unit delay units. The first internal clock signal or the second internal clock signal is selectively provided from the input buffer, a digital half delay line for delaying the input clock signal by a digital method for a predetermined time, and the first internal clock signal ; position of an output clock signal obtained by feeding the output signal from the analog delay line of the mixing delay locked loop circuit A first phase comparator that outputs a first phase comparison signal indicating a comparison result, and a first delay control signal that receives the first phase comparison signal and controls a delay amount in the digital half delay line. Generating and providing to the digital half delay line and receiving the first phase comparison signal and determining that the first internal clock signal and the output clock signal are locked; The locking detector for fixing the first delay control signal, the analog delay line for delaying the output signal of the digital half delay line for a predetermined time by an analog method, and the phase of the first internal clock signal and the output clock signal are compared. A second phase comparator that outputs a second phase comparison signal indicating a comparison result, and a delay in the analog delay line when the second phase comparison signal is received. A second delay controller for generating a second delay control signal for controlling a delay amount; and a digital signal for converting the second delay control signal into an analog signal and providing the analog delay line to the analog delay line for controlling the analog delay line. / Analog converter.
[0010]
In order to achieve the above object, a clock signal synchronization method for a mixed delay locked loop circuit according to the present invention synchronizes an output clock signal generated with respect to a reference clock signal input from the outside in the mixed delay locked loop circuit. a method for a second having a first internal clock signal having a signal level suitable for the mixing delay locked loop circuit using the reference clock signal and the phase difference between the first internal clock signal and the 180 ° The phase of the first internal clock signal and the output clock signal obtained by feeding back the output signal from the analog delay line of the mixed delay locked loop circuit is compared with the first phase by generating and outputting the internal clock signal . generating a phase comparison signal, comprising a plurality of unit delay unit by using the first phase comparison signal by a digital half delay line And controlling the amount of delay of the internal clock signal serial any one of the internal clock signal in the first internal clock signal and the second internal clock signal is provided selectively, the said first internal clock signal When locking is performed with the output clock signal, the phase of the first internal clock signal and the output clock signal are compared with the step of fixing the delay amount of the internal clock signal in the digital half delay line. Generating a second phase comparison signal, converting the second phase comparison signal to an analog signal, and controlling a delay amount by which the output signal of the digital half delay line is delayed by the analog delay line using the analog signal; And a step of performing.
[0011]
According to the present invention having such a configuration, since the length of the delay line is shortened, the delay change due to the influence of noise is not large. Furthermore, power consumption and required area are reduced, and there is an advantage that clock jitter due to the influence of noise after locking is not large.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Next, a specific example of an embodiment of a mixed delay locked loop circuit and a clock signal synchronization method according to the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram of a mixed delay locked loop circuit (hereinafter referred to as a mixed DLL circuit) having a half delay line according to the present invention. As shown in FIG. 1, the mixed DLL according to the present invention is roughly divided into a digital delay unit 100 and an analog delay unit 200. The digital delay unit 100 includes a phase detector 101, a delay controller 103, a locking detector 105, a phase delay monitor 107, a Mux 109, and a digital (coarse) delay line 111. On the other hand, the analog delay unit 200 includes a phase detector 201, a delay controller 203, a digital / analog converter 205, and an analog (fine) delay line 207.
[0013]
The phase detector 201 shown in FIG. 1 is included in the digital delay unit 100 for the convenience of drawing, but is an element constituting the analog delay unit 200. In addition, an input buffer 301, an output duplication delay unit 303, and a clock frequency divider 305 are further provided. REF_CLK shown in FIG. 1 is a reference clock signal input from the outside, DLL_CLK is a clock signal generated by the mixed DLL circuit of the present invention, FB_CLK is the first phase detection via the output duplication delay 303 via DLL_CLK CLK is a clock signal fed back to the detector 101 and the second phase detector 201, CLK is an output clock signal of the input buffer 301, CLK_B is another output clock signal of the input buffer 301, and phase-shifted from CLK by 180 ° Each represents a clock signal.
[0014]
First, the phase detector 101 in the digital delay unit 100 compares the phase difference between the output signal CLK of the input buffer 301 and the feedback signal FB_CLK to generate an up signal (UP) or a down signal (DN). The output signal of the phase detector 101 is provided to the delay controller 103, the locking detector 105, and the phase delay monitor 107. The delay controller 103 includes a counter (not shown) that stores the degree of delay in the digital (coarse) delay line 111 and changes the value of the counter according to the output signal of the phase detector 101. The locking detector 105 receives the up signal (UP) or the down signal (DN) from the phase detector 101, determines whether locking is possible between the internal clock signal CLK and the feedback clock signal FB_CLK, and the two clocks. When it is confirmed that the signals are locked to each other, the counter inside the delay controller 103 is fixed. The phase delay monitor 107 determines whether or not half delay with respect to the frequency range of the clock signal provided using the output signal of the phase detector 101 is possible. The Mux 109 selectively supplies to the digital (coarse) delay line 111 the first internal clock signal CLK or the second internal clock signal CLK_B phase-shifted by 180 ° from the internal clock signal according to the output signal of the phase delay monitor 107. Acts as a switch. The digital (coarse) delay line 111 is configured by a unit delay, and a clock signal provided via the Mux 109 is delayed for a predetermined time and provided to the analog (fine) delay line 207 of the analog delay unit 200. .
[0015]
Next, in the analog delay unit 200, the phase detector 201 compares the phase difference between the first internal clock signal CLK and the feedback clock signal FB_CLK, generates an up signal (UP) or a down signal (DN), and a delay controller. 203. The delay controller 203 includes a counter (not shown) that stores the degree of delay in the analog (fine) delay line 207, and changes the counter value according to the output of the phase detector 203. The digital / analog converter 205 converts the counter value of the delay controller 203 into a current amount that is an analog signal.
On the other hand, the input buffer 301 receives the reference clock signal REF_CLK from the outside, and changes it to a signal level suitable for the DLL circuit. The output duplication delay unit 303 feeds back the internal clock signal DLL_CLK generated by the DLL circuit and provides it to the phase detectors 101 and 201. The clock divider 305 appropriately divides the reference clock signal and provides it to the delay controllers 103 and 203 to operate the counters in the delay controllers 103 and 203.
[0016]
The digital delay unit 100 shown in FIG. 1 adjusts the digital (coarse) delay line 111 composed of unit delays using a digital method to generate an external reference signal REF_CLK provided through the input buffer 301. Delay with coarse precision. The analog delay unit 200 finely adjusts the analog (fine) delay line 207 using an analog method after the digital delay unit 100 is locked, and delays the output signal of the digital (coarse) delay line 111 with high precision.
[0017]
More specifically, the phase detector 101 in the digital delay unit 100 compares the external clock signal CLK with the feedback clock signal FB_CLK to determine UP / HOLD / DOWN. Only the half delay line must cover the desired external reference clock signal REF_CLK range, and the unit delay is selected from the beginning via the delay controller 103 with the digital (coarse) delay line 111 composed of unit delays. Therefore, the phase delay monitor 107 determines the UP / DOWN signal of the phase detector 101 and selects the first internal clock signal CLK or the second internal clock signal CLK_B. The delay controller 103 checks the number of up signals and down signals so that the coarse delay can be increased or decreased by the output signal of the phase detector 101. The locking detector 105 detects the HOLD state that is the output of the phase detector 101 and stops the delay controller 103. If the digital delay unit 100 maintains the locked state in this way, it will have a jitter equivalent to the unit delay. Next, fine tuning by the operation of the analog delay unit 200 is performed on the jitter of the unit delay. Done.
[0018]
After the delay controller 103 is fixed by the locking detector 105 of the digital delay unit 200, the phase detector 201 compares the clock signal CLK with the feedback clock signal FB_CLK so that the delay can be finely tuned ( Determine UP / DOWN (DOWN). The delay controller 203 checks the number of up signals (UP) or down signals (DN) using an internal counter (not shown) so that the delay can be increased or decreased by the output signal of the phase detector 201. To do. The digital / analog converter 205 converts the counter value of the delay controller 203 into a current amount that is an analog signal. The fine delay is adjusted by adjusting the current of the digital / analog converter 205.
[0019]
The present invention is not limited to the above-described embodiments. Various modifications can be made without departing from the technical scope of the present invention.
[0020]
【The invention's effect】
As described above, according to the mixed delay locked loop circuit and the clock signal synchronization method of the present invention having such a configuration, the delay line length is shortened, so that the delay change due to the noise is not large. Further, power consumption and required area are reduced, and there is an advantage that clock jitter due to the influence of noise after locking is not large.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a mixed delay locked loop circuit according to the present invention.
[Explanation of symbols]
100 Digital Delay Unit 101 Phase Detector 103 Delay Controller 105 Locking Detector 107 Phase Delay Monitor 109 Mux
111 Digital (Coarse) Delay Line 200 Analog Delay Unit 201 Phase Detector 203 Delay Controller 205 Digital / Analog Converter 207 Analog (Fine) Delay Line 301 Input Buffer 303 Output Duplicate Delay 305 Clock Divider

Claims (12)

A mixed delay locked loop circuit,
Using a reference clock signal input from the outside, a first internal clock signal having a signal level suitable for the mixed delay locked loop circuit, and a second internal clock having a phase difference of 180 ° with respect to the first internal clock signal An input buffer for outputting a clock signal;
An output clock having a digital half delay line composed of a plurality of unit delay units, and feeding back the first internal clock signal input from the input buffer and the output signal from the analog delay line of the mixed delay locked loop circuit An internal clock signal in which one of the first internal clock signal and the second internal clock signal is selectively provided is delayed by the digital half delay line by comparing the phase with the signal. A digital delay unit that controls a delay amount and locks the delay amount in the digital half delay line when locking is performed between the first internal clock signal and the output clock signal;
The analog delay line is provided, the phases of the first internal clock signal and the output clock signal are compared, and the comparison result is converted into an analog signal. An analog delay unit for controlling the delay amount by which the output signal of the delay line is delayed ,
The digital delay unit compares the phase of the first internal clock signal with the phase of the output clock signal and outputs a first phase comparison signal indicating a comparison result;
A first delay controller that receives the first phase comparison signal and generates a first delay control signal that controls a delay amount in the digital half delay line;
A locking detector for fixing the first delay control signal when the first phase comparison signal is received and it is determined that the first internal clock signal and the output clock signal are locked ;
According to the first phase comparison signal, one of the first internal clock signal and the second internal clock signal is selectively provided to the digital half delay line, and an output of the analog delay line is provided. A mixed delay locked loop circuit, wherein a signal is provided as the output clock signal of the mixed delay locked loop circuit.   The first delay controller includes a counter that operates according to the first phase comparison signal. When the locking detector determines that the first internal clock signal and the output clock signal are locked, the counter 2. The mixed delay locked loop circuit according to claim 1, wherein is fixed. The analog delay unit compares a phase between the first internal clock signal and the output clock signal and outputs a second phase comparison signal indicating a comparison result ; and
A second delay controller that receives the second phase comparison signal and generates a second delay control signal that controls a delay amount in the analog delay line ;
The digital / analog converter according to claim 1, further comprising a digital / analog converter that converts the second delay control signal into an analog signal and provides the analog delay line to the analog delay line for controlling the analog delay line. Mixed delay locked loop circuit. Mixing delay locked according to claim 1 or 3, characterized in that it further comprises a clock divider providing the reference clock signal to the frequency division to the first delay controller and a second delay controller Loop circuit. Mixing delay locked loop circuit according to claim 1 or 3, characterized by further comprising an output replica delay unit for feeding back the output clock signal to said first phase comparator and second phase comparators. A mixed delay locked loop circuit,
A first internal clock signal having a signal level suitable for the mixed delay locked loop circuit using an input clock signal input from the outside, and a second internal having a phase difference of 180 ° from the first internal clock signal An input buffer for outputting a clock signal;
A digital half delay line configured by a plurality of unit delay units, wherein the first internal clock signal or the second internal clock signal is selectively provided from the input buffer and delays the input clock signal by a digital method for a predetermined time; ,
A first phase for outputting a first phase comparison signal indicating a comparison result by comparing phases of the first internal clock signal and an output clock signal obtained by feeding back an output signal from the analog delay line of the mixed delay locked loop circuit. A comparator;
A first delay controller that receives the first phase comparison signal, generates a first delay control signal for controlling a delay amount in the digital half delay line, and provides the first delay control signal to the digital half delay line;
A locking detector for fixing the first delay control signal when the first phase comparison signal is received and it is determined that the first internal clock signal and the output clock signal are locked;
An analog delay line that delays the output signal of the digital half delay line for a predetermined time in an analog manner;
A second phase comparator for outputting a second phase comparison signal indicating a comparison result by comparing phases of the first internal clock signal and the output clock signal ;
A second delay controller that receives the second phase comparison signal and generates a second delay control signal that controls a delay amount in the analog delay line ;
A mixed delay locked loop circuit comprising: a digital / analog converter that converts the second delay control signal into an analog signal and supplies the analog delay line to the analog delay line for control of the analog delay line . The first delay controller includes a counter that operates according to the first phase comparison signal. When the locking detector determines that the first internal clock signal and the output clock signal are locked, the counter 7. The mixed delay locked loop circuit according to claim 6 , wherein is fixed. Wherein the digital half delay line, wherein further comprising a Mux (multiplexer) to any one of the internal clock signal in accordance with said first phase comparison signal first and said second internal clock signal selectively provides The mixed delay locked loop circuit according to claim 6 . The mixed type according to claim 6 , further comprising a clock divider that divides an input clock signal input from the outside and provides the divided clock signal to the first delay controller and the second delay controller. Delay locked loop circuit. 7. The mixed delay locked loop circuit according to claim 6 , further comprising an output duplicating delay device for feeding back the output clock signal to the first phase comparator and the second phase comparator . A method of synchronizing an output clock signal generated with respect to a reference clock signal input from the outside in a mixed delay locked loop circuit ,
Using the reference clock signal, a first internal clock signal having a signal level suitable for the mixed delay locked loop circuit and a second internal clock signal having a phase difference of 180 ° from the first internal clock signal are generated. And output stage ,
A first phase comparison signal is generated by comparing phases of the first internal clock signal and an output clock signal obtained by feeding back an output signal from an analog delay line of the mixed delay locked loop circuit. Delay of an internal clock signal in which any one of the first internal clock signal and the second internal clock signal is selectively provided by a digital half delay line including a plurality of unit delay units. Controlling the amount;
When locking is performed between the first internal clock signal and the output clock signal, fixing a delay amount of the internal clock signal in the digital half delay line ;
Comparing the phase of the first internal clock signal and the output clock signal to generate a second phase comparison signal, and converting the second phase comparison signal into an analog signal;
A method of synchronizing the clock signal of the mixed delay locked loop circuit, comprising: controlling a delay amount by which the output signal of the digital half delay line is delayed by the analog delay line using the analog signal. According to the first phase comparison signal, claims and further comprising any one step of selectively providing the internal clock signal in said digital half delay the first and the second internal clock signal on line Item 12. A clock signal synchronization method for a mixed delay locked loop circuit according to Item 11 .

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