KR100784028B1 - Delay locked loop - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay locked loop (DLL), in order to supply a low voltage to the first delay line portion having a relatively large unit delay composed of multiple stages to have a wide synchronization range, and to reduce jitter. The second delay line portion, which is composed of a minimum unit delay stage, is provided with a delay lock loop that can minimize jitter while securing a wider sync range in a limited layout area by applying a high voltage.

DLL, Sync Range, Jitter, First and Second Delay Lines, Low Voltage, High Voltage

Description

Delay locked loop             

1 is a block diagram schematically illustrating a conventional delay lock loop.

2 is a graph showing a change in delay time according to a change in operating voltage for explaining the principle to which the present invention is applied.

3 is a block diagram schematically illustrating a delay lock loop according to a first embodiment of the present invention;

4 is a block diagram schematically illustrating a delay lock loop according to a second embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

11, 21 and 31: voltage generators 12, 22 and 32: first delay line section

13, 23, and 33: second delay line section 14, 24, and 34: first phase detector

15, 25, and 35: first shift register

16, 26, and 36: second phase detectors 17, 27, and 37: second shift register

18, 28, and 38: replica 39: frequency detector

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay locked loop (hereinafter, referred to as a "DLL"). In particular, a low voltage is supplied to a first delay line unit having a relatively large unit delay composed of multiple stages in order to have a wide synchronization range. In addition, the present invention relates to a DLL capable of minimizing jitter while securing a wider synchronization range in a limited layout area by applying a high voltage to a second delay line portion having a minimum unit delay stage to reduce jitter.

In a synchronous semiconductor memory device such as SDRAM which performs a high speed operation in synchronization with a clock supplied from the system side, each internal circuit is operated at a timing in synchronization with the rising edge of the clock or with a predetermined phase delayed from the rising edge. In particular, in the case of SDRAM, the circuit of the column system is configured as a pipeline, the pipeline gate provided between the plurality of pipeline circuits is opened by an internal control clock synchronized with the clock, and the data of the memory cell is transferred and output.

However, a double data rate (DDR) scheme has been proposed that increases the data transfer rate by performing internal pipeline operations not only on the rising edge of the clock but also on the falling edge of the clock. In the DDR system, the internal control clock is synchronized with the clock rise and the internal control clock is synchronized with the clock fall, or the internal control clock is delayed, or the internal control clock and the clock fall 90 ° from the clock rise are controlled. A 90 ° delayed internal control clock controls internal operation timing. Further, as a modification, the internal operation timing is controlled by an internal control clock that delays the A ° phase of the clock and an internal control clock that delays the A ° phase from the fall of the clock.

In this case, it is required to generate an internal control clock delaying the A ° phase and an internal control clock delaying the 180 ° + A ° phase from the rise of the reference clock. As a circuit for generating an internal control clock with a predetermined phase delay from the rise of the reference clock, there is a DLL as shown in FIG.

1 is a block diagram schematically showing a conventional DLL.

The voltage generator 11 generates a predetermined voltage and simultaneously supplies the first delay line portion 12 and the second delay line portion 13. The first phase detector 14 feedbacks the internal clock intCLK input through the reference clock refCLK and the replica 18, compares their phases, and detects the difference. A phase comparison result signal is output. The first shift register 15 shifts in response to the two phase comparison result signals from the first phase detector 14 and then outputs a control signal for determining the delay time of the first delay line portion 12. The first delay line unit 12 inputs a predetermined voltage generated from the reference clock refCLK and the voltage generator 11 and sets the reference clock refCLK according to a control signal from the first shift register 15 for a predetermined time. The clock CLK is output with a delay. The second phase detector 16 feedbacks an internal clock intCLK input through the reference clock refCLK and the replica 18, and enables the signal EN from the first phase detector 14. As a result, the phases of the reference clock refCLK and the internal clock intCLK are compared and the difference is detected. Accordingly, two phase comparison result signals are output. The second shift register 17 shifts in response to the two phase comparison result signals from the second phase detector 16 and then outputs a control signal for determining the delay time of the second delay line section 13. The second delay line unit 13 inputs the clock signal CLK output from the first delay line unit 12 and the predetermined voltage generated from the voltage generator 11, and controls from the second shift register 17. The internal clock intCLK is output by delaying the clock signal CLK by a predetermined time according to the signal.

In the above description, the first delay line portion and the second delay line portion include a plurality of unit delays, and the first delay line portion includes a relatively large unit delay in several stages in order to have a wide locked range. The second delay line portion is configured with a minimum unit delay stage in order to reduce jitter. Therefore, the minimum size of the second delay line portion must be greater than or equal to the unit delay of the first delay line portion. In this case, the maximum synchronization range may be expressed by adding the maximum delay of the first delay line unit and the maximum delay of the second delay line unit. Therefore, in order to extend the synchronization range and minimize jitter, the first delay line portion should have a larger delay to increase coverage, and the second delay line portion should have a smaller delay to improve resolution. . In the former case, a large layout area is required to have a large delay, so that the delay cannot be increased indefinitely. Also, the latter suffers some jitter because the latter is limited by the process technology when implementing the minimum delay, and therefore cannot achieve sub-limit delays.

An object of the present invention is to provide a DLL capable of securing a wider synchronization range and minimizing jitter in a limited layout area.

Another object of the present invention is to supply a low voltage to the first delay line portion having a relatively large unit delay composed of multiple stages to have a wide synchronization range, and to provide a low jitter, and a second delay composed of a minimum unit delay stage. By supplying high voltage to the line part, it is possible to provide a DLL that can obtain a wider sync range and minimize jitter in a limited layout area.

In the present invention, the first delay line portion having a relatively large unit delay composed of multiple stages in order to have a wide synchronization range is provided with a low voltage such as 1.5 V or 1.0 V, for example, and the minimum unit delay stage for reducing jitter. The second delay line portion is configured to apply a higher voltage than the voltage supplied to the first delay line portion, for example, 2.5V, 3.0V, to secure a wider synchronization range in a limited layout area. Minimize jitter In other words, by lowering the operating voltage of the circuit, the delay is increased by supplying a low voltage to the first delay line to realize the maximum delay in the limited layout area. On the contrary, increasing the operating voltage of the circuit reduces the delay. When the high voltage is supplied to the second delay line portion using the characteristic, the jitter can be minimized by having the minimum unit delay in the same layout area.

The DLL according to the present invention includes a voltage generator for generating a first voltage and a second voltage that is higher than the first voltage, inputting a reference clock and an internal clock to detect a phase difference, and outputting an enable signal. A first phase detector, a first shift register for outputting a first control signal after shifting in response to a phase detection signal from the first phase detector, and the reference clock according to the first voltage and the first control signal A first delay line section for outputting a clock delayed by a predetermined time, a second phase detector for inputting the reference clock and the internal clock according to an enable signal from the first phase detector, and detecting a phase difference; A second shift register for outputting a second control signal after the shift in response to the phase detection signal from the second phase detector; And a second delay line portion for outputting an internal clock by delaying the clock from the first delay line portion for a predetermined time according to a second voltage and the second control signal.

In addition, the DLL according to the present invention further comprises a frequency detector for detecting the frequency of the reference clock, the voltage generator according to the output signal of the frequency detector to fix the first voltage and vary the second voltage, or The first voltage and the second voltage are fixed, or the first and second voltages are varied to output the first and second voltages.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

FIG. 2 is a graph showing a change in delay time according to a change in operating voltage for explaining the principle to which the present invention is applied, and shows a result of simulating a unit delay constituting the delay line unit by changing the operating voltage at room temperature.

As shown, it can be seen that the delay is increased by about 50% when the operating voltage is reduced to 1.5V, and the delay is decreased by about 30% when the operating voltage is increased to 2.5V. Using this characteristic, a low voltage is supplied to the first delay line part and a high voltage is supplied to the second delay line part. The first delay line part is about 10% in a limited layout area each time the operating voltage is decreased by 0.1V. The synchronization range is widened, and the resolution of the second delay line portion increases by about 6% each time the operating voltage is increased by 0.1V.

3 is a block diagram schematically illustrating a DLL according to a first embodiment of the present invention.

The voltage generator 21 generates two voltages having different potentials, that is, a low voltage and a high voltage, and supplies them to the first delay line portion 22 and the second delay line portion 23, respectively. The first phase detector 24 inputs a reference clock (refCLK) and an internal clock (intCLK) input through the replica 18, compares their phases, and detects the difference. Two phase comparison result signals are output. The first shift register 25 shifts in response to the two phase comparison result signals from the first phase detector 24 and then outputs a control signal for determining the delay time of the first delay line section 22. In order to have a wide synchronization range, the first delay line unit 22 having a relatively large unit delay composed of multiple stages inputs a relatively low voltage among two voltages generated from the reference clock refCLK and the voltage generator 21, The clock CLK obtained by delaying the reference clock refCLK for a predetermined time is output in accordance with the control signal from the first shift register 25. The second phase detector 26 inputs an internal clock intCLK input through the reference clock refCLK and the replica 28 and then enables the enable signal EN from the first phase detector 24. As a result, the phases of the reference clock refCLK and the internal clock intCLK are compared and the difference is detected. Accordingly, two phase comparison result signals are output. The second shift register 27 shifts in response to the two phase comparison result signals from the second phase detector 26 and then outputs a control signal for determining the delay time of the second delay line section 23. In order to reduce jitter, the second delay line unit 23 configured as the minimum unit delay stage has a relative value between the clock CLK output from the first delay line unit 22 and the two voltages generated from the voltage generator 21. Inputs a high high voltage, delays the clock CLK for a predetermined time according to the control signal from the second shift register 27, and outputs the internal clock intCLK.

As described above, a fixed low voltage is supplied to the first delay line part and a fixed high voltage is supplied to the second delay line part. In addition to the method of supplying a fixed high voltage, the voltage output from the voltage generator is varied according to the frequency change of the reference clock. 2 may be supplied to the delay line unit, an example of which will be described with reference to FIG. 4.

4 is a block diagram schematically illustrating a DLL according to a second embodiment of the present invention.

The frequency detector 39 inputs a reference clock refCLK, detects the height of the frequency, and converts it into the voltage or current. The output signal thus converted is used as a control signal of the voltage generator 31. The voltage generator 31 generates two voltages having different potentials, that is, a low voltage and a high voltage according to the output signal of the frequency detector 39, respectively, to the first delay line portion 32 and the second delay line portion 33. Supply. The voltage generator 31 that determines the output voltage according to the output signal of the frequency detector 39 may be configured in various combinations such as high voltage fixed and low voltage variable, high voltage variable and low voltage fixed, or high voltage variable and low voltage variable. Therefore, it is preferable to configure in the form of high voltage fixed and low voltage variable. The first phase detector 34 feedbacks the internal clock intCLK input through the reference clock refCLK and the replica 38 and compares their phases to detect the difference. Phase comparison result signals are outputted. The first shift register 35 outputs a control signal for determining the delay time of the first delay line part 32 after the shift from the first phase detector 34 in response to the two phase comparison result signals. In order to have a wide synchronization range, the first delay line unit 32 having a plurality of relatively large unit delays inputs a relatively low voltage among two voltages generated from the reference clock refCLK and the voltage generator 31. In response to the control signal from the first shift register 35, a clock CLK obtained by delaying the reference clock refCLK for a predetermined time is output. The second phase detector 26 inputs an internal clock intCLK input through the reference clock refCLK and the replica 38 and then enables the enable signal EN from the first phase detector 34. As a result, the phases of the reference clock refCLK and the internal clock intCLK are compared and the difference is detected. Accordingly, two phase comparison result signals are output. The second shift register 37 shifts in response to the two phase comparison result signals from the second phase detector 36 and outputs a control signal for determining the delay time of the second delay line section 33. In order to reduce jitter, the second delay line unit 33 having the minimum unit delay stage includes a clock signal CLK output from the first delay line unit 32 and two voltages generated from the voltage generator 31. A relatively high high voltage is input, and the internal clock intCLK is output by delaying the clock CLK for a predetermined time according to the control signal from the second shift register 37.

When configured as in the second embodiment of the present invention, it is possible to configure a DLL having a fixed delay line and whose synchronization range varies according to a frequency change.

As described above, according to the present invention, a first delay line portion having a relatively large unit delay composed of multiple stages in order to have a wide synchronization range is provided with a minimum unit delay stage to supply a low voltage and to reduce jitter. By supplying high voltage to the two delay line sections, a wider sync range and limited jitter can be achieved over a limited layout area. In addition, there is an additional effect of extending or reducing the synchronization range of the DLL by changing the low voltage and the high voltage output from the voltage generator.

Claims (7)

A voltage generator for generating a first voltage and a second voltage that is higher than the first voltage; A first phase detector for inputting a reference clock and an internal clock to detect a phase difference thereof, and outputting an enable signal; A first shift register for outputting a first control signal after the shift in response to the phase detection signal from the first phase detector; A first delay line unit configured to output a clock obtained by delaying the reference clock by a predetermined time according to the first voltage and the first control signal; A second phase detector for detecting a phase difference by inputting the reference clock and the internal clock according to the enable signal from the first phase detector; A second shift register for outputting a second control signal after shifting in response to the phase detection signal from the second phase detector; And a second delay line portion for outputting an internal clock by delaying the clock from the first delay line portion for a predetermined time according to the second voltage and the second control signal. delete 2. The delay lock loop as recited in claim 1, wherein the first and second delay line portions have a delay time determined according to first and second control signals from the first and second shift registers. A frequency detector for detecting a frequency of the reference clock, A voltage generator for generating a first voltage and a second voltage having different potentials according to the output signal of the frequency detector; A first phase detector for inputting a reference clock and an internal clock to detect a phase difference thereof, and outputting an enable signal; A first shift register for outputting a first control signal after the shift in response to the phase detection signal from the first phase detector; A first delay line unit configured to output a clock obtained by delaying the reference clock by a predetermined time according to the first voltage and the first control signal; A second phase detector for detecting a phase difference by inputting the reference clock and the internal clock according to the enable signal from the first phase detector; A second shift register for outputting a second control signal after shifting in response to the phase detection signal from the second phase detector; And a second delay line portion for outputting an internal clock by delaying the clock from the first delay line portion for a predetermined time according to the second voltage and the second control signal. 5. The delay lock loop as recited in claim 4, wherein the second voltage is higher than the first voltage. The voltage generator of claim 4, wherein the voltage generator is configured to fix the first voltage and to vary the second voltage, to vary the first voltage and to fix the second voltage according to an output signal of the frequency detector. And outputting first and second voltages by varying the second voltage. 5. The delay lock loop as recited in claim 4, wherein the first and second delay line portions have a delay time determined according to first and second control signals from the first and second shift registers.

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