CN109831206B - Delay locked loop and delay locking method - Google Patents
Delay locked loop and delay locking method Download PDFInfo
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Abstract
The invention provides a delay locking ring and a delay locking method, comprising the following steps: an analog master delay line that delays the reference clock signal based on the master delay control word; a digital phase discrimination module for identifying the phase difference of the reference clock signal before and after delay; the main delay control word is adjusted based on the phase difference, and the main delay control word corresponding to one period of delay is assigned to the digital main control module for setting the delay control word; the digital slave control module takes the set delay control word with the set proportion as the slave delay control word; an analog slave delay line that controls the delay of the input clock signal based on the slave delay control word. Delaying the reference clock signal by one period based on the phase locked loop control; the corresponding main delay control word is assigned to the set delay control word, and the delay of the input clock signal is adjusted after multiplying the set ratio. The invention adopts the digital phase discriminator and the digital controller, has higher reliability and is more stable in loop; by adopting the analog delay line, the delay can be adjusted, and the circuit debugging difficulty is simplified.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a delay locked loop and a delay locking method.
Background
With the development of modern integrated circuit technology, the chip scale is continuously increased, the working frequency is continuously improved, and the on-chip clock distribution quality and clock delay are becoming more and more important. The delay locked loop (Delay Locked Loop, DLL) can meet the accurate synchronization requirement of the on-chip high-speed clock, eliminate clock delay, realize zero transmission delay and minimize the deviation between the clock input signal and the clock pins inside the whole chip. As a very important part of the integrated circuit design, the delay locked loop has become a focus of attention, and is more widely used in various SoC (System on Chip) chips.
In the application of the SDIO (Secure Digital Input and Output) protocol standard, the delay locking ring can realize clock alignment between the host and the SD card, and ensure that the time sequence between the clock and the data can meet the requirement, thereby ensuring the correctness of data transmission. Meanwhile, the delay locking ring can adapt to different working frequencies and is suitable for different new and old versions of the SDIO standard.
However, the traditional all-digital delay locked loop has complex and complicated time sequence problems, and once the time sequence is wrong, the whole loop cannot work normally; the accuracy of conventional analog delay locked loops is greatly inadequate. Therefore, how to provide a delay locked loop with simple timing and high accuracy has become one of the problems to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a delay locked loop and a delay locked method for solving the problems of complex delay locked loop timing, poor accuracy, and the like in the prior art.
To achieve the above and other related objects, the present invention provides a delay locked loop comprising:
the system comprises an analog main delay line, a digital phase discrimination module, a digital main control module, a digital slave control module and an analog slave delay line;
the analog main delay line is connected to the output end of the digital main control module, receives a reference clock signal, and controls the delay of the reference clock signal based on a main delay control word output by the digital main control module;
the digital phase discrimination module is connected to the output end of the analog main delay line, and is used for receiving the reference clock signal and identifying the phase difference before and after the delay of the reference clock signal;
the digital main control module is connected to the output end of the digital phase discrimination module, adjusts the main delay control word based on the phase difference before and after the delay of the reference clock signal, and assigns the main delay control word corresponding to the delay of the reference clock signal by one period to the set delay control word;
the digital slave control module is connected to the output end of the digital master control module, receives a control signal, multiplies the set delay control word by a set proportion based on the control signal and then outputs the set delay control word as a slave delay control word;
the analog slave delay line is connected to the output end of the digital slave control module, receives an input clock signal with the same frequency as the reference clock signal, and controls the delay of the input clock signal based on the slave delay control word.
Optionally, the analog main delay line includes a plurality of analog delay units, a first input end of each analog delay unit is connected to a first output end of a front stage, a second input end of each analog delay unit is connected to a second output end of a rear stage, the first output end outputs a delay signal of a first input end signal of a current stage analog delay unit, the second output end selects a first output end signal of the front stage or a second output end signal of the rear stage through the main delay control word to output, and a control end is connected to the main delay control word; the first input end of the first-stage analog delay unit is used as the input end of the analog main delay line, and the second output end of the first-stage analog delay unit is used as the output end of the analog main delay line; the second input end of the last stage analog delay unit is connected with a low level.
More optionally, the analog delay unit includes a delay and a data selector; the input end of the delayer is used as the first input end of the analog delay unit, and the output end of the delayer is used as the first output end of the analog delay unit; the first input end of the data selector is connected with the output end of the delayer, the second input end is used as the second input end of the analog delay unit, the control end is connected with the main delay control word, and the output end is used as the second output end of the analog delay unit, wherein the control end of the data selector outputs an output signal of the delayer when in high level.
More optionally, the analog slave delay line is identical in structure to the analog master delay line.
Optionally, the digital phase discrimination module includes a single analog delay line, a first D flip-flop, a second D flip-flop, a third D flip-flop, and a fourth D flip-flop; the input end of the single analog delay line is connected with the delay signal of the reference clock signal, and adjacent delay signals of the single analog delay line input signal are output after passing through a delay unit; the data end of the first D trigger is connected with the delay signal of the reference clock signal, and the clock end is connected with the reference clock signal; the data end of the second D trigger is connected with the positive phase output end of the first D trigger, the clock end is connected with the reference clock signal, and the positive phase output end outputs a first phase comparison result; the data end of the third D trigger is connected with the output signal of the single analog delay line, and the clock end is connected with the reference clock signal; and the data end of the fourth D trigger is connected with the positive phase output end of the third D trigger, the clock end is connected with the reference clock signal, and the positive phase output end outputs a second phase comparison result.
Optionally, the digital main control module comprises an AND logic unit and a counting unit; the AND logic unit receives the inverse signals of the adjacent two-bit signals output by the digital phase discrimination module and performs AND operation; the counting unit is connected to the output end of the AND logic unit, receives one bit of adjacent two-bit signals output by the digital phase discrimination module, reduces the main delay control word when the phase difference is larger than one period, does not change the main delay control word when the phase difference is equal to one period, and increases the main delay control word when the phase difference is smaller than one period.
Optionally, the set proportion is a fixed value or an adjustable value.
More optionally, the digital slave control module includes a multiplication unit that receives the set delay control word and the control signal to implement a multiplication operation.
Optionally, the delay locked loop is adapted for secure digital input output cards.
To achieve the above and other related objects, the present invention provides a delay locking method, including at least:
delaying a reference clock signal, detecting the phase difference of the reference clock signal before and after the delay, and generating a main delay control word to adjust the delay time of the reference clock signal based on the detected phase comparison result until the reference clock signal is delayed by one period;
assigning a master delay control word corresponding to the delay of the reference clock signal by one period to a set delay control word, and multiplying the set delay control word by a set proportion to obtain a slave delay control word;
and adjusting the delay of the input clock signal with the same frequency as the reference clock signal based on the slave delay control word, so as to realize delay locking of the input clock signal.
Optionally, the master delay control word adjusts the delay time by controlling the number of analog delay cells selected.
Optionally, sampling a delayed signal of the reference clock signal with the reference clock signal; when the sampling signal is at a high level, the delay is more than half a period and less than one period; when the sampling signal is low, the delay is less than half a period.
More optionally, determining a delay time of the reference clock signal based on the phase comparison result of two adjacent bits; when the value of the comparison result of two adjacent bit phases is 10, the reference clock signal is delayed for one period, the loop is locked, and the current main delay control word is assigned to the set delay control word; when the value of the comparison result of two adjacent bit phases is 00, judging that the delay of the reference clock signal is larger than one period, reducing the value of the main delay control word, and unlocking a loop; when the value of the comparison result of two adjacent bit phases is 11, judging that the delay of the reference clock signal is smaller than one period, increasing the value of the main delay control word, and locking a loop; and when the value of the comparison result of the two adjacent bit phases is 01, judging that the reference clock signal is delayed to be half period, increasing the value of the main delay control word, and unlocking a loop.
Optionally, the set proportion is a fixed value or an adjustable value.
As described above, the delay locked loop and the delay locking method of the present invention have the following advantages:
the delay locking ring and the delay locking method adopt the digital phase discriminator and the digital controller, so that the reliability is higher, and the loop is more stable.
The delay locking ring and the delay locking method of the invention adopt an analog delay line, can realize the adjustment of delay, do not need to consider the common problems of setup time, hold time and the like in a digital circuit, and simplify the circuit debugging difficulty.
Drawings
Fig. 1 is a schematic diagram of a delay locked loop according to the present invention.
Fig. 2 is a schematic diagram of an analog main delay line according to the present invention.
Fig. 3 is a schematic diagram of the structure of the analog delay unit of the present invention.
Fig. 4 is a schematic structural diagram of a digital phase detection module according to the present invention.
Fig. 5 is a schematic diagram of a digital main control module according to the present invention.
Fig. 6 is a schematic diagram of a digital slave control module according to the present invention.
Description of element reference numerals
1. Delay locked loop
11. Analog main delay line
111. Analog delay unit
111a to 111c first to third stage analog delay units
12. Digital phase discrimination module
121-124 first-fourth D flip-flops
125. Single analog delay line
13. Digital main control module
131. Counting unit
14. Digital slave control module
141. Multiplication unit
15. Analog slave delay line
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1-6. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
As shown in fig. 1, the present embodiment provides a delay locked loop 1, the delay locked loop 1 including:
an analog master delay line 11, a digital phase discrimination module 12, a digital master control module 13, a digital slave control module 14 and an analog slave delay line 15.
As shown in fig. 1, the analog main delay line 11 is connected to the output terminal of the digital main control module 13, and receives a reference clock signal Refclk, and controls the delay of the reference clock signal Refclk based on a main delay control word MCODE output from the digital main control module 13.
Specifically, the analog main delay line 11 includes a plurality of analog delay units 111, where a first input terminal IN of each analog delay unit 111 is connected to a first output terminal PASS of a front stage, a second input terminal RET is connected to a second output terminal OUT of a rear stage, the first output terminal PASS outputs a delay signal of a first input terminal signal of the current stage analog delay unit 111, and the second output terminal OUT selects the first output terminal signal of the front stage or the second output terminal signal of the rear stage to output through the main delay control word MCODE; the control end S is connected with the main delay control word MCODE, wherein a first input end of a first-stage analog delay unit is used as an input end of the analog main delay line 11, and a second output end of the first-stage analog delay unit is used as an output end of the analog main delay line 11; the second input of the last stage analog delay unit is not useful and can be directly connected to a low level. As shown in fig. 2, only three analog delay units 111 are shown in the present embodiment, which are a first-stage analog delay unit 111a, a second-stage analog delay unit 111b, and a third-stage analog delay unit 111c, respectively. The first input terminal IN of the first stage analog delay unit 111a receives the reference clock signal Refclk, the second input terminal RET is connected to the second output terminal OUT of the second stage analog delay unit 111b, the first output terminal PASS is connected to the first input terminal IN of the second stage analog delay unit 111b, and the second output terminal OUT is used as an output terminal of the analog main delay line 11 to output a delay signal rfelk_delay of the reference clock signal; the first input terminal IN of the second-stage analog delay unit 111b is connected to the first output terminal PASS of the first-stage analog delay unit 111a, the second input terminal RET is connected to the second output terminal OUT of the third-stage analog delay unit 111c, the first output terminal PASS is connected to the first input terminal IN of the third-stage analog delay unit 111c, and the second output terminal OUT is connected to the second input terminal RET of the first-stage analog delay unit 111 a; the first input terminal IN of the third stage analog delay unit 111c is connected to the first output terminal PASS of the previous stage analog delay unit, the second input terminal RET is connected to the low level, the first output terminal PASS is suspended, and the second output terminal OUT is connected to the second input terminal RET of the previous stage analog delay unit.
More specifically, as shown in fig. 3, the analog Delay unit 111 includes a Delay and a data selector MUX; the input terminal of the Delay is taken as the first input terminal IN of the analog Delay unit 111, and the output terminal is taken as the first output terminal PASS of the analog Delay unit 111. A first input terminal of the data selector MUX is connected to an output terminal of the Delay unit Delay, a second input terminal is used as a second input terminal RET of the analog Delay unit 111, a control terminal S is connected to the main Delay control word MCODE, and an output terminal is used as a second output terminal OUT of the analog Delay unit 111, where out=pass when s=1; when s=0, out=ret.
Note that, the analog main delay line 11 may be any analog delay circuit that adjusts the delay time via the main delay control word MCODE, and is not limited to this embodiment. The number of analog delay units 111 in the analog main delay line 11 can be set according to the requirement, and is not limited to the present embodiment.
As shown in fig. 1, the digital phase discrimination module 12 is connected to the output end of the analog main delay line 11 and receives the reference clock signal Refclk, for discriminating the phase difference before and after the reference clock signal Refclk is delayed.
Specifically, as shown in fig. 3, in the present embodiment, the digital phase demodulation module 12 includes a single analog delay line 125, a first D flip-flop 121, a second D flip-flop 122, a third D flip-flop 123, and a fourth D flip-flop 124. The input end of the single analog delay line 125 is connected to the delay signal refclk_delay of the reference clock signal Refclk, the output end outputs the adjacent delay signal refclk_delay2 of the delay signal refclk_delay, and the control end (not shown) selects a single delay unit to operate, that is, the delay signal refclk_delay and the adjacent delay signal refclk_delay2 differ by a set delay unit, in this embodiment, the structure of the single analog delay line 125 is the same as that of the analog main delay line 11; the data terminal D of the first D flip-flop 121 is connected to the delay signal refclk_delay of the reference clock signal, and the clock terminal clk is connected to the reference clock signal Refclk; the data end D of the second D flip-flop 122 is connected to the positive phase output end Q of the first D flip-flop 121, the clock end clk is connected to the reference clock signal Refclk, and the positive phase output end Q outputs the first phase comparison result PDQ1; the data end D of the third D flip-flop 123 is connected to the adjacent delay signal refclk_delay2, and the clock end clk is connected to the reference clock signal Refclk; the data terminal D of the fourth D flip-flop 124 is connected to the positive phase output terminal Q of the third D flip-flop 123, the clock terminal clk is connected to the reference clock signal Refclk, and the positive phase output terminal Q outputs the second phase comparison result PDQ2. When the positive output signal Q1 of the first D flip-flop 121 (or the positive output signal Q2 of the third D flip-flop 123) is 1, the current delay exceeds a half period and is less than one period; when the positive output signal Q1 of the first D flip-flop 121 (or the positive output signal Q2 of the third D flip-flop 123) is 0, the current delay is less than half a period.
It should be noted that the digital phase discrimination module 12 may be implemented by any digital phase discrimination circuit or software code, which is not limited to this embodiment.
As shown in fig. 1, the digital main control module 13 is connected to the output end of the digital phase demodulation module 12, adjusts the main delay control word MCODE based on the phase difference before and after the reference clock signal Refclk is delayed, and assigns the main delay control word MCODE corresponding to the reference clock signal Refclk delayed by one period to the set delay control word PCODE.
Specifically, as shown in fig. 4, in the present embodiment, the digital main control module 13 includes an and logic unit and a counting unit 131. The and logic unit and receives the inverse signals of the two adjacent bit signals (the first phase comparison result PDQ1 and the second phase comparison result PDQ2, the second phase comparison result PDQ2 lags behind the first phase comparison result PDQ 1) output by the digital phase discrimination module 12, performs an and operation, and outputs an operation result DEC; in this embodiment, the and logic unit and is implemented by a two-input and gate, and the inverse signal is obtained by a first inverter not1 and a second inverter not 2. The counting unit 131 is connected to the output end of the and logic unit and receives one of the two adjacent signals output by the digital phase demodulation module 12, in this embodiment, the counting unit 131 receives a signal INC of the second phase comparison result PDQ2 after passing through the buffer; when the values of the first phase comparison result PDQ1 and the second phase comparison result PDQ2 are respectively 10, the reference clock signal Refclk is delayed for one period, the loop is in a locked state, the digital master control module 13 assigns the value of the current master delay control word MCODE to the set delay control word PCODE and outputs the set delay control word PCODE to the digital slave control module 14, and the locked state is also output to the digital slave control module 14; when the values of the first phase comparison result PDQ1 and the second phase comparison result PDQ2 are respectively 00, the reference clock signal Refclk is delayed for more than one period, the operation result DEC is a high level, the value of the main delay control word MCODE is reduced, and the loop is unlocked; when the values of the first phase comparison result PDQ1 and the second phase comparison result PDQ2 are respectively 11, the reference clock signal Refclk is delayed by more than half a period and less than one period, the signal INC is at a high level, the value of the main delay control word MCODE is increased, and the loop is unlocked; when the values of the first phase comparison result PDQ1 and the second phase comparison result PDQ2 are respectively 01, the reference clock signal Refclk is delayed by half a period, the signal INC is at a high level, the value of MCODE is increased, the value of the main delay control word MCODE is increased, and the loop is unlocked.
It should be noted that any circuit or software code capable of implementing the logic described above is suitable for the digital main control module 13 of the present invention, and is not limited to this embodiment.
As shown in fig. 1, the digital slave control module 14 is connected to the output end of the digital master control module 13, and receives a control signal Ctrl, and multiplies the set delay control word PCODE by a set proportion based on the control signal Ctrl, and then outputs the result as a slave delay control word SCODE.
Specifically, as shown in fig. 6, in the present embodiment, the digital slave control module 14 includes a multiplication unit 141, and the multiplication unit 141 receives the set delay control word PCODE and the control signal Ctrl, and performs multiplication operation on the set delay control word PCODE and the control signal Ctrl, so as to obtain the slave delay control word SCODE. The control signal Ctrl controls the set proportion, which is a fixed value or an adjustable value. In this embodiment, the control signal Ctrl is a two-bit bus signal, and when the control signal Ctrl is 00, the slave delay control word SCODE is 0, and the analog slave delay line 15 does not work; when the control signal Ctrl is 01, the slave delay control word SCODE controls the analog slave delay line 15 to delay 1/4 period; when the control signal Ctrl is 10, the slave delay control word SCODE controls the analog slave delay line 15 to delay 1/2 period; when the control signal Ctrl is 11, the slave delay control word SCODE controls the analog slave delay line 15 to delay 3/4 cycles.
It should be noted that any hardware circuit or software code that can extract the set delay control word PCODE in a certain proportion is suitable for the present invention, and is not limited to this embodiment. The number of bits of the control signal Ctrl can be set according to the requirement, the number of bits is about more, and the smaller the minimum adjustment proportion of the set proportion is.
As shown in fig. 1, the analog slave delay line 15 is connected to the output end of the digital slave control module 14, and receives an input clock signal clk having the same frequency as the reference clock signal Refclk, and controls the delay of the input clock signal clk based on the slave delay control word scede to obtain a delay signal Clkiout of the input clock signal.
Specifically, in the present embodiment, the structure of the analog slave delay line 15 is the same as the structure of the analog master delay line 11, and the number of stages of the input signal, the control signal and the analog delay unit are adaptively adjusted, which is not described herein.
The configuration of the analog slave delay line 15 may be different from that of the analog master delay line 11, and any analog delay circuit for adjusting the delay time by controlling the slave delay control word stream is applicable to the analog slave delay line 15 of the present invention, and is not limited to this embodiment.
It should be noted that the delay locked loop 1 of the present invention is suitable for a secure digital input/output card (SDIO, secure Digital Input and Output Card), and the output end is connected to the outside of the chip through IO to perform clock interaction with the SD card, so as to achieve alignment of the clock and the data. The delay locked loop 1 of the present invention is also suitable for other occasions where delay locking is required, and will not be described in detail here.
Example two
The present embodiment provides a delay locking method, in this embodiment, the delay locking method is implemented based on the delay locking ring 1 in the first embodiment, and in practical application, any structure capable of implementing the method is suitable for the method of the present invention, not limited to this embodiment. The delay locking method comprises the following steps:
1) And delaying the reference clock signal, detecting the phase difference of the reference clock signal before and after the delay, and generating a main delay control word based on the detected phase comparison result to adjust the delay time of the reference clock signal until the reference clock signal is delayed by one period.
Specifically, as shown in fig. 1, the reference clock signal Refclk is delayed based on the analog main delay line 11, and the main delay control word MCODE is set in an initial state.
Specifically, as shown in fig. 1, the phase difference between the reference clock signal Refclk and the delay signal refclk_delay of the reference clock signal is identified based on the digital phase identifying module 12, and phase comparison results PDQ1 and PDQ2 are obtained. In this embodiment, the reference clock signal Refclk is used to sample the delay signal refclk_delay of the reference clock signal; when the sampling signal is at a high level, the delay is more than half a period and less than one period; when the sampling signal is low, the delay is less than half a period.
Specifically, as shown in fig. 1, the main delay control word MCODE is adjusted based on the digital main control module 13 according to the phase comparison result PDQ. The analog main delay line 11, the digital phase demodulation module 12 and the digital main control module 13 form a phase locking loop. In this embodiment, the delay time of the reference clock signal is determined based on the phase comparison result of two adjacent bits; when the value of the comparison result of two adjacent bit phases is 10, the reference clock signal Refclk is delayed for one period, and the loop is locked; when the value of the comparison result of two adjacent bit phases is 00, judging that the delay of the reference clock signal Refclk is larger than one period, reducing the value of the main delay control word MCODE, and unlocking a loop; when the value of the comparison result of two adjacent bit phases is 11, judging that the delay of the reference clock signal Refclk is smaller than a period, increasing the value of the main delay control word MCODE, and locking a loop; when the value of the comparison result of two adjacent bit phases is 01, the reference clock signal Refclk is determined to be delayed to be half period, the value of the main delay control word MCODE is increased, and the loop is unlocked. And continuously adjusting the main delay control word MCODE, and adjusting delay time by controlling the number of the selected analog delay units so that the phases are different by one period and the loop is locked.
2) And assigning the master delay control word MCODE corresponding to the reference clock signal Refclk delayed by one period to the set delay control word PCODE, and multiplying the set delay control word PCODE by the set proportion to obtain the slave delay control word SCODE.
Specifically, the master delay control word MCODE corresponding to the loop locking is assigned to the set delay control word PCODE, where the set delay control word PCODE is the number of analog delay units corresponding to one period of delay.
Specifically, as shown in fig. 1, the relative delay is calculated in a set ratio from the control signal Ctrl based on the digital slave control module 14. The set proportion is a fixed value or an adjustable value. In this implementation, when the control signal Ctrl is 00, the slave delay control word SCODE is 0, and the analog slave delay line 15 does not operate; when the control signal Ctrl is 01, the slave delay control word SCODE controls the analog slave delay line 15 to delay 1/4 period; when the control signal Ctrl is 10, the slave delay control word SCODE controls the analog slave delay line 15 to delay 1/2 period; when the control signal Ctrl is 11, the slave delay control word SCODE controls the analog slave delay line 15 to delay 3/4 cycles.
3) And adjusting the delay of the input clock signal Clkin with the same frequency as the reference clock signal Refclk based on the slave delay control word PSCODE, so as to realize the delay locking of the input clock signal Clkin.
The delay locking ring and the delay locking method have the advantages of easy integration of a digital circuit and high reliability by combining the digital delay phase-locked ring and the analog delay line, and solve the problem that the time sequence of the digital delay line is difficult to adjust in different delay states.
In summary, the present invention provides a delay locked loop and a delay locked method, including: the system comprises an analog main delay line, a digital phase discrimination module, a digital main control module, a digital slave control module and an analog slave delay line; the analog main delay line is connected to the output end of the digital main control module, receives a reference clock signal, and controls the delay of the reference clock signal based on a main delay control word output by the digital main control module; the digital phase discrimination module is connected to the output end of the analog main delay line, and is used for receiving the reference clock signal and identifying the phase difference before and after the delay of the reference clock signal; the digital main control module is connected to the output end of the digital phase discrimination module, adjusts the main delay control word based on the phase difference before and after the delay of the reference clock signal, and assigns the main delay control word corresponding to the delay of the reference clock signal by one period to the set delay control word; the digital slave control module is connected to the output end of the digital master control module, receives a control signal, multiplies the set delay control word by a set proportion based on the control signal and then outputs the set delay control word as a slave delay control word; the analog slave delay line is connected to the output end of the digital slave control module, receives an input clock signal, and controls the delay of the input clock signal based on the slave delay control word. Delaying a reference clock signal, detecting the phase difference of the reference clock signal before and after the delay, and generating a main delay control word to adjust the delay time of the reference clock signal based on the detected phase comparison result until the reference clock signal is delayed by one period; assigning a master delay control word corresponding to the delay of the reference clock signal by one period to a set delay control word, and multiplying the set delay control word by a set proportion to obtain a slave delay control word; and adjusting the delay of the input clock signal based on the slave delay control word to realize delay locking of the input clock signal. The delay locking ring and the delay locking method adopt a digital phase discriminator and a digital controller, so that the reliability is higher, and the loop is more stable; the delay can be adjusted by adopting the analog delay line, and the common problems of setup time, hold time and the like in the digital circuit do not need to be considered, so that the circuit debugging difficulty is simplified. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (13)
1. A delay locked loop, the delay locked loop comprising at least:
the system comprises an analog main delay line, a digital phase discrimination module, a digital main control module, a digital slave control module and an analog slave delay line;
the analog main delay line is connected to the output end of the digital main control module, receives a reference clock signal, and controls the delay of the reference clock signal based on a main delay control word output by the digital main control module;
the digital phase discrimination module is connected to the output end of the analog main delay line, and is used for receiving the reference clock signal and identifying the phase difference before and after the delay of the reference clock signal;
the digital main control module is connected to the output end of the digital phase discrimination module, adjusts the main delay control word based on the phase difference before and after the delay of the reference clock signal, and assigns the main delay control word corresponding to the delay of the reference clock signal by one period to the set delay control word; wherein the digital main control module comprises an AND logic unit and a counting unit; the AND logic unit receives the inverse signals of the adjacent two-bit signals output by the digital phase discrimination module and performs AND operation; the counting unit is connected to the output end of the AND logic unit, receives one bit of adjacent two-bit signals output by the digital phase discrimination module, reduces the main delay control word when the phase difference is larger than one period, does not change the main delay control word when the phase difference is equal to one period, and increases the main delay control word when the phase difference is smaller than one period;
the digital slave control module is connected to the output end of the digital master control module, receives a control signal, multiplies the set delay control word by a set proportion based on the control signal and then outputs the set delay control word as a slave delay control word;
the analog slave delay line is connected to the output end of the digital slave control module, receives an input clock signal with the same frequency as the reference clock signal, and controls the delay of the input clock signal based on the slave delay control word.
2. The delay locked loop of claim 1, wherein: the analog main delay line comprises a plurality of analog delay units, wherein a first input end of each analog delay unit is connected with a first output end of a front stage, a second input end of each analog delay unit is connected with a second output end of a rear stage, the first output end outputs a delay signal of a first input end signal of the current stage analog delay unit, the second output end selects the first output end signal of the front stage or the second output end signal of the rear stage through the main delay control word to output, and a control end is connected with the main delay control word; the first input end of the first-stage analog delay unit is used as the input end of the analog main delay line, and the second output end of the first-stage analog delay unit is used as the output end of the analog main delay line; the second input end of the last stage analog delay unit is connected with a low level.
3. The delay locked loop of claim 2, wherein: the analog delay unit comprises a delay device and a data selector; the input end of the delayer is used as the first input end of the analog delay unit, and the output end of the delayer is used as the first output end of the analog delay unit; the first input end of the data selector is connected with the output end of the delayer, the second input end is used as the second input end of the analog delay unit, the control end is connected with the main delay control word, and the output end is used as the second output end of the analog delay unit, wherein the control end of the data selector outputs an output signal of the delayer when in high level.
4. A delay locked loop as claimed in any one of claims 1 to 3, wherein: the analog slave delay line has the same structure as the analog master delay line.
5. The delay locked loop of claim 1, wherein: the digital phase discrimination module comprises a single analog delay line, a first D trigger, a second D trigger, a third D trigger and a fourth D trigger; the input end of the single analog delay line is connected with the delay signal of the reference clock signal, and adjacent delay signals of the single analog delay line input signal are output after passing through a delay unit; the data end of the first D trigger is connected with the delay signal of the reference clock signal, and the clock end is connected with the reference clock signal; the data end of the second D trigger is connected with the positive phase output end of the first D trigger, the clock end is connected with the reference clock signal, and the positive phase output end outputs a first phase comparison result; the data end of the third D trigger is connected with the output signal of the single analog delay line, and the clock end is connected with the reference clock signal; and the data end of the fourth D trigger is connected with the positive phase output end of the third D trigger, the clock end is connected with the reference clock signal, and the positive phase output end outputs a second phase comparison result.
6. The delay locked loop of claim 1, wherein: the set proportion is a fixed value or an adjustable value.
7. The delay locked loop of claim 1 or 6, wherein: the digital slave control module comprises a multiplication unit, and the multiplication unit receives the set delay control word and the control signal to realize multiplication operation.
8. The delay locked loop of claim 1, wherein: the delay locked loop is suitable for secure digital input output cards.
9. A delay-locked method based on a delay-locked loop implementation as claimed in any of claims 1-8, characterized in that the delay-locked method comprises at least:
delaying a reference clock signal, detecting the phase difference of the reference clock signal before and after the delay, and generating a main delay control word to adjust the delay time of the reference clock signal based on the detected phase comparison result until the reference clock signal is delayed by one period;
assigning a master delay control word corresponding to the delay of the reference clock signal by one period to a set delay control word, and multiplying the set delay control word by a set proportion to obtain a slave delay control word;
and adjusting the delay of the input clock signal with the same frequency as the reference clock signal based on the slave delay control word, so as to realize delay locking of the input clock signal.
10. The delay lock method of claim 9, wherein: the master delay control word adjusts the delay time by controlling the number of analog delay cells selected.
11. The delay lock method of claim 9, wherein: sampling a delayed signal of the reference clock signal with the reference clock signal; when the sampling signal is at a high level, the delay is more than half a period and less than one period; when the sampling signal is low, the delay is less than half a period.
12. The delay lock method of claim 9 or 11, wherein: judging the delay time of the reference clock signal based on the phase comparison result of two adjacent bits; when the value of the comparison result of two adjacent bit phases is 10, the reference clock signal is delayed for one period, the loop is locked, and the current main delay control word is assigned to the set delay control word; when the value of the comparison result of two adjacent bit phases is 00, judging that the delay of the reference clock signal is larger than one period, reducing the value of the main delay control word, and unlocking a loop; when the value of the comparison result of two adjacent bit phases is 11, judging that the delay of the reference clock signal is smaller than one period, increasing the value of the main delay control word, and locking a loop; and when the value of the comparison result of the two adjacent bit phases is 01, judging that the reference clock signal is delayed to be half period, increasing the value of the main delay control word, and unlocking a loop.
13. The delay lock method of claim 9, wherein: the set proportion is a fixed value or an adjustable value.
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| CN114696822B (en) * | 2020-12-29 | 2024-06-07 | 宸芯科技股份有限公司 | Phase tuning device |
| CN116032252B (en) * | 2022-12-22 | 2024-02-02 | 新港海岸(北京)科技有限公司 | Digital-analog interface time sequence control circuit |
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