JP6631117B2 - Semiconductor device, demultiplexer, semiconductor circuit, data processing method and inspection method - Google Patents

Description

  The present invention relates to a semiconductor device, a demultiplexer, a semiconductor circuit, a data processing method, and an inspection method.

  FIG. 1 is a schematic diagram illustrating an example of a conventional demultiplexer 16. The demultiplexer 16 receives, for example, serial data from outside the semiconductor chip, converts the received serial data into parallel data, and transmits the parallel data to another circuit inside the semiconductor chip (for example, a serializer deserializer circuit; Used in serdes circuit).

  The demultiplexer 16 has two clocks (data clock 19a and boundary clock 19b) having the same frequency and different phases, serial input data 15a synchronized with the data clock 19a, and synchronization with the boundary clock 19b. Serial boundary data 15b is input. The boundary data 15b represents detection data of the boundary of the input data 15a (timing at which the logical value of the input data 15a transitions from 0 to 1 or from 1 to 0).

  The demultiplexer 16 synchronizes both serial data of the input data 15a and the boundary data 15b with a data clock obtained by dividing only one of the two clocks 19a, and parallelizes the two serial data. Output. The demultiplexer 16 outputs a frequency-divided data clock 17c (divided-by-8 data clock in FIG. 1) used for synchronization, and all data parallelized at the same timing (parallel data 17a and parallel boundary data 17b). Is output.

  The demultiplexer 16 includes a frequency divider group 1000 in which a plurality of frequency dividers are connected in series, a first flip-flop group 1001 in which a plurality of flip-flops are connected in series, and a plurality of flip-flops connected in series. And a second flip-flop group 1002. The frequency divider group 1000 divides the frequency of the data clock 19a and outputs a frequency-divided data clock 17c. The first flip-flop group 1001 converts serial input data 15a into parallel data 17a and outputs the parallel data 17a. The second flip-flop group 1002 converts the serial boundary data 15b into the parallel boundary data 17b and outputs it.

  Note that Div represents a frequency divider, FF represents a flip-flop, f represents a frequency [Hz], and × 1, × 2, × 4, and × 8 represent the number of parallel FFs.

  FIG. 2 is a detailed diagram illustrating an example of the internal configuration of each flip-flop (FF). One FF 50 has five latches (two latches T and three latches I), synchronizes serial input data (I_Data) with a differential input clock (I_Clock / x), and parallel data 0_Data [1: 0]. ]. Each latch T has a series circuit of an inverter 51, a transfer gate 52, and a latch circuit 53. Each latch I has a series circuit of a transfer gate 52 and a latch circuit 53. The transfer gate 52 and the latch circuit 53 operate with the input clock clk and the inverted clock clkx having the opposite phase to the input clock clk.

  FIG. 3 is a detailed diagram illustrating an example of the internal configuration of each frequency divider (Div). One frequency divider 60 has inverters 61 and 62 and a series circuit of two differential latches 63 and 72. The differential latch 63 has inverters 64-67 and transfer gates 68-71, and the differential latch 72 has inverters 73-76 and transfer gates 77-80. When one of the nodes B and C goes high, the other goes low. The frequency divider 60 divides the frequency of the input clock clka of the frequency f by two and the inverted clock clkax of the opposite phase by two, and the four quadrature clocks (clkq, clkqx, clki, clki, clix).

  Note that, for example, Patent Documents 1 and 2 disclose techniques relating to data clock synchronization.

JP-A-5-260029 JP-A-7-143109

  In the prior art of FIG. 1, the input data 15a synchronized with the data clock 19a and the boundary data 15b synchronized with the boundary clock 19b having a phase different from that of the data clock 19a are obtained by dividing the frequency of the common data clock 19a. And to be parallelized. However, in such a configuration in which synchronization is performed using a common data clock, if the phase difference between the data clock 19a and the boundary clock 19b becomes too large, the timing for synchronizing the data with the clock is shifted, and the parallel data 17a and the data are not synchronized. The output data order may be shifted between the parallel boundary data 17b.

  For example, if the phase difference between the data clock 19a and the boundary clock 19b becomes too large, the setup or hold timing to be satisfied may not be satisfied in the FF 1003 that synchronizes the boundary data 15b with the clock divided by two. In particular, as the operating frequency f increases, an FF having a smaller frequency division ratio (that is, an FF to which serial data is input) has an operation margin (a period during which the FF should be latched) with respect to FF setup or hold timing. Is reduced, so that the data synchronization timing does not fall within the operation margin. As a result, the synchronization timing may be shifted by one cycle, and the output data order of the parallel boundary data 17b may be shifted.

  In view of the above, it is an object of the present invention to prevent the output data sequence from being out of order when a serial data group synchronized with a different phase clock is synchronized with a single phase clock and parallelized.

In one proposal,
A first frequency divider for dividing the data clock and outputting a first frequency-divided data clock;
A second frequency divider circuit for dividing a boundary clock having the same frequency as the data clock but having a different phase and outputting a divided boundary clock;
A third frequency divider for dividing the first frequency-divided data clock and outputting a second frequency-divided data clock;
A first latch circuit that synchronizes serial input data synchronized with the data clock with the first frequency-divided data clock and converts the data into first parallel data;
A second latch circuit that synchronizes the first parallel data with the second frequency-divided data clock and converts the data into second parallel data;
A third latch circuit that synchronizes the serial boundary data synchronized by the boundary clock with the divided boundary clock to convert the data into first parallel boundary data;
A fourth latch circuit that synchronizes the first parallel boundary data with the second frequency-divided data clock and converts the data into second parallel boundary data;
A synchronization circuit for synchronizing the first divided data clock and the divided boundary clock;
A semiconductor device is provided that includes a processing unit that processes the second parallel data, the second parallel boundary data, and the second frequency-divided data clock.

  According to one aspect, the data order between the parallelized data can be prevented from shifting.

It is the schematic which shows an example of the conventional demultiplexer. FIG. 3 is a detailed diagram showing an example of the internal configuration of each flip-flop (FF). FIG. 3 is a detailed diagram illustrating an example of an internal configuration of each frequency divider (Div). FIG. 3 is a diagram illustrating an example of a transmission / reception configuration between a first semiconductor chip and a second semiconductor chip. FIG. 4 is an explanatory diagram illustrating an example of a clock phase adjustment function of a CDR unit. An example is shown in which the optimum timing of the edge of the data clock is delayed from the ideal timing in design due to rounding of the waveform and the edge of the boundary clock is located at the ideal logical transition timing. An example is shown in which the optimum timing of the edge of the data clock is ahead of the ideal timing in design due to rounding of the waveform and the edge of the boundary clock is located at the ideal logical transition timing. FIG. 3 is a diagram illustrating an example of a configuration of a semiconductor device including a demultiplexer. FIG. 3 is a detailed diagram illustrating an example of an internal configuration of a phase detection circuit. FIG. 3 is a diagram illustrating an example of a first-stage data input latch in a phase detection circuit. FIG. 7 is a diagram illustrating an example of an operation waveform of a latch during setup violation. 7 is an example of an operation waveform of a phase detector during setup violation. FIG. 9 shows an example of a waveform at each node when a soft error occurs in a latch circuit in a second frequency divider that divides a boundary clock. FIG. 9 is a diagram illustrating another example of the internal configuration of the phase detection circuit. 9 is a flowchart illustrating an example of a data processing method. FIG. 3 is a diagram illustrating an example of a configuration for setting an ECS. FIG. 4 is a diagram illustrating an example of ECS settings. FIG. 4 is a diagram illustrating an example of ECS settings. FIG. 9 is a diagram illustrating another example of a configuration for setting an ECS. It is a flowchart which shows an example of an inspection method. 9 is a flowchart illustrating an example of a search method for searching for an optimal ECS and a phase difference. FIG. 6 is a diagram for explaining an example of a relationship between variables.

  FIG. 4 is a diagram illustrating an example of a transmission / reception configuration between the first semiconductor chip 1 and the second semiconductor chip 2. The multiplexer 4 serializes the parallel data 3 from inside the first semiconductor chip 1. The driver 6 amplifies the signal of the serial data 5 serialized by the multiplexer 4 and transmits a signal amplification waveform 7 of the serial data 5 to the second semiconductor chip 2 via the back plane 8 (an example of a circuit board). . The signal amplification waveform 7 of the serial data 5 is attenuated by the back plane 8.

  The pre-filter amplifier 10 of the second semiconductor chip 2 supplies the signal amplification waveform 11 of the serial data 9 to the comparator 12 by shaping and amplifying the attenuation signal waveform 9. The comparator 12 makes a logical decision (0, 1 decision) of the signal amplification waveform 11 in accordance with a clock 19 supplied from a CDR (Clock and Data Recovery) section 18, and the latch 14 makes a digital reception data 13 which is the decision result. Are synchronized in accordance with a clock 19 to output serial data 15. The clock 19 includes a data clock 19c having the same frequency but different phases and a boundary clock 19d.

  The demultiplexer 102 parallelizes the serial data 15 synchronized by the latch 14 with the clock 19 and transmits the parallel data 17 to the inside of the second semiconductor chip 2. The serial data 15 includes serial input data 15c synchronized with the data clock 19c and serial boundary data 15d synchronized with the boundary clock 19d. The boundary data 15d represents detection data of the boundary of the input data 15c (timing at which the logical value of the input data 15c transitions from 0 to 1 or from 1 to 0). The parallel data 17 includes parallel data 17d obtained by parallelizing the input data 15c, parallel boundary data 17e obtained by parallelizing the boundary data 15d, and a divided data clock 17f obtained by dividing the data clock 19c. It is.

  Since the received data 11 (signal amplified waveform of the serial data 9) does not include a clock, the CDR unit 18 reproduces a clock from the received data 11. In high-speed data transmission between transmission / reception circuits used for USB (Universal Serial Bus) and SATA (Serial Advanced Technology Attachment), a reception circuit uses a clock used for logical determination (0, 1 determination) of received data. Restore from received data. In order to correctly determine the logic of the received data, the phase of the clock restored by the receiving circuit is adjusted by a feedback circuit inside the receiving circuit so that the phase difference from the received data becomes constant. As described above, the receiving circuit reproduces the clock for logical determination of the received data, and performs the logical determination of the received data using the reproduced clock to reproduce the transmission data. : Clock and Data Recovery).

  FIG. 5 is an explanatory diagram illustrating an example of a phase adjustment function of the clock 19 of the CDR unit 18. The data clock 19c is for fetching 1 or 0 of the received data 11, and the boundary clock 19d is for fetching the boundary of the received data 11 (boundary timing when the logical value transitions from 1 to 0 or 0 to 1). . The data clock 19c is adjusted by the CDR unit 18 so that a rising or falling edge exists at a timing when the waveform amplitude of the reception data 11 is large so that the logical value of the reception data 11 is accurately fetched. On the other hand, the boundary clock 19d is adjusted by the CDR unit 18 so that a rising or falling edge exists near the boundary of the reception data 11 so that the boundary of the reception data 11 is correctly fetched.

  The CDR unit 18 determines whether the rising or falling edge of the boundary clock 19d is delayed or advanced with respect to the logical transition timing Tm in accordance with the contents of the parallel data 17d and the parallel boundary data 17e. The phase of the clock 19d is automatically adjusted. Tl indicates the timing at which the rising or falling edge of the boundary clock 19d is ahead of the logical transition timing Tm, and Tf is the rising or falling edge of the boundary clock 19d is later than the logical transition timing Tm. Shows timing.

  FIG. 6 shows an example in which the optimal timing of the edge of the data clock is later than the ideal timing in design due to the rounding of the waveform and the edge of the boundary clock is located at the ideal logical transition timing. Specifically, FIG. 6 shows that the actually desired timing Ti of the rising or falling edge of the data clock 19c is later than the ideal timing Tl due to the rounding of the waveform, and the timing of the rising or falling edge of the boundary clock 19d. Is located at an ideal logical transition timing Tm. FIG. 7 shows an example in which the optimal timing of the edge of the data clock is ahead of the ideal timing in design due to the rounding of the waveform and the edge of the boundary clock is located at the ideal logical transition timing. Specifically, FIG. 7 shows that the actually desired timing Ti of the rising or falling edge of the data clock 19c is ahead of the ideal timing Tf due to waveform rounding or the like, and the timing of the rising or falling edge of the boundary clock 19d. Is located at an ideal logical transition timing Tm.

  The actually desirable timing Ti of the edge of the data clock 19c is not always the median value (ideal timing) between adjacent logical transition timings Tm as shown in FIGS. . In addition, the CDR unit 18 automatically adjusts the phase of the boundary clock 19d according to the set value set in the CDR unit 18 so that the rising or falling edge of the boundary clock 19d moves to an ideal timing.

  The CDR unit 18 automatically adjusts the phase between the boundary clock 19d and the data clock 19c, for example, during an initial sequence when the power supply of the transmission / reception circuit rises. Alternatively, the CDR unit 18 may fix the phase between the boundary clock 19d and the data clock 19c to, for example, a setting value obtained before shipment in an inspection process or the like.

  Therefore, the CDR unit 18 can determine the phase of the data clock 19c based on the boundary clock 19d, and the comparator 12 provides a function that can always fetch the reception data 11 at a practically desirable timing. As described above, there is a phase difference between the data clock 19c and the boundary clock 19d, and the optimum value of the phase difference at which the received data 11 can be accurately fetched differs between individual semiconductor chips due to manufacturing variations of the semiconductor chips. It becomes.

  FIG. 8 is a diagram illustrating an example of a configuration of a semiconductor device 101 including the demultiplexer 102. The semiconductor device 101 includes, for example, a demultiplexer 102 and a processing unit 103. The processing unit 103 processes the parallel output data 17 (17d, 17f, 17e) output from the demultiplexer 102 according to a predetermined processing procedure. For example, the semiconductor device 101 is a CPU (Central Processing Unit), and the processing unit 103 is an arithmetic core unit of the CPU, a memory, and a serdes internal circuit. The semiconductor device 101 may be, for example, a device including a CPU or an information processing device such as a server incorporating the device.

  The demultiplexer 102 includes a first frequency divider 91, a second frequency divider 92, a third frequency divider 34, a first latch circuit 25, a second latch circuit 26, and a third , A fourth latch circuit 45, and a synchronization circuit 100. The demultiplexer 102 is, for example, a circuit formed on a semiconductor chip.

  The first frequency dividing circuit 91 outputs the first frequency-divided data clock 35 by dividing the frequency of the data clock 19c by two, for example. The data clock 19c may be a single clock or a pair of clocks (differential clocks) obtained by combining a clock and an inverted clock having the opposite phase. FIG. 8 shows a case where the data clock 19c is a differential clock.

  The second frequency dividing circuit 92 divides the frequency of the boundary clock 19d having the same frequency as that of the data clock 19c and having a different phase by two, and outputs a frequency-divided boundary clock 19e. The boundary clock 19d may be a single clock or a pair of clocks (differential clocks) obtained by combining a clock and an inverted clock having the opposite phase. FIG. 8 shows a case where the boundary clock 19d is a differential clock.

  The third frequency dividing circuit 34 divides the first frequency-divided data clock 35 and outputs a second frequency-divided data clock 17f. The third frequency divider 34 has, for example, a frequency divider 32 and a frequency divider 33. The divider 32 outputs a divided data clock obtained by dividing the first divided data clock 35 by two. The frequency divider 33 divides the frequency-divided data clock output from the frequency divider 32 by two and outputs a second frequency-divided data clock 17f.

  The first latch circuit 25 synchronizes the serial input data 15c synchronized with the data clock 19c with the first frequency-divided data clock 35, converts the input data 15c into first parallel data 27, and outputs the first parallel data 27. The first latch circuit 25 has, for example, an FF 21 and an FF 22. The FF 21 outputs two columns of parallel data obtained by synchronizing the serial input data 15c with the data clock 19c. The FF 22 outputs four columns of first parallel data 27 in which two columns of parallel data output from the FF 21 are synchronized by a first frequency-divided data clock 35.

  The second latch circuit 26 synchronizes the first parallel data 27 with the second divided data clock 17f, converts the first parallel data 27 into second parallel data 17d, and outputs the second parallel data 17d. The second latch circuit 26 includes, for example, an FF 23 and an FF 24. The FF 23 outputs eight columns of parallel data obtained by synchronizing the four columns of the first parallel data 27 with the divided clock output from the frequency divider 32. The FF 24 outputs 16 columns of second parallel data 17d obtained by synchronizing the eight columns of parallel data output from the FF 23 with the second frequency-divided data clock 17f.

  The third latch circuit 93 synchronizes the serial boundary data 15d synchronized by the boundary clock 19d with the frequency-divided boundary clock 19e, converts the data into first parallel boundary data 47, and outputs the first parallel boundary data 47.

  The fourth latch circuit 45 synchronizes the first parallel boundary data 47 with the second frequency-divided data clock 17f, converts the data into second parallel boundary data 17e, and outputs the second parallel boundary data 17e. The fourth latch circuit 45 has, for example, an FF 43 and an FF 44. The FF 43 outputs eight columns of parallel data obtained by synchronizing the four columns of the first parallel boundary data 47 with the frequency-divided clock output from the frequency divider 32. The FF 44 converts the eight columns of parallel data output from the FF 43 into 16 columns of second parallel boundary data 17e synchronized by the second frequency-divided data clock 17f, and outputs the converted data.

  The synchronization circuit 100 synchronizes the first divided data clock 35 with the divided boundary clock 19e. As in the present embodiment, not only the first frequency divider 91 for dividing the data clock 19c but also the second frequency divider 92 for dividing the boundary clock 19d are provided. The frequency dividing operations of the first frequency dividing circuit 91 and the second frequency dividing circuit 92 can be synchronized with each other. Therefore, between the parallel data 17d and the parallel boundary data 17e, the data order is prevented from shifting due to the fact that the frequency division operations of the first frequency divider 91 and the second frequency divider 92 are not synchronized. can do.

  In this embodiment, the second frequency divider 92 is provided in addition to the first frequency divider 91, so that the boundary data 15d is synchronized with the frequency-divided clock of the data clock 19c. It can be implemented in a latch circuit unit having a relatively low f. That is, the present invention can be implemented by a latch circuit unit (specifically, the FF 43) that parallelizes from four columns to eight columns, rather than a latch circuit unit that parallelizes from two columns to four columns. Therefore, the restriction on the operation timing of the FF can be relaxed. Further, a circuit (a circuit having the same form as the circuit 90) having a frequency divider for further dividing the frequency-divided clock of the boundary clock 19d by two and a circuit for synchronizing the frequency divider with the frequency divider 32 is provided. By further providing, the restriction on the operation timing of the FF can be further relaxed. That is, the synchronization of the boundary data 15d with the frequency-divided clock of the data clock 19c can be performed by the latch circuit unit (specifically, the FF 44) that parallelizes the data from 8 columns to 16 columns.

  The second frequency dividing circuit 92 outputs, for example, a plurality of frequency dividing boundary clocks 19e having different phases. In the present embodiment, the second frequency dividing circuit 92 outputs the frequency-divided boundary clock 19e having four quadrature phases different in phase by 90 °, and has, for example, the configuration shown in FIG. In the present embodiment, the synchronization circuit 100 includes, for example, a phase detection circuit 94 and a multiplexer (MUX) 95.

  The phase detecting circuit 94 includes four phase detectors for comparing the phase of one differential signal in the first frequency-divided data clock 35 with the frequency-divided boundary clock 19e having four quadrature phases. It is. The multiplexer 95 is a selection circuit that selects one from the four phase detectors.

  FIG. 9 is a diagram illustrating an example of the internal configuration of the phase detection circuit 94. The phase detection circuit 94 has four phase detectors 94a to 94d, and each of the phase detectors 94a to 94d has four latches 110 to 113 connected in series and one inverter 114. The phase detector 94a compares the phase of the first frequency-divided data clock 35 (0 °) with the frequency-divided boundary clock 19e (0 °) having a phase of 0 °. The phase detector 94b converts the phase of the first frequency-divided data clock 35 (0 °) and the frequency-divided boundary clock 19e (90 °) whose phase is shifted by 90 ° with respect to the frequency-divided boundary clock 19e (0 °). Compare. The phase detector 94c converts the phase of the first frequency-divided data clock 35 (0 °) and the frequency-divided boundary clock 19e (180 °) whose phase is shifted by 180 ° with respect to the frequency-divided boundary clock 19e (0 °). Compare. The phase detector 94d converts the phase of the first frequency-divided data clock 35 (0 °) and the frequency-divided boundary clock 19e (270 °) whose phase is shifted by 270 ° with respect to the frequency-divided boundary clock 19e (0 °). Compare. The division boundary clocks 19e (0 °), 19e (90 °), 19e (180 °), and 19e (270 °) are examples of a plurality of division boundary clocks having different phases. In FIG. 9, all clocks and data input to the phase detection circuit 94 are actually differential signals, but are represented by single-ended signals for simplicity.

  In each of the phase detectors 94a to 94d, the frequency-divided boundary clock 19e is an input clock input to the four latches 110 to 113 via the inverter 114, and one differential clock in the first frequency-divided data clock 35. The signal is input data input to the latch 110.

  Each of the phase detectors 94a to 94d receives the frequency-divided boundary clock 19e and one differential signal in the first frequency-divided data clock 35. The fixed signal fx output from each of the phase detectors 94a to 94d depends on whether or not the rising edge of the frequency-divided boundary clock 19e is within the high-level margin period of the first frequency-divided data clock 35 (0 °). Are different at 0/1.

  Among the phase detectors 94a to 94d, the phase detector whose rising edge of the frequency-divided boundary clock 19e is outside the high-level margin period of the first frequency-divided data clock 35 (0 °) is set to the low level (logical level). 0), it is assumed that the rising edge of the frequency-divided boundary clock 19e is within the high-level margin period of the first frequency-divided data clock 35 (0 °). A (logic 1) fixed signal fx is output. Alternatively, among the phase detectors 94a to 94d, the phase detector whose rising edge of the frequency-divided boundary clock 19e is outside the high-level margin period of the first frequency-divided data clock 35 (0 °) is at a high level. Assuming that the fixed signal fx of (logic 1) is output, the phase detector in which the rising edge of the frequency-divided boundary clock 19e is within the high-level margin period of the first frequency-divided data clock 35 (0 °) The low-level (logic 0) fixed signal fx is output.

  The phase detection circuit 94 generates the first divided data clock 35 based on the result of comparing the phase of one differential signal in the first divided data clock 35 with the four quadrature-phase divided boundary clocks 19e. It is determined whether or not the dividing operation is phase-synchronized between the first dividing circuit 91 that outputs the signal and the second dividing circuit 92 that outputs the dividing boundary clock 19e. The fixed signal fx output from each of the phase detectors 94a to 94d determines whether or not the frequency division operation between the first frequency dividing circuit 91 and the second frequency dividing circuit 92 is phase-synchronized. Represent.

  The multiplexer 95 selects one phase detector from the four phase detectors 94a to 94d according to the external control signal 48. That is, the multiplexer 95 selects and outputs one fixed signal fx from the four fixed signals fx based on the set value of the external control signal 48. The external control signal 48 is a signal set in advance so that the data order is not shifted between the parallel data 17d and the parallel boundary data 17e. For example, the demultiplexer 102 includes an external register 104 (see FIG. 8) that stores a set value of the external control signal 48. The external register 104 is an example of a memory.

  In FIG. 8, the second frequency divider 92 outputs a first frequency-divided boundary clock 19e having four quadrature phases different from each other. Then, the third latch circuit 93 includes an FF 41, an FF 97, an FF 98, and a second multiplexer 99. The FF 97 synchronizes with a first differential clock 97a, which is a set of two clocks having phases different from each other by 180 ° among four quadrature-phase first frequency-divided boundary clocks 19e having different phases from each other. Is an example of the flip-flop of FIG. The FF 98 synchronizes with the second differential clock 98a (that is, a differential clock obtained by inverting the first differential clock 97a) by 180 ° with respect to the phase of the first differential clock 97a. It is an example of a second flip-flop. The second multiplexer 99 selects one of the output of the FF 97 and the output of the FF 98 according to the fixed signal 96 output from the multiplexer 95. The fixed signal 96 corresponds to the above-described fixed signal fx selected by the multiplexer 95. This makes it possible to select one of the FFs 97 and 98 that avoids a data order shift between the parallel data 17d and the parallel boundary data 17e.

  The FF 97 synchronizes, for example, the parallel data 15e in which the boundary data 15d is parallelized in two columns by the FF 41 in accordance with the boundary clock 19d by the first differential clock 97a to generate four columns of parallel data of the boundary data 15d. I do. On the other hand, the FF 98 synchronizes, for example, the parallel data 15e in which the boundary data 15d is parallelized in two columns by the FF 41 in accordance with the boundary clock 19d with the second differential clock 98a, and outputs the parallel data of four columns of the boundary data 15d. Generate

  FIG. 10 is a diagram illustrating an example of the first-stage data input latch 110 in each of the phase detectors 94a to 94d. The latch 110 is a differential D-type latch that operates with an input clock clk and an inverted clock clkx having the opposite phase. The latch 110 has inverters 121 to 126 and transfer gates 127 to 129. The latch 110 can output the same data X as the input data A by including the inverters 121, 122, and 124 to 126 and the transfer gates 127 and 128. The inverted input data AX is input data having a phase opposite to that of the input data A. The transfer gate 129 is for equalizing the loads of the input data A and the inverted input data AX.

  By changing the configuration of the latch 110 from, for example, the configuration in FIG. 2 to the configuration in FIG. 10, it is possible to ease the limitation on the operation margin for the setup or hold timing of the latches 110 to 113.

  FIG. 11 is a diagram illustrating an example of operation waveforms of the latch 110 during setup violation when the configuration of the latch 110 is the configuration illustrated in FIG. Due to the setup violation, even if the amplitudes of the nodes N1 and N2 inside the latch 110 are not the maximum amplitude (one is the power supply voltage and the other is the ground voltage), the data X and the outputs of the latches 111 to 113 subsequent to the latch 110 1/0 logic can be determined.

  FIG. 12 is an example of operation waveforms of the phase detector 94a during setup violation when the configuration of the latch 110 is the configuration of FIG. 10 and the configuration of the latches 111 to 113 is the configuration of the latch I of FIG. . The 1/0 logic undetermined state inside the first stage latch 110 due to the setup violation is filtered by the four stages of latches 110 to 113, and the correct fixed signal fx (the fixed signal fx of the low level Lo in the example of FIG. 12) is output. Can output. The same applies to the other phase detectors 94b to 94d. In FIG. 12, Lo indicates a low level, and Hi indicates a high level.

  Therefore, in each of the phase detectors 94a to 94d, the limitation of the operation margin with respect to the setup or hold timing of the latches 110 to 113 can be relaxed.

  With only one phase detector, it is difficult to perform an appropriate phase comparison when the phase difference between the data clock 19c and the boundary clock 19d is relatively large. However, providing a plurality of phase detectors makes it easy to perform an appropriate phase comparison even when the phase difference between the data clock 19c and the boundary clock 19d is relatively large.

  In the four phase detectors 94a to 94d, four quadrature-phase frequency-divided boundary clocks 19e are used as clock inputs. Since there is a large overlap between the four quadrature phase dividing boundary clocks 19e, the normal operation ranges of the four phase detectors 94a to 94d also overlap. Therefore, it is possible to avoid that the phase comparison cannot be performed by all of the phase detectors 94a to 94d and that the phase detectors 94a to 94d operate outside the normal operation range.

  Further, each frequency dividing circuit may have a latch configuration in which a soft error is not dealt with. In this case, the logical value of the internal node of the frequency divider may be inverted due to a soft error. Thus, the phase synchronization relationship between the first frequency dividing circuit 91 and the second frequency dividing circuit 92 changes during operation. Even if such an event occurs, the output value of the phase detection circuit 94 also changes. As a result, the FF selected from the FFs 97 and 98 is switched, so that the change is canceled in the semiconductor circuit 90. In this canceling process, only the delay of the circuit included in the circuit 90 causes a latency until resynchronization, so that the latency until resynchronization is sufficiently small, and real-time synchronization can be realized.

  FIG. 13 shows an example of the waveform of each node when a soft error occurs in the latch circuit in the second frequency divider 92 that divides the boundary clock 19d to generate the frequency-divided boundary clock 19e. The dividing boundary clock 19e shown in FIG. 13 is an example of one of the four quadrature-phase dividing boundary clocks 19e. When the internal node of the latch circuit in the second frequency dividing circuit 92 is inverted due to a soft error, the frequency dividing boundary clock 19e is shifted by a half cycle. However, since the fixed signal 96 output from the multiplexer 95 is also inverted by the inversion of the fixed signal fx output from the phase detection circuit 94, the output FF switches between the FFs 97 and 98, and the change due to the soft error is canceled. You.

  Therefore, when the first frequency dividing circuit 91 and the second frequency dividing circuit 92 cannot be synchronized with each other, an event such as initialization or interruption of the latch circuit due to a reset signal of the latch circuit does not occur. In addition, it is possible to realize a situation where normal operation is always performed. In addition, it is possible to realize a situation in which the circuit always operates normally without complicated settings before and after the power supply of the circuit is cut off.

  FIG. 14 is a diagram illustrating another example of the internal configuration of the phase detection circuit 94. The basic function of the configuration in FIG. 14 is the same as the configuration in FIG. 9, and the configuration in FIG. 14 has four phase detectors 94e to 94h. In at least one of the four phase detectors 94e to 94h, the transmission delay time of the clock or data input signal is set to the clock path 117 or the data path 118 to the four latches 110 to 113 in the configuration of FIG. A buffer is provided for this purpose. FIG. 14 illustrates the buffers 115a to 115g. As a result, the portion where the normal operation ranges of the four phase detectors 94e to 94d overlap each other can be increased, and the reduction of the overlap of the normal operation range due to internal variations can be canceled.

  At least one of the four phase detectors 94e to 94h has a clock gating circuit 116 that can cut off the frequency-divided boundary clock 19e input to the latches 110 to 113. The clock gating circuit 116 selects whether to block the frequency-divided boundary clock 19e according to the set value of the clock gate signal ipd * (* is 0 to 3 in the example shown in FIG. 14). The clock gating circuit 116 inputs the unselected divided boundary clock 19e by cutting off the unselected divided boundary clock 19e among the four divided boundary clocks 19e according to the setting value of the external control signal 48. The power consumed by the detected phase detector can be reduced. The set value of the clock gate signal ipd * is determined in advance, for example, similarly to the set value of the external control signal 48, as described later.

  FIG. 15 is a flowchart illustrating an example of the data processing method. Each step of FIG. 15 will be described below with reference to FIG.

  The first frequency dividing circuit 91 divides the frequency of the data clock 19c and outputs the first frequency-divided data clock 35 (first frequency dividing step S10). The second frequency dividing circuit 92 divides the frequency of the boundary clock 19d having the same frequency as that of the data clock 19c and having a different phase, and outputs four divided boundary clocks having different phases (19e (0 °) and 19e (90 °)). ), 19e (180 °) and 19e (270 °)) (second frequency dividing step S20). The phase detection circuit 94 of the synchronization circuit 100 compares the phase of one differential signal in the first frequency-divided data clock 35 with the frequency-divided boundary clock 19e having four quadrature phases (phase comparison step S30). The second multiplexer 99 determines whether to synchronize the boundary data 15e synchronized by the boundary clock 19d with the first differential clock 97a or the second differential clock 98a. The selection is made according to the comparison result in S30 (selection step S40).

  According to such a data processing method, even if the frequency dividing operation in the first frequency dividing step S10 and the frequency dividing operation in the second frequency dividing step S20 become asynchronous, a synchronous method in which the data order is not shifted. Can be selected in the selection step S40.

  Which of the four phase detectors 94a to 94d the multiplexer 95 selects is determined by the set value of the external control signal 48 (ECS (External Control Signal) set value) stored in the external register 104 in advance. The ECS setting value is set according to the value of the phase difference between the data clock 19c and the boundary clock 19d. However, it is difficult to quantitatively determine the current value of the phase difference from outside the chip. Therefore, the following method of determining and using the ECS setting value is provided.

  FIG. 16 is a diagram illustrating an example of a configuration for setting an ECS, and specifically, a diagram illustrating an example of a test configuration for determining an ECS set value. FIG. 16 shows a serdes circuit 130 and an inspection device 105 for inspecting the serdes circuit 130. The serdes circuit 130 is an example of a transmission / reception circuit including a transmission circuit 131 that transmits serial data, and a reception circuit 132 that receives the serial data transmitted from the transmission circuit 131. In FIG. 16, when the serdes circuit 130 is a circuit on a semiconductor chip, the measuring device 162 of the inspection device 105 is a device installed outside the semiconductor chip.

  16, the same components as those in FIG. 4 are denoted by the same reference numerals as those in FIG. The sampler 142 of the receiving circuit 132 is a circuit including the pre-filter amplifier 10, the comparator 12, and the latch 14 in FIG.

  The processing unit 103 of the reception circuit 132 includes, for example, a register 143, a reception-side selection circuit 144, and a reception processing circuit 145. The register 143 temporarily stores the output data 17 of the demultiplexer 102 (for example, the second parallel data 17d). The reception-side selection circuit 144 selects whether to output the output data 17 of the demultiplexer 102 to the reception processing circuit 145 or the measurement device 162 according to the selection signal 140. The reception processing circuit 145 is an example of a circuit that processes data stored in the register 143 by a predetermined processing method.

  The inspection device 105 includes a waveform generation device 161 that can generate a test waveform of serial data, and a measurement device 162 that measures the bit error rate (BER) of the second parallel data 17d of the demultiplexer 102.

  The transmission circuit 131 includes a transmission-side selection circuit 141. The transmission-side selection circuit 141 selects one of serial data from outside the transmission circuit 131 and test serial data from the waveform generation device 161 according to the selection signal 140.

  In order to determine the ECS setting value of the demultiplexer 102, a waveform generation device 161, a measurement device 162, a transmission side selection circuit 141, and a reception side selection circuit 144 are provided.

  In an inspection process for determining the ECS set value, the signal path is switched by the transmission-side selection circuit 141 according to the selection signal 140, a test waveform having a known pattern is input from the waveform generation device 161 to the multiplexer 4, and the driver 6 Output from As a result, the test serial data is transmitted to the receiving circuit 132. The received test serial data is converted by the demultiplexer 102 into parallel data. The output data 17 of the demultiplexer 102 is supplied to the measuring device 162 via a signal path different from that of the reception processing circuit 145. The measuring device 162 measures the bit error rate (BER) of the second parallel data 17d by comparing the known test serial data transmitted from the waveform generating device 161 with a predetermined expected value. The determination of the ECS set value here is performed by the measurement device 162 of the inspection device 105, and may be manually performed.

  The measurement device 162 sweeps the phase difference between the data clock 19c and the boundary clock 19d (hereinafter, referred to as “phase difference φ”) to measure the BER of the entire serdes circuit 130 at each phase difference φ. The process is executed for each of the plurality of candidate values of the setting value. The measuring device 162 selects, for example, the ECS setting value and the phase difference φ at which the BER becomes the lowest.

  FIG. 17 is a diagram illustrating an example of ECS settings. For example, as shown in FIG. 17, when the BER is measured for each candidate value of the ECS setting value, the measuring device 162 determines the ECS setting value with the lowest BER as “01”, and when the ECS setting value is “01”. Is determined as the optimum value.

  FIG. 18 is a diagram illustrating another example of the ECS setting. The inspection device 105 sweeps the power supply voltage of the serdes circuit 130 and measures the BER of the entire serdes circuit 130 at each candidate value of the ECS setting value. In FIG. 18, “P” indicates that the measured value of BER satisfies a predetermined criterion, and “F” indicates that the measured value of BER does not satisfy a predetermined criterion. As shown in FIG. 18, when the BER is measured for each candidate value of the ECS setting value, the measuring device 162 has the widest operating range among the four candidate values of the ECS setting value (that is, even if the power supply voltage is low). A candidate value whose BER measurement value satisfies a predetermined criterion is determined as the best set value (“01” in FIG. 18).

  FIG. 19 is a diagram illustrating another example of the configuration for setting the ECS, in which a serdes circuit 133 including a transmission circuit 134 and a reception circuit 135 is illustrated. In FIG. 16, the setting value of the ECS is determined externally. However, FIG. 19 shows a configuration in which the setting value is automatically determined by executing software such as firmware. In FIG. 19, the core on which the transmission-side firmware 151 is mounted and the core on which the reception-side firmware 152 is mounted (or the core on which the operating system (OS) is mounted) are switched between the waveform generator 161, the BER measurement, and the selection signal 140. , ECS settings are automatically controlled. For example, during the initial sequence when the power of the serdes circuit 133 is turned on, the optimization of the ECS setting value is performed, and after the optimization of the ECS setting value, the normal transmission / reception operation can be started.

  FIG. 20 is a flowchart illustrating an example of an inspection method for inspecting a semiconductor device. 20 will be described below with reference to FIG. 16 or FIG.

  The measuring device 162 measures the bit error rate of the second parallel data 17d with a plurality of candidate ECS setting values (measuring step S110). The measurement device 162 selects a candidate value having a bit error rate satisfying a predetermined determination criterion from a plurality of candidate values of the ECS setting value (selection step S120). The measuring device 162 stores the candidate value selected in the selection step S120 in the external register 104 (storage step S130).

  FIG. 21 is a flowchart illustrating an example of a search method for searching for the optimum ECS and phase difference φ, and illustrates a specific example of the measurement step S110 in FIG. FIG. 22 is a diagram for explaining an example of the relationship between the variables in FIG. 21, and shows an example of the BER measurement value when the phase difference φ is swept. FIG. 21 will be described below with reference to FIG.

  The measurement device 162 sets one candidate value from among a plurality of candidate values of the ECS setting value (S210). The measurement device 162 determines whether there is any PC whose BER measurement value is less than a predetermined threshold thb (an example of a first threshold) (S220). PC is a phase difference code for controlling the phase difference φ to a desired value.

  When the measurement device 162 determines that there is no PC whose BER measurement value is less than the predetermined threshold thb, the measurement device 162 increases the threshold thb by a predetermined value, and performs the determination of S220 again. When determining that there is at least one PC whose BER measurement value is less than the predetermined threshold thb, the measuring device 162 selects an arbitrary one of the at least one PC (S240).

  The measurement device 162 extracts two PCs whose BER matches a predetermined threshold thu (an example of a second threshold larger than the first threshold), acquires one PC as a minimum PC candidate value pcl, and The PC is acquired as the PC maximum candidate value pcr (S250).

  The measuring device 162 determines whether or not the PC selected in the immediately preceding S240 is an intermediate value between the minimum candidate value pcl and the maximum candidate value pcr (Step S260). When the measuring device 162 determines that the PC selected in the immediately preceding S240 is not an intermediate value between the minimum candidate value pcl and the maximum candidate value pcr, the measuring device 162 reselects another PC having a value less than the threshold thb (S240). On the other hand, when the measuring device 162 determines that the PC selected in the immediately preceding S240 is an intermediate value between the minimum candidate value pcl and the maximum candidate value pcr, it outputs a search result (S270).

  For example, in S270, the measuring device 162 outputs the PC selected in S240, the phase width pw (difference between pcr and pcl), and the threshold thb as a search result with the candidate value of the ECS set value set in S210. I do.

  According to this search method, the optimum PC, the phase width pw, and the lower limit of the BER measurement value (the lower limit of the threshold thb) can be obtained for each candidate ECS setting value. For example, the measurement device 162 can select a candidate value having the smallest lower limit value of the BER measurement value and the largest phase width pw as the optimum value from among a plurality of candidate values of the ECS setting value, and can output the candidate value as a search result ( The selection step S120 in FIG. 20).

  As described above, the semiconductor device, the demultiplexer, the semiconductor circuit, the data processing method, and the inspection method have been described with the embodiments, but the present invention is not limited to the above embodiments. Various modifications and improvements, such as combinations and replacements with some or all of the other embodiments, are possible within the scope of the present invention.

Regarding the above embodiment, the following supplementary notes are further disclosed.
(Appendix 1)
A first frequency divider for dividing the data clock and outputting a first frequency-divided data clock;
A second frequency divider circuit for dividing a boundary clock having the same frequency as the data clock but having a different phase and outputting a divided boundary clock;
A third frequency divider for dividing the first frequency-divided data clock and outputting a second frequency-divided data clock;
A first latch circuit that synchronizes serial input data synchronized with the data clock with the first frequency-divided data clock and converts the data into first parallel data;
A second latch circuit that synchronizes the first parallel data with the second frequency-divided data clock and converts the data into second parallel data;
A third latch circuit that synchronizes the serial boundary data synchronized by the boundary clock with the divided boundary clock to convert the data into first parallel boundary data;
A fourth latch circuit that synchronizes the first parallel boundary data with the second frequency-divided data clock and converts the data into second parallel boundary data;
A synchronization circuit for synchronizing the first divided data clock and the divided boundary clock;
A semiconductor device comprising: a processing unit that processes the second parallel data, the second parallel boundary data, and the second frequency-divided data clock.
(Appendix 2)
The second frequency divider divides the boundary clock and outputs a plurality of divided boundary clocks having different phases.
The synchronization circuit includes:
One differential signal in the first divided data clock, and a phase detection circuit including a plurality of phase detectors for comparing the phases of the plurality of divided boundary clocks;
The semiconductor device according to claim 1, further comprising: a multiplexer that selects one of the plurality of phase detectors.
(Appendix 3)
A memory for storing the set value of the external control signal is provided,
3. The semiconductor device according to claim 2, wherein the multiplexer selects one of the plurality of phase detectors according to a set value of the external control signal.
(Appendix 4)
The third latch circuit includes:
A first flip-flop that synchronizes with a first differential clock as a set of two clocks whose phases are different from each other by 180 ° among the plurality of divided boundary clocks;
A second flip-flop synchronized by a second differential clock, each of which is shifted by 180 ° with respect to the phase of the first differential clock;
4. The semiconductor device according to claim 2, further comprising: a second multiplexer that selects one of the output of the first flip-flop and the output of the second flip-flop according to the output of the multiplexer.
(Appendix 5)
5. The semiconductor device according to claim 2, wherein at least one of the plurality of phase detectors includes a latch to which a clock or data is input via a buffer.
(Appendix 6)
6. The semiconductor device according to claim 2, wherein at least one of the plurality of phase detectors includes a clock gating circuit capable of interrupting a clock.
(Appendix 7)
A first frequency divider for dividing the data clock and outputting a first frequency-divided data clock;
A second frequency divider circuit for dividing a boundary clock having the same frequency as the data clock but having a different phase and outputting a divided boundary clock;
A third frequency divider for dividing the first frequency-divided data clock and outputting a second frequency-divided data clock;
A first latch circuit that synchronizes serial input data synchronized with the data clock with the first frequency-divided data clock and converts the data into first parallel data;
A second latch circuit that synchronizes the first parallel data with the second frequency-divided data clock and converts the data into second parallel data;
A third latch circuit that synchronizes the serial boundary data synchronized by the boundary clock with the divided boundary clock to convert the data into first parallel boundary data;
A fourth latch circuit that synchronizes the first parallel boundary data with the second frequency-divided data clock and converts the data into second parallel boundary data;
A demultiplexer comprising: a synchronization circuit that synchronizes the first divided data clock with the divided boundary clock.
(Appendix 8)
A first frequency divider for dividing the data clock and outputting a first frequency-divided data clock;
A second frequency divider circuit for dividing a boundary clock having the same frequency as the data clock but having a different phase and outputting a divided boundary clock;
A latch circuit that synchronizes the serial boundary data synchronized by the boundary clock with the divided boundary clock and converts the data into parallel boundary data;
A semiconductor circuit comprising: a synchronization circuit that synchronizes the first divided data clock with the divided boundary clock.
(Appendix 9)
A first dividing step of dividing the data clock and outputting a divided data clock;
A second frequency dividing step of dividing the frequency of the boundary clock having the same frequency as the data clock and having a different phase, and outputting a plurality of divided boundary clocks having different phases;
A phase comparing step of comparing one differential signal in the divided data clock with the plurality of divided boundary clocks;
Whether the boundary data synchronized by the boundary clock is synchronized by a first differential clock which is two clocks of which phases are different from each other by 180 ° among the plurality of divided boundary clocks, A selecting step of selecting whether to synchronize with a second differential clock that is shifted by 180 ° with respect to the phase of the clock according to the comparison result in the phase comparing step.
(Appendix 10)
A first frequency divider for dividing the data clock and outputting a first frequency-divided data clock;
A second frequency divider circuit for dividing a boundary clock having the same frequency as the data clock but having a different phase and outputting a divided boundary clock;
A third frequency divider for dividing the first frequency-divided data clock and outputting a second frequency-divided data clock;
A first latch circuit that synchronizes serial input data synchronized with the data clock with the first frequency-divided data clock and converts the data into first parallel data;
A second latch circuit that synchronizes the first parallel data with the second frequency-divided data clock and converts the data into second parallel data;
A third latch circuit that synchronizes the serial boundary data synchronized by the boundary clock with the divided boundary clock to convert the data into first parallel boundary data;
A fourth latch circuit that synchronizes the first parallel boundary data with the second frequency-divided data clock and converts the data into second parallel boundary data;
A synchronization circuit for synchronizing the first divided data clock and the divided boundary clock;
A processing unit that processes the second parallel data, the second parallel boundary data, and the second frequency-divided data clock;
A memory for storing a set value of an external control signal,
The second frequency divider divides the boundary clock and outputs a plurality of divided boundary clocks having different phases.
The synchronization circuit includes:
One differential signal in the first divided data clock, and a phase detection circuit including a plurality of phase detectors for comparing the phases of the plurality of divided boundary clocks;
An inspection method for inspecting a semiconductor device having a multiplexer for selecting one from the plurality of phase detectors according to the set value,
A measuring step of measuring a bit error rate of the second parallel data with a plurality of candidate values of the set value;
A selecting step of selecting a candidate value whose bit error rate satisfies a predetermined criterion from among the plurality of candidate values,
Storing the candidate value selected in the selecting step as the set value in the memory.
(Appendix 11)
A first frequency divider for dividing the data clock and outputting a first frequency-divided data clock;
A second frequency divider circuit for dividing a boundary clock having the same frequency as the data clock but having a different phase and outputting a divided boundary clock;
A third frequency divider for dividing the first frequency-divided data clock and outputting a second frequency-divided data clock;
A first latch circuit that synchronizes serial input data synchronized with the data clock with the first frequency-divided data clock and converts the data into first parallel data;
A second latch circuit that synchronizes the first parallel data with the second frequency-divided data clock and converts the data into second parallel data;
A third latch circuit that synchronizes the serial boundary data synchronized by the boundary clock with the divided boundary clock to convert the data into first parallel boundary data;
A fourth latch circuit that synchronizes the first parallel boundary data with the second frequency-divided data clock and converts the data into second parallel boundary data;
A synchronization circuit for synchronizing the first divided data clock and the divided boundary clock;
A processing unit that processes the second parallel data, the second parallel boundary data, and the second frequency-divided data clock;
A search method for searching for the set value, for a semiconductor device including a memory for storing a set value of an external control signal,
The second frequency divider circuit divides the boundary clock and outputs a plurality of divided boundary clocks having different phases.
The synchronization circuit includes:
One differential signal in the first divided data clock, and a phase detection circuit including a plurality of phase detectors for comparing the phases of the plurality of divided boundary clocks;
A multiplexer for selecting one from the plurality of phase detectors according to the set value,
An increasing step of increasing the first threshold until there is a phase difference between the data clock and the boundary clock, wherein the measured value of the bit error rate of the second parallel data is less than a first threshold. ,
An obtaining step of obtaining two phase differences between the data clock and the boundary clock, wherein the measured value is equal to a predetermined second threshold larger than the first threshold;
Outputting a candidate value having the smallest first threshold value and the largest phase width between the two phase differences as a search result among the plurality of candidate values of the set value.

1 First semiconductor chip 2 Second semiconductor chip 15 Serial data 15a, 15c Input data 15b, 15d Boundary data 16 Demultiplexer 17a Parallel data 17b Parallel boundary data 17c Divided data clock 17d Second parallel data 17e Second Parallel boundary data 17f Second divided data clock 18 CDR unit 19 Clocks 19a, 19c Data clock 19b, 19d Boundary clock 19e Divided boundary clock 25 First latch circuit 26 Second latch circuit 27 First parallel data 34 Third frequency divider 35 First frequency-divided data clock 45 Fourth latch circuit 47 First parallel boundary data 48 External control signal 63, 72 Differential latch 90 Semiconductor circuit 91 First frequency divider 92 2 frequency divider circuit 93 third latch circuit 94 phase detector circuits 94a to 94d phase detector 95 multiplexer 96 fixed signal 97 first flip-flop 97a first differential clock 98 second flip-flop 98a second difference Operation clock 99 Second multiplexer 100 Synchronization circuit 101 Semiconductor device 102 Demultiplexer 103 Processing unit 104 External register 105 Inspection device 110-113 Latch 115a-115g Buffer 116 Clock gating circuit 130, 133 serdes circuit 131, 134 Transmission circuit 132 , 135 Receiving circuit 140 Selection signal 161 Waveform generation device 162 Measurement device 1000 Divider group 1001 First flip-flop group 1002 Second flip-flop group

Claims (8)

A first frequency divider for dividing the data clock and outputting a first frequency-divided data clock;
A second frequency divider circuit for dividing a boundary clock having the same frequency as the data clock but having a different phase and outputting a divided boundary clock;
A third frequency divider for dividing the first frequency-divided data clock and outputting a second frequency-divided data clock;
A first latch circuit that synchronizes serial input data synchronized with the data clock with the first frequency-divided data clock and converts the data into first parallel data;
A second latch circuit that synchronizes the first parallel data with the second frequency-divided data clock and converts the data into second parallel data;
A third latch circuit that synchronizes the serial boundary data synchronized by the boundary clock with the divided boundary clock to convert the data into first parallel boundary data;
A fourth latch circuit that synchronizes the first parallel boundary data with the second frequency-divided data clock and converts the data into second parallel boundary data;
A synchronization circuit for synchronizing the first divided data clock and the divided boundary clock;
A semiconductor device comprising: a processing unit that processes the second parallel data, the second parallel boundary data, and the second frequency-divided data clock. The second frequency divider divides the boundary clock and outputs a plurality of divided boundary clocks having different phases.
The synchronization circuit includes:
One differential signal in the first divided data clock, and a phase detection circuit including a plurality of phase detectors for comparing the phases of the plurality of divided boundary clocks;
The semiconductor device according to claim 1, further comprising: a multiplexer that selects one from the plurality of phase detectors. The third latch circuit includes:
A first flip-flop that synchronizes with a first differential clock that is a set of two clocks whose phases are different from each other by 180 ° among the plurality of divided boundary clocks;
A second flip-flop synchronized by a second differential clock that is 180 ° shifted from the phase of the first differential clock;
The semiconductor device according to claim 2, further comprising a second multiplexer that selects one of the output of the first flip-flop and the output of the second flip-flop according to the output of the multiplexer. A first frequency divider for dividing the data clock and outputting a first frequency-divided data clock;
A second frequency divider circuit for dividing a boundary clock having the same frequency as the data clock but having a different phase and outputting a divided boundary clock;
A third frequency divider for dividing the first frequency-divided data clock and outputting a second frequency-divided data clock;
A first latch circuit that synchronizes serial input data synchronized with the data clock with the first frequency-divided data clock and converts the data into first parallel data;
A second latch circuit that synchronizes the first parallel data with the second frequency-divided data clock and converts the data into second parallel data;
A third latch circuit that synchronizes the serial boundary data synchronized by the boundary clock with the divided boundary clock to convert the data into first parallel boundary data;
A fourth latch circuit that synchronizes the first parallel boundary data with the second frequency-divided data clock and converts the data into second parallel boundary data;
A demultiplexer comprising: a synchronization circuit that synchronizes the first divided data clock with the divided boundary clock. A first frequency divider for dividing the data clock and outputting a first frequency-divided data clock;
A second frequency divider circuit for dividing a boundary clock having the same frequency as the data clock but having a different phase and outputting a divided boundary clock;
A latch circuit that synchronizes the serial boundary data synchronized by the boundary clock with the divided boundary clock and converts the data into parallel boundary data;
A semiconductor circuit comprising: a synchronization circuit that synchronizes the first divided data clock with the divided boundary clock. A first dividing step of dividing the data clock and outputting a divided data clock;
A second frequency dividing step of dividing the frequency of the boundary clock having the same frequency as the data clock and having a different phase, and outputting a plurality of divided boundary clocks having different phases;
A phase comparing step of comparing one differential signal in the divided data clock with the plurality of divided boundary clocks;
Whether the serial boundary data synchronized by the boundary clock is synchronized by a first differential clock that is two clocks of which phases are different from each other by 180 ° among the plurality of divided boundary clocks, a selection step of whether to synchronize with a second differential clock shifted 180 °, respectively, selected according to the comparison result in the phase comparing step to the differential clock phase,
A latch step of synchronizing serial boundary data synchronized by the boundary clock with the differential clock selected in the selecting step and converting the data into parallel boundary data . A first frequency divider for dividing the data clock and outputting a first frequency-divided data clock;
A second frequency divider circuit for dividing a boundary clock having the same frequency as the data clock but having a different phase and outputting a divided boundary clock;
A third frequency divider for dividing the first frequency-divided data clock and outputting a second frequency-divided data clock;
A first latch circuit that synchronizes serial input data synchronized with the data clock with the first frequency-divided data clock and converts the data into first parallel data;
A second latch circuit that synchronizes the first parallel data with the second frequency-divided data clock and converts the data into second parallel data;
A third latch circuit that synchronizes the serial boundary data synchronized by the boundary clock with the divided boundary clock to convert the data into first parallel boundary data;
A fourth latch circuit that synchronizes the first parallel boundary data with the second frequency-divided data clock and converts the data into second parallel boundary data;
A synchronization circuit for synchronizing the first divided data clock and the divided boundary clock;
A processing unit that processes the second parallel data, the second parallel boundary data, and the second frequency-divided data clock;
An inspection method for inspecting a semiconductor device comprising: a memory that stores a set value of an external control signal;
The second frequency divider circuit divides the boundary clock and outputs a plurality of divided boundary clocks having different phases.
The synchronization circuit includes:
One differential signal in the first divided data clock, and a phase detection circuit including a plurality of phase detectors for comparing the phases of the plurality of divided boundary clocks;
A multiplexer for selecting one from the plurality of phase detectors according to the set value,
A measuring step of measuring a bit error rate of the second parallel data with a plurality of candidate values of the set value;
A selecting step of selecting a candidate value whose bit error rate satisfies a predetermined criterion from among the plurality of candidate values,
Storing the candidate value selected in the selecting step as the set value in the memory. A first frequency divider for dividing the data clock and outputting a first frequency-divided data clock;
A second frequency divider circuit for dividing a boundary clock having the same frequency as the data clock but having a different phase and outputting a divided boundary clock;
A third frequency divider for dividing the first frequency-divided data clock and outputting a second frequency-divided data clock;
A first latch circuit that synchronizes serial input data synchronized with the data clock with the first frequency-divided data clock and converts the data into first parallel data;
A second latch circuit that synchronizes the first parallel data with the second frequency-divided data clock and converts the data into second parallel data;
A third latch circuit that synchronizes the serial boundary data synchronized by the boundary clock with the divided boundary clock to convert the data into first parallel boundary data;
A fourth latch circuit that synchronizes the first parallel boundary data with the second frequency-divided data clock and converts the data into second parallel boundary data;
A synchronization circuit for synchronizing the first divided data clock and the divided boundary clock;
A processing unit that processes the second parallel data, the second parallel boundary data, and the second frequency-divided data clock;
A search method for searching for the set value, for a semiconductor device including a memory for storing a set value of an external control signal,
The second frequency divider circuit divides the boundary clock and outputs a plurality of divided boundary clocks having different phases.
The synchronization circuit includes:
One differential signal in the first divided data clock, and a phase detection circuit including a plurality of phase detectors for comparing the phases of the plurality of divided boundary clocks;
A multiplexer for selecting one from the plurality of phase detectors according to the set value,
An increasing step of increasing the first threshold until there is a phase difference between the data clock and the boundary clock, wherein the measured value of the bit error rate of the second parallel data is less than a first threshold. ,
An obtaining step of obtaining two phase differences between the data clock and the boundary clock, wherein the measured value is equal to a predetermined second threshold larger than the first threshold;
Outputting a candidate value having the smallest first threshold value and the largest phase width between the two phase differences as a search result among the plurality of candidate values of the set value.

Images