JPH03171945A - Digital system - Google Patents

Abstract

PURPOSE:To always execute the signal transmission between modules at an optimal timing by inputting a clock reference signal to the module for inputting a digital signal and generating optimal receiving timing information, and correction a common clock signal so as to conform with the reception of the digital signal. CONSTITUTION:A control part 11 obtains optimal timing information by a state variation of a status signal F by giving correction data 16 to a timing correcting circuit 13 through a circuit 15 in accordance with the status signal F inputted through the timing correcting circuit 13. The timing correcting circuit 13 obtains a clock signal of a form whose timing is shifted suitably against a common clock signal 3D by bringing a selector provided on its inside to selecting operation by the correction data 16, and outputs it as a receiving clock signal 3C to a flip-flop 10. In such a way, the signal transmission between modules can always be executed at an optimal timing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a digital system that transmits digital signals between modules.

(Prior Art) Generally, digital systems such as various computers and integrated circuits are composed of a plurality of modules, and have a digital transmission line for transmitting digital signals and a common line for providing a common clock signal for this transmission. They are connected by a clock signal line, and data is transmitted between each module.

When considering the operating state of this type of digital system, it is necessary to set the timing, frequency, accuracy, etc. of the receiving clock by taking into account differences in operating speed of logic elements and propagation delays due to wiring length.

However, in various digital circuits, even if the reception timing is set assuming an ideal circuit, the modules are connected by many signal lines, and the operating speeds and wiring lengths of the logic elements in each module are different. Even if one signal line operates correctly, another signal line may not operate correctly.

There are also complex issues, such as what works correctly on one system may not work correctly on another, or a system that was working correctly may no longer work properly if you replace one connected module with another. There is.

If you want to increase the operating speed of the system to its limit, you must use a measuring instrument such as an oscilloscope to find out the timing correction value and adjust the signal propagation timing according to the situation. However, this requires a lot of effort and is not possible on large systems.

Therefore, in conventional digital systems,... Operation speed and wiring length of the ethical element. A compromise has been made by determining the clock frequency within a range with sufficient margin and taking into account the variations in these values to some extent, and limiting the clock frequency to a certain value.

(Problem to be Solved by the Invention) However, in the conventional digital system as described above, the clock frequency must be determined with sufficient margin after considering the operating speed of the logic element, the wiring length, and the variations in these values. Because of this, the clock frequency could not be increased higher, which significantly limited the operating speed of the system.

Furthermore, since differences in propagation delays and operating speeds of elements are recognized as they are, there is a problem in that system reliability is reduced.

Therefore, the present invention aims to always transmit signals between modules at optimal timing using a common clock signal of a higher frequency without being affected by the operating speed of logic elements, delays caused by wiring, and variations in these values. The purpose of the present invention is to provide a digital system that can operate at high speed and improve reliability.

[Structure of the Invention] (Means for Solving the Problems) The present invention, which solves the above problems, connects a plurality of modules with digital signal transmission lines, gives a common clock signal to each module, and transmits digital signals between the modules. In a digital system configured to transmit a digital signal, the clock reference signal output means outputs a common clock signal input to the module to which the digital signal is to be output as a clock reference signal from an output terminal of a digital signal transmission line. and inputting the clock reference signal to a module that inputs the digital signal to generate optimal reception timing information, and adjusting the common clock signal to the digital signal reception module based on the generated timing information. The present invention is characterized in that a common clock signal correction means is provided for correcting the clock signal to match the clock signal.

Further, the common clock signal correction means includes means for generating a large number of clock signal groups in which the timing of the common clock signal is slightly shifted, and selecting an appropriate clock signal from the generated clock signal group. and a phase difference between the ideal reception clock signal obtained from the reference clock f3 and the actual reception clock signal output from the final stage of the selector according to the selection state of the selector. The present invention is characterized by comprising: phase detection means for outputting a phase detection signal in response to the detected phase difference; and means for creating correction data for selecting the selector so that the detected phase difference becomes zero (0). .

(Function) In the digital system of the present invention, the common clock signal input to the module that outputs the digital signal is output as a clock reference signal from the digital signal output terminal of the module that outputs the digital signal to the module that inputs the digital signal, and the digital signal is outputted as a clock reference signal. By automatically correcting the timing of the common clock signal in the module on the input side, a reception clock signal optimal for inputting a digital signal is generated.

At this time, the common clock signal is output from the module that inputs the digital signal to the module that outputs the digital signal via the actual circuit, especially the digital signal transmission line, so errors in propagation delays and operating speeds of logic elements occur. It is possible to generate a reception clock signal excluding the following.

Furthermore, in the present invention, when the common clock correction means is configured as described above, it is possible to set a receiving clock signal in which the timing of the common clock signal is appropriately shifted, for example, once in the timing setting mode. The set reception clock signal can be used in a fixed and stable manner as long as there are no changes in conditions. Further, a predetermined timing can also be set according to changes in conditions.

(Example) Examples of the present invention will be described below.

FIG. 1 is a block diagram showing the overall configuration of a digital system according to an embodiment of the present invention.

In the figure, the digital system of this example comprises two modules 2A, 2B operated by a common clock 1, both modules 2A, 2B are operated by a common clock signal 3.
a common clock signal line 4 that provides a common clock signal line 4, and a digital signal (
They are interconnected by a digital signal transmission line 6 that transmits data) 5.

In this example, module 2A is assumed to transmit data, and module 2B is assumed to receive data.

The common clock signal 3 and the transmission data 5 are input to the module 2A, and the digital signal transmission line 6 is inputted to the module 2A.
The circuit comprises a flip-flop 7 for outputting data to the circuit, and a gate 8 as a clock reference signal output means.

The gate 8 receives data 5A output from the flip-flop 7 depending on the normal mode or the timing setting mode.
Alternatively, the common clock signal 3A input to the gate is sent to the digital signal transmission line 6. In general, the mode is switched to a timing setting mode before data transmission, and then switched to a normal mode.

On the other hand, the module 2B includes a flip-flop 10 that receives data 5B input via the digital signal transmission line 6 in the normal mode using a reception clock signal 3C input from the line 9, and a timing correction circuit. It has a control section 11, a timing generation circuit 12, and a timing correction circuit 13 as means.

First, to give an overview, the control unit 11 supplies correction data to the timing correction circuit 13 via the line 15 in response to the status signal F input via the timing correction circuit 13, thereby controlling the status signal F. Optimum timing information is obtained by changing the state of . In addition, the timing generation circuit 1 inputs the common clock signal 3D,
A large number of clock signals with shifted timings are generated and sent to the timing correction circuit 13 via the line 17.
It is provided to Finally, the timing correction circuit 13
obtains a clock signal whose timing is suitably shifted from the common clock signal 3D by selectively operating a selector provided therein using the correction data 16;
This is outputted to the flip-flop 10 as a receiving clock signal 3C. Note that this circuit 13 includes:
In order to output the status signal F, a phase detector outputs a status signal F of 1 in the case of a phase lead and 0 in the case of a lag, depending on the phase difference between the reference clock signal 3B and the receiving clock signal 3C. It is included.

FIG. 2 shows details of the timing generation circuit 12, and FIG. 3 shows details of the control section 11 and timing correction circuit 13.

In FIG. 2, the timing generation circuit 12 includes P L
A frequency multiplier using an L (Phase Locked Loop) circuit and seven flip-flops 18,
It consists of a phase shift circuit with 19, 20, 21, 22, 23, and 24. The PLL circuit includes a phase comparator 25, a low-pass filter 26, voltage controlled oscillators (VCo) 27 and 1
/8 frequency divider circuit 28.

Now, set the frequency of the system common clock signal 3D to 21.
5 MHz, and the free-running oscillation frequency of the VCO is 10 QMHz. In a steady state, a 100 MHz clock signal synchronized with the common clock signal 3D is applied to each flip-flop 18 to 24 via two common signal lines. By phase-shifting the signal obtained by dividing the frequency of the 100 MHz clock by 1/8 with the 100 MHz clock, a 12.5 MHz clock signal (CKO, CKI, ...CK7) whose phase is shifted by 1 Ons is finally obtained. is,
This can be output individually from a plurality of lines 17.

In Figure 3, 30, 31.32 are data selectors, 33, 34.35 are 2.5 ns delay elements using gates, and 36, 37, 38 are 0
．． This is a 6ns delay element.

This circuit 13 allows the selector 30 to
Selector 31: 2.5ns unit, selector 32: 0.6
Phase correction of the timing signal is performed in ns units, totaling 7
By performing a phase correction of 80 ns from Ons corresponding to one cycle of the timing signal in 0.6 ns units according to the binary value of the bit, a clock signal whose phase is slightly shifted can be obtained, and the selector 30.31 Any clock signal can be selected depending on the operating state of the .32.

Further, 39 is a D-flip-flop for detecting the phase difference between the clock reference signal 3B input from the transmission line 6 and the reception clock signal 3C output from the selector 32 in the initialization mode. . 40 and 41 are D-flip-flops provided to eliminate the metastable state of the flip-flop 33.

Next, the control unit 11 shown in the figure has a correction data setting circuit 11A and a storage circuit 11B for the line 14, and the correction data setting circuit 11A checks the status signal F while checking the status signal F for the line 14. Select the selectors 30, 31, and 32 so that the phase is delayed if the status signal F is 1, and advance the phase if the status signal F is 0, and select the selector selection signal so that the phase difference between the clock reference signal 3B and the receiving clock signal 3C is O. The selector setting value when the phase difference is 0 is stored in the storage circuit 11B as correction data. That is, at this point, the reception timing information of the data sent from the module 2A is stored in the storage circuit 11B as correction data. FIG. 4 shows the control status of the correction data setting circuit 11A.

In FIG. 4, when comparing the ideal reception clock signal 3Co and the reception clock signal 3C output from the timing correction circuit 13, in this example, the status signal F
The timing error can be minimized by changing the timing error △1 to △2 at the point where the timing error changes from 1 to 0 or from O to 1. Therefore, the final error Δ2 can be reduced to 0.6 ns or less.

As described above, in the digital system of this example, the error of the receiving clock signal 3C with respect to the ideal clock signal 3CO can be reduced to 0.6 ns or less by the actions of the timing generation circuit 12, the control unit 11, and the timing correction circuit 13. can.

In addition, it is possible to set the appropriate timing prior to data transmission in response to changes in conditions, such as changes in the circuit connection state within the module, changes in the communication partner, or changes in the environment, so the optimal reception timing can always be set according to various conditions. Can be done.

Furthermore, since the memory circuit 11B is provided in this example, by setting this memory circuit 11B as a data table in which captured data is set for a plurality of conditions, optimal reception can be achieved according to changing conditions without having to measure each time. You can also set the timing.

Also, in the conventional method, there are three modules A, B, and C, and logically A and B and A and C can be combined, respectively, but because the timing design is different, even if A and B can be combined, A. ! :C could not be connected, but in this example, the signal transfer timing is automatically set between human outputs, so modules can be freely connected, and the connection state can be changed. becomes free.

In the above embodiment, the explanation was given mainly using two modules for transmitting and receiving, but the present invention is also applicable to a digital system that has a larger number of modules and transmits and receives data. In this case as well, if the correction data of the reception timing for the communication partner is stored in the storage circuit, the optimum reception timing can be quickly set according to the change in conditions, that is, the communication module.

Furthermore, in the above embodiment, the data transmission direction is shown as one direction, but by providing the transmitting and receiving sides with clock reference signal output means and common clock signal correction means,
It can handle both directions.

[Effects of the Invention] As described above, since the present invention is a digital system as described in the claims, it is not affected by the operating speed of logic elements, delays due to wiring, and variations in these values, and has a higher Signal transmission between modules can always be performed at optimal timing using a common frequency clock signal, thereby enabling high-speed operation and improving reliability.

[Brief explanation of the drawing]

Fig. 1 is an overall diagram showing a digital system according to an embodiment of the present invention, Fig. 2 is a block diagram of a timing generation circuit, Fig. 3 is a block diagram of a timing correction circuit, and Fig. 4 shows the operation of the embodiment. This is a timing chart for explanation. 1... Common clock 2A, 2B... Module 3... Common clock signal 3A... Clock reference signal 3C... Clock signal for reception 5... Digital signal (data) 6... Digital signal Transmission line 8...Gate 11...Control unit 11B...Storage circuit 12...Timing control circuit 13...Timing correction circuit 16...Correction data F...Status signal

Claims (2)

[Claims] (1) In a digital system in which a plurality of modules are connected by a digital signal transmission line, a common clock signal is given to each module, and digital signals are transmitted between the modules, the module that is to output the digital signal corresponds to A clock reference signal output means is provided for outputting a common clock signal input to the module as a clock reference signal from an output terminal of the digital signal transmission line, and the clock reference signal is input to the module to which the digital signal is input for optimal reception. 1. A digital system comprising: a common clock signal correcting means for generating timing information and correcting the common clock signal based on the generated timing information to match the reception of the digital signal. (2) In the digital system according to claim 1,
The common clock signal correction means includes means for generating a large number of clock signal groups in which the timing of the common clock signal is slightly shifted, and a means for selecting an appropriate clock signal from the generated clock signal groups. An appropriate number of stages of selectors and phase detection according to the phase difference between an ideal reception clock signal obtained from the reference clock signal according to the selection state of the selector and an actual reception clock signal output from the final stage of the selector. A digital system comprising: phase detection means for outputting a signal; and means for creating correction data for selecting the selector so that the detected phase difference becomes zero (0).