JPS5460813A - Clock phase selector circuit - Google Patents

Clock phase selector circuit

Info

Publication number
JPS5460813A
JPS5460813A JP12794977A JP12794977A JPS5460813A JP S5460813 A JPS5460813 A JP S5460813A JP 12794977 A JP12794977 A JP 12794977A JP 12794977 A JP12794977 A JP 12794977A JP S5460813 A JPS5460813 A JP S5460813A
Authority
JP
Japan
Prior art keywords
pulse
unit
pulses
clock
side unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12794977A
Other languages
Japanese (ja)
Other versions
JPS5854694B2 (en
Inventor
Kazuhiro Hiraide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP52127949A priority Critical patent/JPS5854694B2/en
Publication of JPS5460813A publication Critical patent/JPS5460813A/en
Publication of JPS5854694B2 publication Critical patent/JPS5854694B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines

Abstract

PURPOSE:To obtain the necessary pulse with no adjustment regardless of the clock frequency as well as to facilitate the IC formation, by leading out the optimum phase pulse for retiming from the clock pulse of the reception side unit. CONSTITUTION:Timing supply unit 1 supplies the clock pulses of the same frequency repetitively to transmission side unit 2 and reception side unit 3 each. Transmission circuit 5 performs the code conversion via the pulse supplied to unit 2 and transmits the signal to the intra-office transmission line. Reception circuit 6 demodulates the signal to supply it to unit 3. At unit 3, pulses 9-12 of different phases are produced via the clock pulse. And the occupation rate of each pulse is about 0.5 when the intervals between the pulses are equal to each other. In this case, each of pulses 9-12 whose phases are shifted about 90 deg. each other is ratched to the levels of 4 units of the pulse, and the level at that moment is decoded to select the optimum phase of the clock pulse.
JP52127949A 1977-10-25 1977-10-25 Clock phase selection circuit Expired JPS5854694B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52127949A JPS5854694B2 (en) 1977-10-25 1977-10-25 Clock phase selection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52127949A JPS5854694B2 (en) 1977-10-25 1977-10-25 Clock phase selection circuit

Publications (2)

Publication Number Publication Date
JPS5460813A true JPS5460813A (en) 1979-05-16
JPS5854694B2 JPS5854694B2 (en) 1983-12-06

Family

ID=14972615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52127949A Expired JPS5854694B2 (en) 1977-10-25 1977-10-25 Clock phase selection circuit

Country Status (1)

Country Link
JP (1) JPS5854694B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03171945A (en) * 1989-11-30 1991-07-25 Toshiba Corp Digital system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03171945A (en) * 1989-11-30 1991-07-25 Toshiba Corp Digital system

Also Published As

Publication number Publication date
JPS5854694B2 (en) 1983-12-06

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