JPS5773552A - In-step synchronism type receiving circuit - Google Patents
In-step synchronism type receiving circuitInfo
- Publication number
- JPS5773552A JPS5773552A JP55149302A JP14930280A JPS5773552A JP S5773552 A JPS5773552 A JP S5773552A JP 55149302 A JP55149302 A JP 55149302A JP 14930280 A JP14930280 A JP 14930280A JP S5773552 A JPS5773552 A JP S5773552A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- timer
- information bit
- bit
- produces
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE:To simplify the circuit constitution of a timer, by constituting a timer means with a circuit which produces a gate signal with a desired time width of mono-multistable multivibrator type. CONSTITUTION:A serial signal consisting of a start bit of specified clock frequency, information bit and stop bit is inputted to a timer circuit 17, which produces a gate signal with a desired time width when it receives a pulse of the start bit. While this gate signal is produced, a timing clock generating circuit 14 produces a timing clock at reception side. The timing clock is inputted to serial parallel conversion circuit 15, which converts the serial information bit among the input signals into a parallel information bit. This information bit is outputted via a buffer memory cir cuit 16. The timer circuit 17 is constituted with a circuit of mono-multistable multi vibrator type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55149302A JPS5773552A (en) | 1980-10-27 | 1980-10-27 | In-step synchronism type receiving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55149302A JPS5773552A (en) | 1980-10-27 | 1980-10-27 | In-step synchronism type receiving circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5773552A true JPS5773552A (en) | 1982-05-08 |
Family
ID=15472175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55149302A Pending JPS5773552A (en) | 1980-10-27 | 1980-10-27 | In-step synchronism type receiving circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5773552A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6074853A (en) * | 1983-09-30 | 1985-04-27 | Mitsubishi Electric Corp | Wave shaping device |
-
1980
- 1980-10-27 JP JP55149302A patent/JPS5773552A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6074853A (en) * | 1983-09-30 | 1985-04-27 | Mitsubishi Electric Corp | Wave shaping device |
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