JPS5710566A - Decoding circuit - Google Patents

Decoding circuit

Info

Publication number
JPS5710566A
JPS5710566A JP8480880A JP8480880A JPS5710566A JP S5710566 A JPS5710566 A JP S5710566A JP 8480880 A JP8480880 A JP 8480880A JP 8480880 A JP8480880 A JP 8480880A JP S5710566 A JPS5710566 A JP S5710566A
Authority
JP
Japan
Prior art keywords
given
decoding
output
latter half
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8480880A
Other languages
Japanese (ja)
Other versions
JPS6322503B2 (en
Inventor
Shigeyuki Kawarabayashi
Tadayoshi Kitayama
Yasuo Sugiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8480880A priority Critical patent/JPS5710566A/en
Publication of JPS5710566A publication Critical patent/JPS5710566A/en
Publication of JPS6322503B2 publication Critical patent/JPS6322503B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To enable decoding for the data independently of sections at the first and latter half bits of the reception series data, by differentially decoding the decoding circuit of FM code. CONSTITUTION:When a timing clock pulse (b) is given to an FF505, the pulse C from the Q output terminal is introduced from an output terminal 504 externally. Further, the Q output signal of the FF505 and the original timing clock pulse (b) are given to an AND gate 509 to output the clock pulse (d) for the selection of the latter half bit. Further, this pulse (d) is given to an FF506 to select the latter half bit of the reception series data. The signal selected at the FF506 is given to an FF507 and a signal delayed by a period T is outputted Q. Further, the Q output of the FFs 506 and 507 is in EXOR at a gate 508 and inverted at an inverter 511 for decoding.
JP8480880A 1980-06-20 1980-06-20 Decoding circuit Granted JPS5710566A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8480880A JPS5710566A (en) 1980-06-20 1980-06-20 Decoding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8480880A JPS5710566A (en) 1980-06-20 1980-06-20 Decoding circuit

Publications (2)

Publication Number Publication Date
JPS5710566A true JPS5710566A (en) 1982-01-20
JPS6322503B2 JPS6322503B2 (en) 1988-05-12

Family

ID=13841012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8480880A Granted JPS5710566A (en) 1980-06-20 1980-06-20 Decoding circuit

Country Status (1)

Country Link
JP (1) JPS5710566A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62136030A (en) * 1985-05-15 1987-06-19 ワツカ−・ケミトロニク・ゲゼルシヤフト・フユア・エレクトロニク・グルントシユトツフエ・ミツト・ベシユレンクテル・ハフツング Polishing of silicon wafer
JPH07257279A (en) * 1994-03-17 1995-10-09 Tetsuji Tsuzuki Rear-view mirror
JP2002155180A (en) * 2000-11-22 2002-05-28 Asahi Denka Kogyo Kk Vinyl chloride based resin composition for food packaging

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51138312A (en) * 1975-05-12 1976-11-29 Gen Electric Communication system
JPS5232204A (en) * 1975-09-06 1977-03-11 Fujitsu Ltd Light pcm communication system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51138312A (en) * 1975-05-12 1976-11-29 Gen Electric Communication system
JPS5232204A (en) * 1975-09-06 1977-03-11 Fujitsu Ltd Light pcm communication system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62136030A (en) * 1985-05-15 1987-06-19 ワツカ−・ケミトロニク・ゲゼルシヤフト・フユア・エレクトロニク・グルントシユトツフエ・ミツト・ベシユレンクテル・ハフツング Polishing of silicon wafer
JPH07257279A (en) * 1994-03-17 1995-10-09 Tetsuji Tsuzuki Rear-view mirror
JP2002155180A (en) * 2000-11-22 2002-05-28 Asahi Denka Kogyo Kk Vinyl chloride based resin composition for food packaging

Also Published As

Publication number Publication date
JPS6322503B2 (en) 1988-05-12

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