JPS57192127A - Logical circuit - Google Patents

Logical circuit

Info

Publication number
JPS57192127A
JPS57192127A JP56075763A JP7576381A JPS57192127A JP S57192127 A JPS57192127 A JP S57192127A JP 56075763 A JP56075763 A JP 56075763A JP 7576381 A JP7576381 A JP 7576381A JP S57192127 A JPS57192127 A JP S57192127A
Authority
JP
Japan
Prior art keywords
circuit
bit
output
constituting
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56075763A
Other languages
Japanese (ja)
Inventor
Tokuzo Fujii
Eisaku Akutsu
Yasuhiro Yakushiji
Ikuo Yoshiki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56075763A priority Critical patent/JPS57192127A/en
Publication of JPS57192127A publication Critical patent/JPS57192127A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/82—Digital/analogue converters with intermediate conversion to time interval

Abstract

PURPOSE:To simplify the entire circuit, by constituting the circuit with a counter, an NOT circuit, an NOR circuit and an AND circuit. CONSTITUTION:A clock (a) is inputted to a counter 1 and the output value n sequentially repeats 0-7. Outputs (h)-(j) are decoded with an NOT circuit 10 and an NOR circuit 12 to generate an output (k) which is 1 when the output value (n) is 1 or an output l which is at 1 when the output values are 2 and 3 through decoding with an NOT circuit 11 and an NOR circuit 13. The outputs (k), (l) and (j) represent the weight of 2<0>, 2<1> and 2<2> of each bit constituting 3-bit data, respectively. The weight signals are ANDed with bits e-g constituting parallel 3-bit input data at AND circuits 14-16 and are ORed at an NOR circuit 17, allowing to obtain a signal with a pulse width corresponding to the inputted 3-bit parallel data 3.
JP56075763A 1981-05-21 1981-05-21 Logical circuit Pending JPS57192127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56075763A JPS57192127A (en) 1981-05-21 1981-05-21 Logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56075763A JPS57192127A (en) 1981-05-21 1981-05-21 Logical circuit

Publications (1)

Publication Number Publication Date
JPS57192127A true JPS57192127A (en) 1982-11-26

Family

ID=13585579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56075763A Pending JPS57192127A (en) 1981-05-21 1981-05-21 Logical circuit

Country Status (1)

Country Link
JP (1) JPS57192127A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60171829A (en) * 1984-02-16 1985-09-05 Toshiba Corp Da converting circuit
JPH04373215A (en) * 1991-06-21 1992-12-25 Fujitsu General Ltd D/a converter

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60171829A (en) * 1984-02-16 1985-09-05 Toshiba Corp Da converting circuit
JPH0220177B2 (en) * 1984-02-16 1990-05-08 Tokyo Shibaura Electric Co
JPH04373215A (en) * 1991-06-21 1992-12-25 Fujitsu General Ltd D/a converter

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