JPS6449427A - Code converter - Google Patents

Code converter

Info

Publication number
JPS6449427A
JPS6449427A JP20671087A JP20671087A JPS6449427A JP S6449427 A JPS6449427 A JP S6449427A JP 20671087 A JP20671087 A JP 20671087A JP 20671087 A JP20671087 A JP 20671087A JP S6449427 A JPS6449427 A JP S6449427A
Authority
JP
Japan
Prior art keywords
bits
circuit
data word
code
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20671087A
Other languages
Japanese (ja)
Inventor
Akira Iketani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP20671087A priority Critical patent/JPS6449427A/en
Publication of JPS6449427A publication Critical patent/JPS6449427A/en
Pending legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To improve the docoding error rate of a data word, by performing a processing by providing a means to generate a code word of 12 bits for the input of the data word of 8 bits, and a means to select the code word. CONSTITUTION:A data word holding circuit 1 holds the data word of 8 bits sent periodically in order, and the output of the circuit 1 becomes the input of code word generation circuits 2 and 3. At the output of inversion control circuits 7 and 8, the code words CWia* and CWib* appear corresponding to the value of a back side pattern Y, and they are sent to 12 bit delay circuits 9 and 10, respectively. A selection signal generation circuit 12 generates a value S to be set at 0 when the output of the circuit 9 is selected and set at 1 when that of the circuit 10 is selected. By such constitution, it is possible to obtain a runlength limited code to satisfy the limitation of detecting window width Tw=0.667T, the minimum inversion interval Tmin=1.333T, and the maximum successive bit number K=10 by converting the data word of 8 bits to the code word of 12 bits, and to prevent the extension of an error from being generated.
JP20671087A 1987-08-20 1987-08-20 Code converter Pending JPS6449427A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20671087A JPS6449427A (en) 1987-08-20 1987-08-20 Code converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20671087A JPS6449427A (en) 1987-08-20 1987-08-20 Code converter

Publications (1)

Publication Number Publication Date
JPS6449427A true JPS6449427A (en) 1989-02-23

Family

ID=16527829

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20671087A Pending JPS6449427A (en) 1987-08-20 1987-08-20 Code converter

Country Status (1)

Country Link
JP (1) JPS6449427A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008219477A (en) * 2007-03-05 2008-09-18 Sony Corp Encoding method, encoding device, decoding method, and decoding device
WO2018004013A1 (en) * 2016-06-30 2018-01-04 Mapper Lithography Ip B.V. Method and device for generating a decoded and synchronized output

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5665313A (en) * 1979-10-29 1981-06-03 Sony Corp Data converting circuit
JPS5875950A (en) * 1981-10-31 1983-05-07 Sony Corp Encoding method for binary data
JPS5899028A (en) * 1981-12-09 1983-06-13 Hitachi Ltd Code converter
JPS60201728A (en) * 1984-03-26 1985-10-12 Canon Inc Coding system of binary data
JPS6180917A (en) * 1984-09-28 1986-04-24 Nec Corp Encoding circuit
JPS61288623A (en) * 1985-06-17 1986-12-18 Nec Corp Transmitter of synchronizing signal

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5665313A (en) * 1979-10-29 1981-06-03 Sony Corp Data converting circuit
JPS5875950A (en) * 1981-10-31 1983-05-07 Sony Corp Encoding method for binary data
JPS5899028A (en) * 1981-12-09 1983-06-13 Hitachi Ltd Code converter
JPS60201728A (en) * 1984-03-26 1985-10-12 Canon Inc Coding system of binary data
JPS6180917A (en) * 1984-09-28 1986-04-24 Nec Corp Encoding circuit
JPS61288623A (en) * 1985-06-17 1986-12-18 Nec Corp Transmitter of synchronizing signal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008219477A (en) * 2007-03-05 2008-09-18 Sony Corp Encoding method, encoding device, decoding method, and decoding device
WO2018004013A1 (en) * 2016-06-30 2018-01-04 Mapper Lithography Ip B.V. Method and device for generating a decoded and synchronized output

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