JPS645229A - 4/5 nrzi code conversion system - Google Patents

Abstract

PURPOSE:To cancel the DC component of a conversion signal while keeping a DSV integration value within a prescribed limit by selecting a conversion table and applying code conversion so that the DSV integration value after conversion is converged into zero from the data representing even/odd number of the number of inverting code included in the channel bit after the conversion and the DSV integration value before the conversion. CONSTITUTION:In fixing an end bit of a channel bit subject to code conversion before to either noninverting code or an inverting code, the conversion table A comprising the channel bit whose DSV being an index of the signal DC balance is negative and the conversion table B whose DSV is positive are prepared. After data bits (4-bit) are converted into a 9-bit data by a conversion ROM 13, the low-order 5-bit and the high-order 4-bit are fed respectively to a serial/ parallel conversion circuit 14 and a DSV integration circuit 15 respectively. A table selection circuit 18 takes an exclusive OR between the output most significant bit of the integration circuit 15 and the end bit of the channel bit subject to code conversion by a gate circuit 19, and the table A or B is selected by the ROM 13 depending on the output.