JPS56141620A - Output error compensating circuit of digital-to-analog converter - Google Patents

Output error compensating circuit of digital-to-analog converter

Info

Publication number
JPS56141620A
JPS56141620A JP4611080A JP4611080A JPS56141620A JP S56141620 A JPS56141620 A JP S56141620A JP 4611080 A JP4611080 A JP 4611080A JP 4611080 A JP4611080 A JP 4611080A JP S56141620 A JPS56141620 A JP S56141620A
Authority
JP
Japan
Prior art keywords
signal
digital
error
resistance
output error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4611080A
Other languages
Japanese (ja)
Inventor
Tomohisa Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP4611080A priority Critical patent/JPS56141620A/en
Publication of JPS56141620A publication Critical patent/JPS56141620A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To correct an output error by analogically adding or subtracting a digital signal which has been generated by the bit having an error, to an analog output. CONSTITUTION:For instance, in case when a digital signal is vibrating around ''100...0'', a signal of the most significant bit MSB is taken out through the buffer amplifier 18, and it is added to an analog signal which has been D/A-converter by the switching circuit 12 and the ladder resistance 13. The signal of MSB is voltage- divided by the resistance circuit network in accordance with magnitude of an error which is caused by the ladder resistance 13, and relation of magnitude against the standard resistance, and it is input to the operational amplifier 16 so as to be added or subtracted.
JP4611080A 1980-04-08 1980-04-08 Output error compensating circuit of digital-to-analog converter Pending JPS56141620A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4611080A JPS56141620A (en) 1980-04-08 1980-04-08 Output error compensating circuit of digital-to-analog converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4611080A JPS56141620A (en) 1980-04-08 1980-04-08 Output error compensating circuit of digital-to-analog converter

Publications (1)

Publication Number Publication Date
JPS56141620A true JPS56141620A (en) 1981-11-05

Family

ID=12737848

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4611080A Pending JPS56141620A (en) 1980-04-08 1980-04-08 Output error compensating circuit of digital-to-analog converter

Country Status (1)

Country Link
JP (1) JPS56141620A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5876241U (en) * 1981-11-17 1983-05-23 カシオ計算機株式会社 Digital-to-analog converter output error compensation circuit
JPS5954323A (en) * 1982-09-22 1984-03-29 Matsushita Electric Ind Co Ltd Digital-analog converter
JPS59125121A (en) * 1982-12-29 1984-07-19 Fujitsu Ltd Digital-analog converting circuit
JPS60213126A (en) * 1984-04-06 1985-10-25 Matsushita Electric Ind Co Ltd A/d and d/a converter
JPH0377430A (en) * 1989-08-19 1991-04-03 Fujitsu Ltd D/a converter
US5684481A (en) * 1994-03-18 1997-11-04 Analog Devices Rail-to-rail DAC drive circuit
USRE38083E1 (en) * 1994-03-18 2003-04-22 Analog Devices, Inc. Rail-to-rail DAC drive circuit
US7532140B1 (en) 2003-05-15 2009-05-12 Linear Technology Corporation Gradient insensitive split-core digital to analog converter

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5232657A (en) * 1975-09-09 1977-03-12 Fujitsu Ltd Digital-analog converter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5232657A (en) * 1975-09-09 1977-03-12 Fujitsu Ltd Digital-analog converter

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5876241U (en) * 1981-11-17 1983-05-23 カシオ計算機株式会社 Digital-to-analog converter output error compensation circuit
JPS5954323A (en) * 1982-09-22 1984-03-29 Matsushita Electric Ind Co Ltd Digital-analog converter
JPS59125121A (en) * 1982-12-29 1984-07-19 Fujitsu Ltd Digital-analog converting circuit
JPS6351609B2 (en) * 1982-12-29 1988-10-14 Fujitsu Ltd
JPS60213126A (en) * 1984-04-06 1985-10-25 Matsushita Electric Ind Co Ltd A/d and d/a converter
JPH0377430A (en) * 1989-08-19 1991-04-03 Fujitsu Ltd D/a converter
US5684481A (en) * 1994-03-18 1997-11-04 Analog Devices Rail-to-rail DAC drive circuit
USRE38083E1 (en) * 1994-03-18 2003-04-22 Analog Devices, Inc. Rail-to-rail DAC drive circuit
US7532140B1 (en) 2003-05-15 2009-05-12 Linear Technology Corporation Gradient insensitive split-core digital to analog converter

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