JPS5725721A - Digital-to-analog converter - Google Patents
Digital-to-analog converterInfo
- Publication number
- JPS5725721A JPS5725721A JP10072280A JP10072280A JPS5725721A JP S5725721 A JPS5725721 A JP S5725721A JP 10072280 A JP10072280 A JP 10072280A JP 10072280 A JP10072280 A JP 10072280A JP S5725721 A JPS5725721 A JP S5725721A
- Authority
- JP
- Japan
- Prior art keywords
- bits
- input terminal
- output
- produced
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
PURPOSE:To reduce the settling during a high bit, by using two D/A converters having a small number of bits. CONSTITUTION:When the logical signal showing the prescribed value is applied to an input terminal 11 of a D/A converting circuit 12 of n1 bits, the output signal corresponding to the input signal is produced at an output terminal 13 to be applied to the input terminal at one side of an analog adder 15. Then the logical signal showing the prescribed value is applied to the other input terminal 21 of a D/A converting circuit 22 of n1 bits, and thus the output signal corresponding to the input signal is produced at an output terminal 23. This output signal is applied to the other input terminal of the adder 15 after the attenuation carried out through an attenuator 24. The ratio of attenuation of the attenuator 24 is set at a prescribed value according to the conversion code. As a result, the output signal corresponding to a D/A converter of n1+n2 bits can be produced at an output terminal 16 of the adder 15.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10072280A JPS5725721A (en) | 1980-07-21 | 1980-07-21 | Digital-to-analog converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10072280A JPS5725721A (en) | 1980-07-21 | 1980-07-21 | Digital-to-analog converter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5725721A true JPS5725721A (en) | 1982-02-10 |
Family
ID=14281516
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10072280A Pending JPS5725721A (en) | 1980-07-21 | 1980-07-21 | Digital-to-analog converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5725721A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58152355A (en) * | 1982-03-05 | 1983-09-09 | Jeol Ltd | Lens current setting circuit |
JPS60220867A (en) * | 1984-04-17 | 1985-11-05 | Fujitsu Ltd | Voltage setting circuit |
-
1980
- 1980-07-21 JP JP10072280A patent/JPS5725721A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58152355A (en) * | 1982-03-05 | 1983-09-09 | Jeol Ltd | Lens current setting circuit |
JPH0372185B2 (en) * | 1982-03-05 | 1991-11-15 | Nippon Electron Optics Lab | |
JPS60220867A (en) * | 1984-04-17 | 1985-11-05 | Fujitsu Ltd | Voltage setting circuit |
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