JPS57168342A - Data converting circuit - Google Patents
Data converting circuitInfo
- Publication number
- JPS57168342A JPS57168342A JP5395081A JP5395081A JPS57168342A JP S57168342 A JPS57168342 A JP S57168342A JP 5395081 A JP5395081 A JP 5395081A JP 5395081 A JP5395081 A JP 5395081A JP S57168342 A JPS57168342 A JP S57168342A
- Authority
- JP
- Japan
- Prior art keywords
- bit
- output
- circuit
- bits
- significant bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/552—Powers or roots, e.g. Pythagorean sums
Abstract
PURPOSE:To obtain a squared output with a simple constitution, by defining the least significant bit of the output of the first circuit as the final least significant bit and defining the output of the K-th adding circuit as the final (K+1)th bit and adding all of the output of the (n-1)th adding circuit to upper bits. CONSTITUTION:Bits except the least significant bit out of the output of a preceding circuit are shifted to lower bits by one bit and are inputted to the k-th adding circuit of (n-1)-number of adding circuits cascaded after the first circuit 1, and n-bit original data is inputted to the k-th adding circuit also; and if the (k+1)th bit is 0, data of rest shifted bits is outputted as it is; and if the (k+1)th bit is 1, data obtained by adding both inputs is outputted. The least significant bit of the output of the first circuit 1 is defined as the final least significant bit, and the least significant bit of the output of the k-th adding circuit is defined as the final (k+1)th bit, and all bits of the output of the (n-1)th adding circuit are added to upper bits, thereby obtaining a squared output of n-bit original data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5395081A JPS57168342A (en) | 1981-04-09 | 1981-04-09 | Data converting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5395081A JPS57168342A (en) | 1981-04-09 | 1981-04-09 | Data converting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57168342A true JPS57168342A (en) | 1982-10-16 |
Family
ID=12956994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5395081A Pending JPS57168342A (en) | 1981-04-09 | 1981-04-09 | Data converting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57168342A (en) |
-
1981
- 1981-04-09 JP JP5395081A patent/JPS57168342A/en active Pending
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