JPS55147715A - Signal processing circuit - Google Patents

Signal processing circuit

Info

Publication number
JPS55147715A
JPS55147715A JP5671379A JP5671379A JPS55147715A JP S55147715 A JPS55147715 A JP S55147715A JP 5671379 A JP5671379 A JP 5671379A JP 5671379 A JP5671379 A JP 5671379A JP S55147715 A JPS55147715 A JP S55147715A
Authority
JP
Japan
Prior art keywords
output
bit
gate
upper rank
rom31
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5671379A
Other languages
Japanese (ja)
Inventor
Fumihiko Isogai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5671379A priority Critical patent/JPS55147715A/en
Publication of JPS55147715A publication Critical patent/JPS55147715A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02Digital function generators
    • G06F1/03Digital function generators working, at least partly, by table look-up
    • G06F1/035Reduction of table size
    • G06F1/0356Reduction of table size by using two or more smaller tables, e.g. addressed by parts of the argument

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE:To enable to reduce the used memory capacity or number of components used, by providing a plurality of conversion blocks depending whether the upper rank given number of the linear rate binary coded signal output is all ''0'' or not through the use of OFF-gate. CONSTITUTION:The OR gate 4 judges whether or not the upper rank given number of the output of the linear rate binary coded signal output register 1, in this case, three-bit is all zero. Further, if this upper rank 3-bit is all ''0'', the output of the gate 4 is ''0'', the output of the inverter 5 is ''1'', the operation of ROM32 is inhibited, and the bits excluding 3-bit are inputted to ROM31. If either one of the upper rank 3 bits is not ''0'', the output of the gate 4 is ''0'' to inhibit the operation of ROM31, and the bits excluding the lower rank 3-bit is inputted to ROM32. Thus, the variable block is split into a plurality, enabling to reduce the used memory capacity or number of components used.
JP5671379A 1979-05-04 1979-05-04 Signal processing circuit Pending JPS55147715A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5671379A JPS55147715A (en) 1979-05-04 1979-05-04 Signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5671379A JPS55147715A (en) 1979-05-04 1979-05-04 Signal processing circuit

Publications (1)

Publication Number Publication Date
JPS55147715A true JPS55147715A (en) 1980-11-17

Family

ID=13035113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5671379A Pending JPS55147715A (en) 1979-05-04 1979-05-04 Signal processing circuit

Country Status (1)

Country Link
JP (1) JPS55147715A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2530854A1 (en) * 1982-07-21 1984-01-27 Raytheon Co METHOD FOR EXECUTING MATHEMATICAL TREATMENT USING PERMANENT MEMORY AND ADDRESSING DEVICE FOR IMPLEMENTING SAID METHOD
JPS5927331A (en) * 1982-08-09 1984-02-13 Hitachi Ltd Function generator
EP0390055A2 (en) * 1989-03-28 1990-10-03 Konica Corporation Color image processing apparatus with digital color signal compression means

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2530854A1 (en) * 1982-07-21 1984-01-27 Raytheon Co METHOD FOR EXECUTING MATHEMATICAL TREATMENT USING PERMANENT MEMORY AND ADDRESSING DEVICE FOR IMPLEMENTING SAID METHOD
JPS5933523A (en) * 1982-07-21 1984-02-23 レイセオン カンパニ− Digital processor
JPH0418328B2 (en) * 1982-07-21 1992-03-27 Raytheon Co
JPS5927331A (en) * 1982-08-09 1984-02-13 Hitachi Ltd Function generator
JPH0241044B2 (en) * 1982-08-09 1990-09-14 Hitachi Ltd
EP0390055A2 (en) * 1989-03-28 1990-10-03 Konica Corporation Color image processing apparatus with digital color signal compression means

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