JPS5789363A - Digital demodulating system - Google Patents
Digital demodulating systemInfo
- Publication number
- JPS5789363A JPS5789363A JP16553080A JP16553080A JPS5789363A JP S5789363 A JPS5789363 A JP S5789363A JP 16553080 A JP16553080 A JP 16553080A JP 16553080 A JP16553080 A JP 16553080A JP S5789363 A JPS5789363 A JP S5789363A
- Authority
- JP
- Japan
- Prior art keywords
- code
- information
- blocks
- block
- bits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE:To reduce the capacity of a storage element, by dividing a code block into plural small blocks and by adding all code numbers corresponding to respective small blocks to decode them to an information block. CONSTITUTION:Information block groups consisting of 16 information blocks of different combinations with 4 information bits as a unit and code block groups of 16 combinations with 7 code bits as a unit correspond to each other in 1:1, and a modulation signal obtained by converting information blocks, which are obtained by dividing an information signal with 3 bits as a unit, to corresponding code blocks respectively is inputted to a terminal S of a shift register 1 and is subjected to parallel conversion to obtain a binary code of the code block in terminals Q0-Q6. These obtained output signals are divided into two small blocks and are encoded by NOR gates 2 and 3 and OR gates 4 and 5 and are all added by a 4-bit full adder 6 to decode them to an information block corresponding to the code block.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16553080A JPS5789363A (en) | 1980-11-25 | 1980-11-25 | Digital demodulating system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16553080A JPS5789363A (en) | 1980-11-25 | 1980-11-25 | Digital demodulating system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5789363A true JPS5789363A (en) | 1982-06-03 |
Family
ID=15814136
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16553080A Pending JPS5789363A (en) | 1980-11-25 | 1980-11-25 | Digital demodulating system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5789363A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102201818A (en) * | 2011-05-12 | 2011-09-28 | 中兴通讯股份有限公司 | Method and device for outputting Turbo decoding result |
-
1980
- 1980-11-25 JP JP16553080A patent/JPS5789363A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102201818A (en) * | 2011-05-12 | 2011-09-28 | 中兴通讯股份有限公司 | Method and device for outputting Turbo decoding result |
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