CN102201818A - Method and device for outputting Turbo decoding result - Google Patents
Method and device for outputting Turbo decoding result Download PDFInfo
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- CN102201818A CN102201818A CN2011101227201A CN201110122720A CN102201818A CN 102201818 A CN102201818 A CN 102201818A CN 2011101227201 A CN2011101227201 A CN 2011101227201A CN 201110122720 A CN201110122720 A CN 201110122720A CN 102201818 A CN102201818 A CN 102201818A
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- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
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Abstract
The invention provides a method and device for outputting a Turbo decoding result. The method comprises the following steps: reading the Turbo decoding result stored by taking a CB (code block) as a unit to a parallel shift register; according to the information related to the CB, selecting the tap position of the parallel shift register to carry out data registration; and controlling output of the registration result. According to the method and device, the parallel shift register and a data registration control module are utilized to process the Turbo decoding result, thus efficiently realizing the output of the Turbo decoding result with the low cost. The storage overhead is low, the processing time delay is short and the processing is simple. The processing capacity of the system is improved, thus being beneficial to reducing the cost.
Description
Technical field
The decoding treatment technology that the present invention relates to communicate by letter relates in particular to a kind of output intent and device of Turbo decode results.
Background technology
Turbo code is constructed the long code with pseudo-random characteristics with two simple component codes by the pseudo random interleaver parallel cascade dexterously, and the performance of Turbo code is considerably beyond other coded systems, is therefore more and more paid close attention to and develops.Yet, the processing more complicated of Turbo decoding, so in order to improve the throughput of Turbo decoding, field programmable gate array (the Field Programmable Gate Array that adopt in the baseband system more, FPGA) or application-specific integrated circuit (ASIC) (Application Specific Integrated Circuit ASIC) finishes Turbo decoding and handles.
According to third generation partner program (The 3rd Generation Partnership Project, 3GPP) stipulate among TS25.212 and the TS25.222, as a transmission block (Transport Block, TB) length is during greater than 5114bit, (Code Block CB) is cut apart, and the CB size after cutting apart can be the arbitrary value between 40bit～5114bit need to carry out code block to this TB, and usually at the additional dummy argument of the front end of first CB, so that the size of each CB is equal fully.Because the size of CB is the arbitrary value between 40bit～5114bit, and additional dummy argument number also has arbitrariness, so the size of the actual valid data of CB is same relatively arbitrarily.
After Turbo decoding finishes, if do not handle to obtain actual valid data, and when directly data being outputed to External memory equipment, then External memory equipment is being transferred to decode results central processing unit (Central Processing Unit, CPU) or digital signal processing chip (Digital Signal Processor, when DSP) carrying out back level processing, CPU or DSP are when using these data, just need carry out data access and handle, so can increase intractability at the bit position of actual valid data in the input data.
Here, no matter CPU still is DSP when External memory equipment reads and writes data, and all handles with least unit, specifically can be according to the difference of system and difference; Wherein, described least unit is Word, and its width w is respectively 8,16 or 32, can be designated as Word8, Word16 or Word32 respectively.In view of the foregoing, need when Turbo decoding output decode results, finish the Word splicing of CB and handle, to improve the treatment effeciency of total system.
Existing finishing in the Word splicing processing, a kind of method commonly used is that first-in first-out (First In First Out is set, FIFO), each CB decode results is write FIFO in proper order, during output, according to the size of dummy argument number and CB, order each w bit that takes out from FIFO finishes the Word splicing and handles again.But this method need be used FIFO, has increased storage overhead, realizes that cost is higher; And can only be by the bit serial process, it is bigger to handle time-delay, and efficient is lower.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of output intent and device of Turbo decode results, can realize the output of Turbo decode results low-cost, expeditiously.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of output intent of Turbo decode results, described method comprises:
To be that the Turbo decode results that unit stores reads in the parallel shift register with code block CB;
According to the relevant information of described CB, select the tap position of parallel shift register, carry out data splicing;
Control splicing result's output.
Wherein, the described Turbo decode results that will be unit stores with CB reads in the parallel shift register and is:
Read first Word of described CB, be input in the first order register of described parallel shift register; Wherein, the width w of described Word is 8,16 or 32;
Read the next Word of described CB, be input in the first order register of described parallel shift register, simultaneously, the former data parallel that is stored in the first order register is displaced in the second level register of described parallel shift register.
Wherein, described relevant information according to described CB, select the tap position of parallel shift register to be:
When described CB was first CB of Turbo decode results, the tap position of then selecting parallel shift register was the bit n～bit (w-1) of second level register of parallel shift register and the bit 0～bit (n-1) of first order register; Wherein, n is the dummy argument number of described CB;
When described CB is not first CB of Turbo decode results, then according to CB index and the CB size of described CB, obtain the also figure place m of valid data of output not of a CB, selecting the tap position of parallel shift register is bit (the w-m)～bit (w-1) of second level register and the bit0～bit (w-m-1) of first order register.
Wherein, the described data splicing that carries out is: the w bit data that obtain of splicing are followed successively by the data that the bit 0～bit (n-1) of the bit n～bit (w-1) of second level register and first order register stores from low bit to the higher bit position; Or,
The w bit data that obtain of splicing are followed successively by the data that the bit 0～bit (w-m-1) of bit (the w-m)～bit (w-1) of second level register and first order register stores from low bit to the higher bit position.
Further, described method also comprises:
Judge whether the figure place of splicing valid data in the data that obtain is w;
If the figure place of described valid data is not w, judge further then whether the CB when pre-treatment is last CB of Turbo decode results.
Wherein, described control splicing result is output as:
If when the figure place of valid data is w in the data that described splicing obtains, export described splicing result to external cache;
If the figure place of valid data is not w in the data that obtain of described splicing, and when the CB of pre-treatment is last CB,, export external cache to after gathering together enough w bit in described valid data back benefit 0 or 1;
If the figure place of valid data is not w in the data that described splicing obtains, and when the CB of pre-treatment is not last CB, the data that described splicing obtains are moved, described valid data are moved to right to low order end, and be written back into the first order register of parallel shift register, read first Word of next CB then.
A kind of output device of Turbo decode results, described device comprises: input selects module, parallel shift register, data splicing control module, output to select module; Wherein,
Module is selected in input, and the Turbo decode results that is used for CB being the unit storage reads described parallel shift register;
The data splicing control module is used for the relevant information according to described CB, selects the tap position of described parallel shift register, carries out data splicing;
Module is selected in output, is used to control splicing result's output.
Further, module is selected in described input, specifically is used to read first Word of described CB, is input in the first order register of described parallel shift register; Read the next Word of described CB, be input in the described first order register, simultaneously, the former data parallel that is stored in the described first order register is displaced in the second level register of described parallel shift register; Wherein, the width w of described Word is 8,16 or 32.
Further, described data splicing control module, specifically be used for when described CB is first CB of Turbo decode results, the tap position of then selecting parallel shift register is the bit n～bit (w-1) of second level register of parallel shift register and the bit0～bit (n-1) of first order register; Wherein, n is the dummy argument number of described CB; When described CB is not first CB of Turbo decode results, then according to CB index and the CB size of described CB, obtain the also figure place m of valid data of output not of a CB, selecting the tap position of parallel shift register is bit (the w-m)～bit (w-1) of second level register and the bit0～bit (w-m-1) of first order register.
Further, the w bit data that obtain of described data splicing control module splicing are followed successively by the data that the bit 0～bit (n-1) of the bit n～bit (w-1) of second level register and first order register stores from low bit to the higher bit position; Or be followed successively by the data of bit 0～bit (w-m-1) storage of bit (the w-m)～bit (w-1) of second level register and first order register.
Further, described data splicing control module is used for also judging whether the figure place of splicing the data valid data that obtain is w; If the figure place of described valid data is not w, judge further then whether the CB when pre-treatment is last CB of Turbo decode results.
Further, module is selected in described output, specifically is used for exporting described splicing result to external cache when if the figure place of the data valid data that described splicing obtains is w; If the figure place of valid data is not w in the data that obtain of described splicing, and when the CB of pre-treatment is last CB,, export external cache to after gathering together enough w bit in described valid data back benefit 0 or 1; If the figure place of valid data is not w in the data that described splicing obtains, and when the CB of pre-treatment is not last CB, the data that described splicing obtains are moved, described valid data are moved to right to low order end, and be written back into the first order register of parallel shift register, read first Word of next CB then.
The output intent of a kind of Turbo decode results provided by the invention and device, realize parallel processing by parallel shift register and data splicing control module to the Turbo decode results, so, can realize the output of Turbo decode results low-cost, expeditiously, have that storage overhead is low, processing delay is little and handle characteristics such as simple, and then can improve system processing power, be beneficial to the reduction of cost.
Description of drawings
Fig. 1 is the realization flow schematic diagram of the output intent of Turbo decode results of the present invention;
Fig. 2 is the schematic diagram of the external cache form of the inner buffer form of Turbo decode results in output intent one specific embodiment of Turbo decode results of the present invention and expectation;
Fig. 3 is the realization flow schematic diagram of a specific embodiment of the output intent of Turbo decode results shown in Figure 2;
Fig. 4 is input to the schematic diagram of register for first Word of first CB in the Turbo decode results shown in Figure 2;
Fig. 5 is input to the schematic diagram of register for second Word of first CB in the Turbo decode results shown in Figure 2;
Fig. 6 is input to the schematic diagram of register for last Word of first CB in the Turbo decode results shown in Figure 2;
Fig. 7 is the schematic diagram of the write-back of last Word of first CB in the Turbo decode results shown in Figure 2 register when handling;
Fig. 8 is input to the schematic diagram of register for first Word of second CB in the Turbo decode results shown in Figure 2;
Fig. 9 is for using the system configuration schematic diagram of Turbo decode results output device of the present invention;
Figure 10 is the structural representation of Turbo decode results output device of the present invention.
Embodiment
Basic thought of the present invention is: will be that the Turbo decode results that unit stores reads in the parallel shift register with code block CB; According to the relevant information of described CB, select the tap position of parallel shift register, carry out data splicing; Control splicing result's output; Wherein, the relevant information of described CB can be in the dummy argument number of described CB, CB index, the CB size one or more.
For making the purpose, technical solutions and advantages of the present invention clearer, by the following examples and with reference to accompanying drawing, the present invention is described in more detail.
Fig. 1 shows the realization flow of the output intent of Turbo decode results of the present invention, and as shown in Figure 1, described method comprises the steps:
In this step, described parallel shift register can be the parallel shift register of 8bit, 16bit, 32bit; Particularly, from the inner buffer that stores described Turbo decode results, read first Word of a CB of this Turbo decode results, be input in the first order register of this parallel shift register, and then read next Word, be input in the first order register of parallel shift register, the former data parallel that is stored in the first order register is displaced in the register of the second level; Wherein, the width w of described Word also can be 8,16 or 32, is designated as Word8, Word16 or Word32 respectively;
Particularly, in this step, can according to the dummy argument number of described CB, CB index, CB size isoparametric one or more, carry out the selection of tap position; When described CB was first CB of Turbo decode results, the tap position of then selecting parallel shift register was the bit n～bit (w-1) of second level register of parallel shift register and the bit0～bit (n-1) of first order register; Wherein, n is the dummy argument number;
When described CB is not first CB of Turbo decode results, then according to CB index and CB size, obtain the also figure place m of valid data of output not of a CB, selecting the tap position of parallel shift register is bit (the w-m)～bit (w-1) of second level register and the bit0～bit (w-m-1) of first order register; Wherein: the w bit data that obtain of splicing are followed successively by the data that the bit 0～bit (n-1) of the bit n～bit (w-1) of second level register and first order register stores from low bit to the higher bit position; Or, be followed successively by the data of bit 0～bit (w-m-1) storage of bit (the w-m)～bit (w-1) of second level register and first order register.
Particularly, when w is 8, when CB is first CB of this Turbo decode results, may need to fill dummy argument, guarantee that the length of each CB of this Turbo decode results is identical; For example, when the dummy argument number of first CB is 2, and first 8bit data of this CB have been imported when the second level register of parallel shift register, when first order register has been imported second 8bit data of this CB, the data of the front two bit storage of second level register are the dummy argument of above-mentioned filling, not the valid data of Turbo decode results, therefore, the tap position of the parallel shift register of need selecting is the tap of back six bit of second level register and the tap of first order register front two bit, and splicing obtains the data of a 8bit.
Here, the w bit data that above-mentioned splicing is obtained export external cache etc. to, repeat above-mentioned steps then, until last group data of having got a CB, because the not of uniform size of CB is the integral multiple of w surely, so also may include invalid data in last group data;
Particularly, this step also comprises: judge whether the figure place of splicing valid data in the data that obtain is w; If the figure place of described valid data is not w, judge further then whether the CB when pre-treatment is last CB of Turbo decode results;
Correspondingly, if when the figure place of valid data is w in the data that obtain of described splicing, export described splicing result to external cache;
If the figure place of valid data is not w in the data that obtain of described splicing, and when the CB of pre-treatment is last CB, can be in described valid data back benefit 0 or 1, export external cache etc. to after gathering together enough w bit;
If the figure place of valid data is not w in the data that described splicing obtains, and when the CB of pre-treatment is not last CB, the data that described splicing obtains are moved, described valid data are moved to right to low order end, and be written back into the first order register of parallel shift register, read first Word of next CB then; Particularly, be written back to first order register after, at this moment, the w bit data that step 102 splicing obtains are invalid data, give up to get final product, repeating step 101 then, read first Word of next CB.
Fig. 2 shows the inner buffer form of Turbo decode results in output intent one specific embodiment of Turbo decode results of the present invention and the external cache form of expectation, for convenience of description, the maximum length of supposing CB among the 3GPP is 64bit, and supposition is 154bit when the length of the TB of pre-treatment, suppose that it is 8 that the DSP/CPU system adopts Word width w, promptly adopts Word8.According to the CB separation algorithms, the CB that division obtains adds up to 3, the length of each CB is 52bit, the dummy argument of filling is 2bit, under these conditions, after Turbo decoding finished, the inner buffer form of three CB was shown in the arrow left side among Fig. 2, and the external cache form of this Turbo decode results expectation is shown in arrow the right among Fig. 2; Three rectangle frames among Fig. 2 shown in the arrow left side are followed successively by the hard decision result of first CB, second CB, the 3rd CB; Wherein, among the hard decision result of first CB, the dummy argument of the front two of first 8bit data for filling, last four of each CB is the invalid data of polishing; The external cache form of the expectation shown in arrow the right is removed splicing result behind the invalid data for left side CB.
Fig. 3 is the realization flow to the specific embodiment of the output intent of Turbo decode results shown in Figure 2, and in the present embodiment, the width w of Word is 8; As shown in Figure 3, described embodiment comprises the steps:
Step 301 reads first Word of first CB, deposits in the first order register of parallel shift register;
Particularly, as shown in Figure 4, first 8bit data that read first CB deposit the first order register of parallel shift register in, and at this moment, the second level register of this parallel shift register does not also deposit data in.
Step 302 reads second Word of this CB, deposits in the first order register of this parallel shift register, and at this moment, data in buffer is displaced in the register of the second level in the former first order register;
Particularly, as shown in Figure 5, read second 8bit data of first CB, be input in the first order register of parallel shift register, the former data parallel that is stored in the first order register is displaced in the register of the second level.
Particularly, with reference to Fig. 5, bit0, the dummy argument of the data in the bit1 position for filling owing to second level register so the tap position of selecting is the bit2～bit 7 of second level register and the bit0～bit 1 of first order register, carry out data splicing.
Particularly, herein, the data of splicing back output are the bit0～bit 1 of first order register from hanging down bit is followed successively by second level register to the higher bit position bit2～bit 7 then.
Particularly, the figure place of valid data is 4 among last Word of first CB, 8 of less thaies, referring to Fig. 6, when above-mentioned last Word is input in the first order register, the figure place of valid data still is 8 among the Word that this moment, splicing obtained, so execution in step 304, the 8bit data that splicing is obtained export external cache to, repeat this step then;
It should be noted that, wouldn't carry out the reading of next Word of Turbo decode results this moment, but deposit 8bit data at random in first order register, simultaneously data parallel in the former first order register is displaced to second level register, specifically can be with reference to Fig. 7, so the valid data that contain 2bit in the 8bit data that this moment, splicing obtained are execution in step 306.
Step 306 judges whether the CB when pre-treatment is last CB of Turbo decode results, if then execution in step 304, specifically can mend 0 or 1 in the valid data back of 8 of less thaies, exports external cache to after gathering together enough 8bit; If not, execution in step 307 then;
Particularly, with reference to Fig. 7, when the CB of pre-treatment is not last CB of Turbo decode results, so execution in step 307.
Particularly, referring to Fig. 7, the valid data that step 305 is spliced in the 8bit data that obtain are moved, and move to right to low order end, utilize the random data completion behind 8bit, are written back into first order register.
Step 308 reads first Word of next CB, deposits first order register in, and the 8bit data shift that contains valid data in the former first order register is in the register of the second level, and execution in step 303 then, redefine tap position, carry out data splicing;
Particularly, referring to Fig. 8, after first Word of second CB deposits first order register in, the position of bit6～bit7 remains not 2 valid data of output for first CB in the register of the second level at this moment, therefore at this moment, the tap position of determining is bit6～7 of second level register and bit0～5 of first order register, repeats above-mentioned steps then, until the Turbo decode results of the external cache form that obtains the expectation shown in Fig. 2 arrow the right.
Fig. 9 shows the system configuration signal of using Turbo decode results output device of the present invention, as shown in Figure 9, described output device can be built in the Turbo decoding processing unit of ASIC/FPGA, its internally buffer memory read the Turbo decode results, after the output device processing, export to exterior storage, offer CPU/DSP then and use.
Figure 10 shows the structural representation of Turbo decode results output device of the present invention, and as shown in figure 10, described output device comprises input selection module, parallel shift register, data splicing control module, output selection module; Wherein, module is selected in input, and the Turbo decode results that is used for CB being the unit storage reads described parallel shift register; The data splicing control module is used for the relevant information according to described CB, selects the tap position of described parallel shift register, carries out data splicing; Module is selected in output, is used to control splicing result's output.
Further, described parallel shift register comprises first order register and second level register.
Further, module is selected in described input, specifically is used to read first Word of described CB, is input in the first order register of described parallel shift register; Read the next Word of described CB, be input in the described first order register, simultaneously, the former data parallel that is stored in the described first order register is displaced in the second level register of described parallel shift register; Wherein, the width w of described Word is 8,16 or 32, is designated as Word8, Word16 or Word32 respectively.
Further, described data splicing control module, specifically be used for when described CB is first CB of Turbo decode results, the tap position of then selecting parallel shift register is the bit n～bit (w-1) of second level register of parallel shift register and the bit0～bit (n-1) of first order register; Wherein, n is the dummy argument number of described CB; When described CB is not first CB of Turbo decode results, then according to CB index and the CB size of described CB, obtain the also figure place m of valid data of output not of a CB, selecting the tap position of parallel shift register is bit (the w-m)～bit (w-1) of second level register and the bit0～bit (w-m-1) of first order register.
Wherein, the w bit data that obtain of described data splicing control module splicing are followed successively by the data that the bit0～bit (n-1) of the bit n～bit (w-1) of second level register and first order register stores from low bit to the higher bit position; Or be followed successively by the data of bit0～bit (w-m-1) storage of bit (the w-m)～bit (w-1) of second level register and first order register.
Further, described data splicing control module is used for also judging whether the figure place of splicing the data valid data that obtain is w; If the figure place of described valid data is not w, judge further then whether the CB when pre-treatment is last CB of Turbo decode results.
Further, module is selected in described output, specifically is used for exporting described splicing result to external cache when if the figure place of the data valid data that described splicing obtains is w; If the figure place of valid data is not w in the data that obtain of described splicing, and when the CB of pre-treatment is last CB,, export external cache to after gathering together enough w bit in described valid data back benefit 0 or 1; If the figure place of valid data is not w in the data that described splicing obtains, and when the CB of pre-treatment is not last CB, the data that described splicing obtains are moved, described valid data are moved to right to low order end, and be written back into the first order register of parallel shift register, read first Word of next CB then.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.
Claims (12)
1. the output intent of a Turbo decode results is characterized in that, described method comprises:
To be that the Turbo decode results that unit stores reads in the parallel shift register with code block CB;
According to the relevant information of described CB, select the tap position of parallel shift register, carry out data splicing;
Control splicing result's output.
2. method according to claim 1 is characterized in that, the described Turbo decode results that will be unit stores with CB reads in the parallel shift register and is:
Read first Word of described CB, be input in the first order register of described parallel shift register; Wherein, the width w of described Word is 8,16 or 32;
Read the next Word of described CB, be input in the first order register of described parallel shift register, simultaneously, the former data parallel that is stored in the first order register is displaced in the second level register of described parallel shift register.
3. method according to claim 1 and 2 is characterized in that, described relevant information according to described CB selects the tap position of parallel shift register to be:
When described CB was first CB of Turbo decode results, the tap position of then selecting parallel shift register was the bit n～bit (w-1) of second level register of parallel shift register and the bit 0～bit (n-1) of first order register; Wherein, n is the dummy argument number of described CB;
When described CB is not first CB of Turbo decode results, then according to CB index and the CB size of described CB, obtain the also figure place m of valid data of output not of a CB, selecting the tap position of parallel shift register is bit (the w-m)～bit (w-1) of second level register and the bit0～bit (w-m-1) of first order register.
4. method according to claim 3, it is characterized in that the described data splicing that carries out is: the w bit data that obtain of splicing are followed successively by the data that the bit 0～bit (n-1) of the bit n～bit (w-1) of second level register and first order register stores from low bit to the higher bit position; Or,
The w bit data that obtain of splicing are followed successively by the data that the bit 0～bit (w-m-1) of bit (the w-m)～bit (w-1) of second level register and first order register stores from low bit to the higher bit position.
5. method according to claim 1 is characterized in that, described method also comprises:
Judge whether the figure place of splicing valid data in the data that obtain is w;
If the figure place of described valid data is not w, judge further then whether the CB when pre-treatment is last CB of Turbo decode results.
6. method according to claim 5 is characterized in that, described control splicing result is output as:
If when the figure place of valid data is w in the data that described splicing obtains, export described splicing result to external cache;
If the figure place of valid data is not w in the data that obtain of described splicing, and when the CB of pre-treatment is last CB,, export external cache to after gathering together enough w bit in described valid data back benefit 0 or 1;
If the figure place of valid data is not w in the data that described splicing obtains, and when the CB of pre-treatment is not last CB, the data that described splicing obtains are moved, described valid data are moved to right to low order end, and be written back into the first order register of parallel shift register, read first Word of next CB then.
7. the output device of a Turbo decode results is characterized in that, described device comprises: input selects module, parallel shift register, data splicing control module, output to select module; Wherein,
Module is selected in input, and the Turbo decode results that is used for CB being the unit storage reads described parallel shift register;
The data splicing control module is used for the relevant information according to described CB, selects the tap position of described parallel shift register, carries out data splicing;
Module is selected in output, is used to control splicing result's output.
8. device according to claim 7 is characterized in that, module is selected in described input, specifically is used to read first Word of described CB, is input in the first order register of described parallel shift register; Read the next Word of described CB, be input in the described first order register, simultaneously, the former data parallel that is stored in the described first order register is displaced in the second level register of described parallel shift register; Wherein, the width w of described Word is 8,16 or 32.
9. according to claim 7 or 8 described devices, it is characterized in that, described data splicing control module, specifically be used for when described CB is first CB of Turbo decode results, the tap position of then selecting parallel shift register is the bit n～bit (w-1) of second level register of parallel shift register and the bit0～bit (n-1) of first order register; Wherein, n is the dummy argument number of described CB; When described CB is not first CB of Turbo decode results, then according to CB index and the CB size of described CB, obtain the also figure place m of valid data of output not of a CB, selecting the tap position of parallel shift register is bit (the w-m)～bit (w-1) of second level register and the bit0～bit (w-m-1) of first order register.
10. device according to claim 9, it is characterized in that the w bit data that the splicing of described data splicing control module obtains are followed successively by the data that the bit 0～bit (n-1) of the bit n～bit (w-1) of second level register and first order register stores from low bit to the higher bit position; Or be followed successively by the data of bit 0～bit (w-m-1) storage of bit (the w-m)～bit (w-1) of second level register and first order register.
11. device according to claim 7 is characterized in that, described data splicing control module is used for also judging whether the figure place of splicing the data valid data that obtain is w; If the figure place of described valid data is not w, judge further then whether the CB when pre-treatment is last CB of Turbo decode results.
12. device according to claim 7 is characterized in that, module is selected in described output, specifically is used for exporting described splicing result to external cache when if the figure place of the data valid data that described splicing obtains is w; If the figure place of valid data is not w in the data that obtain of described splicing, and when the CB of pre-treatment is last CB,, export external cache to after gathering together enough w bit in described valid data back benefit 0 or 1; If the figure place of valid data is not w in the data that described splicing obtains, and when the CB of pre-treatment is not last CB, the data that described splicing obtains are moved, described valid data are moved to right to low order end, and be written back into the first order register of parallel shift register, read first Word of next CB then.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110122720.1A CN102201818B (en) | 2011-05-12 | 2011-05-12 | A kind of output intent of Turbo decode results and device |
| PCT/CN2011/081264 WO2012151864A1 (en) | 2011-05-12 | 2011-10-25 | Outputting method and device for result of turbo coding |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012151864A1 (en) * | 2011-05-12 | 2012-11-15 | 中兴通讯股份有限公司 | Outputting method and device for result of turbo coding |
| CN103475451A (en) * | 2013-09-10 | 2013-12-25 | 江苏中科梦兰电子科技有限公司 | Datagram network transmission method suitable for forward error correction and encryption application |
| CN104702294A (en) * | 2015-03-26 | 2015-06-10 | 中国科学院自动化研究所 | Bit-width asymmetric analog memory interface of Turbo coder |
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| JPS5789363A (en) * | 1980-11-25 | 1982-06-03 | Matsushita Electric Ind Co Ltd | Digital demodulating system |
| CN101164242A (en) * | 2005-03-11 | 2008-04-16 | 高通股份有限公司 | Parallel turbo decoders with multiplexed output |
| CN101192833A (en) * | 2006-11-28 | 2008-06-04 | 华为技术有限公司 | A device and method for low-density checksum LDPC parallel coding |
| CN101957743A (en) * | 2010-10-12 | 2011-01-26 | 中国电子科技集团公司第三十八研究所 | Parallel digital signal processor |
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| US20090287980A1 (en) * | 2008-05-16 | 2009-11-19 | Lsi Corporation | Computational Architecture for Soft Decoding |
| CN102201818B (en) * | 2011-05-12 | 2015-12-16 | 中兴通讯股份有限公司 | A kind of output intent of Turbo decode results and device |
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- 2011-05-12 CN CN201110122720.1A patent/CN102201818B/en active Active
- 2011-10-25 WO PCT/CN2011/081264 patent/WO2012151864A1/en active Application Filing
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| JPS5789363A (en) * | 1980-11-25 | 1982-06-03 | Matsushita Electric Ind Co Ltd | Digital demodulating system |
| CN101164242A (en) * | 2005-03-11 | 2008-04-16 | 高通股份有限公司 | Parallel turbo decoders with multiplexed output |
| CN101192833A (en) * | 2006-11-28 | 2008-06-04 | 华为技术有限公司 | A device and method for low-density checksum LDPC parallel coding |
| CN101957743A (en) * | 2010-10-12 | 2011-01-26 | 中国电子科技集团公司第三十八研究所 | Parallel digital signal processor |
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| WO2012151864A1 (en) * | 2011-05-12 | 2012-11-15 | 中兴通讯股份有限公司 | Outputting method and device for result of turbo coding |
| CN103475451A (en) * | 2013-09-10 | 2013-12-25 | 江苏中科梦兰电子科技有限公司 | Datagram network transmission method suitable for forward error correction and encryption application |
| CN104702294A (en) * | 2015-03-26 | 2015-06-10 | 中国科学院自动化研究所 | Bit-width asymmetric analog memory interface of Turbo coder |
| CN104702294B (en) * | 2015-03-26 | 2018-04-27 | 北京思朗科技有限责任公司 | A kind of asymmetric imitate of bit wide of Turbo decoders deposits interface |
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| Publication number | Publication date |
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| CN102201818B (en) | 2015-12-16 |
| WO2012151864A1 (en) | 2012-11-15 |
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