CN102571107A - System and method for decoding high-speed parallel Turbo codes in LTE (Long Term Evolution) system - Google Patents
System and method for decoding high-speed parallel Turbo codes in LTE (Long Term Evolution) system Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3972—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using sliding window techniques or parallel windows
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
Abstract
The invention provides a decoding method for Turbo codes. The method comprises the following steps of: firstly judging whether the length K of a code block is larger than 768, if so, storing the input three paths of soft information into an input storage unit segmentally, if not, storing the three paths of soft information into a preset input storage unit, then acquiring the values of the soft information from the preset input storage unit through a preset MAP (Maximum posterior probability) unit to carry out iteration decoding calculation, wherein the values generated during the decoding calculation is stored in a preset local storage unit; continuously judging whether the eight MAP units of a Turbo code decoder are in a ready state, if so, acquiring the values of the soft information from different input storage units by each MAP unit for carrying out iteration decoding calculation, wherein the values generated during the decoding calculation are respectively stored in a plurality of local storage units; finally, determining whether reaching the maximum times of iterations or whether passing the CRC (cyclic redundancy check), if so, carrying out hard decision output on the soft information, and storing the K output results in an output storage.
Description
Technical field
The present invention relates to a kind of decode system and method, relate in particular to Long Term Evolution (Long TermEvolution, LTE) decode system and the method for the parallel Turbo code of system's high speed.
Background technology
Require descending peak rate to reach 100Mb/s in the LTE system; Up peak rate reaches 50Mb/s; This decoding speed to chnnel coding is had higher requirement, and has been applied to the Turbo decoding algorithm in the chip design at present, and great majority are to Rel 6; If LTE continues to use the Turbo code coding/decoding method among the Rel 6, can't satisfy the requirement of above-mentioned data rate.
Implementation to the Turbo code decoding accelerator of LTE system is a lot, and known common method is following:
A kind of is that the sliding window method that Turbo code decoding is commonly used is expanded to parallel method and realized that the decoder of Turbo code adopts sliding window method usually among the Rel 6, and window and window are the serial realizations, promptly goes up a window calculating and finishes and carry out the calculating of next window again.And parallel sliding window method to be a plurality of sliding windows begin to calculate simultaneously, each window is reserved the training sequence of certain-length as initial value.Aspect interleaver designs, according to the characteristics of the function that interweaves of LTE system, the function that interweaves of LTE is decomposed, the function that interweaves of LTE system is P (i)=(f
1* i+f
2* i
2) modK, wherein K is the length of decoder input bit, f
1, f
2Get different values according to the value of block length K, specifically follow the example of the table 5.1.3-3 that sees also among the LTE agreement 3GPP TS 36.212V8.5.0.Usually adopt the mode of iteration to obtain interleaving address, make the i=i+1 in the function that interweaves, obtain P (i+1)=P (i)+(f
1+ f
2+ f
22i) modK has avoided power operation.
Above-mentioned sliding window method, the number of window is at least 4, and the number of common window is 8 or 16 during enforcement; So cause the length of window to shorten; Because each window all will be reserved the training sequence of certain-length (being at least 16 bits), under window length itself was not very long situation, expense computing time that training sequence takies can not be ignored; And the length of window and the length of training sequence shorten, and decoding performance can receive very big influence.The account form of above-mentioned interleaving address though avoided power operation, is calculated interleaving address at every turn, also can reduce the speed of decoder.
Also have some researchers to propose the immediate processing method of Radix-4 and Radix-8; But because these method critical paths increase; And the system cost resource also waits magnitude to increase; In fact still increase computing unit and the memory cell through at double exchanges speed at double for, the improvement not essential to the performance of decoding accelerator.
Summary of the invention
The object of the invention is to propose a kind of decode system and method for parallel Turbo code; Use system and method provided by the invention, can use memory cell seldom, realize high-speed decoding; Satisfy the demand of LTE system high-throughput, and have good decoding performance.
For addressing the above problem, according to the decode system of a kind of Turbo code of the present invention, this system comprises:
Input store is in order to receive the soft information through coding of input;
Input controller is connected with input store, controls exporting in the Turbo code decoder to soft information input and with information of input store;
The Turbo code decoder has a plurality of maximal posterior probability algorithms and realizes unit (MAP unit), and this MAP unit takes out the soft value of information from input store and carries out iterative decoding calculating;
Local memory is used for storing the value that Turbo code decoder computational process produces;
O controller is declared the output result firmly in order to control Turbo code decoder;
Declare output storage firmly, storage Turbo code decoder is declared the output result firmly.
According to above-mentioned principal character, described system is the Turbo code decode system of 8 parallel-by-bits in a kind of LTE of the being applied to system.
According to above-mentioned principal character, described input store comprises 8 input memory cell.
According to above-mentioned principal character, described soft information is divided into three tunnel information according to system bits, first check digit 1 and second check digit 2.
According to above-mentioned principal character, described code block length was not carried out segment processing less than 768 o'clock, three tunnel information was left in the first input memory cell of input store; When code block length greater than 768 the time, three tunnel information are divided into respectively in 8 sections 8 different input memory cell that leave this input store in.
According to above-mentioned principal character, described Turbo code decoder has 8 MAP unit, after these 8 MAP are in ready (Ready) state, take out the soft value of information from 8 different input memory cell respectively and carries out iterative decoding calculating.
According to above-mentioned principal character, described each MAP unit comprises that first softly goes into the soft unit that goes out, the first external information computing unit; Interleave unit, second softly goes into the soft unit that goes out, the second external information computing unit; The deinterleaving unit; Iteration control unit and softly go into to go out firmly to declare firmly the unit, wherein said first softly goes into softly to go out the unit according to system bits, and first check digit 1 and external information are calculated log-likelihood information; The described first external information computing unit softly goes into softly to go out the log-likelihood information of unit output and the external information of input is calculated new external information according to first; Described interleave unit interweaves system bits information and new external information; Described second softly goes into softly to go out the unit and calculate the log-likelihood information according to the interweaving information and second check digit 2; The described second external information computing unit is softly gone into the soft output that goes out the unit and is calculated an external information more accurately according to second; Described deinterleaving unit external information accurately carries out deinterleaving; The external information of described iteration control unit after according to deinterleaving judges whether stop iteration; Describedly softly go into to go out firmly to declare firmly the unit and carry out hard decision output according to the external information of iterative instruction after that stop that the iteration control unit sends to deinterleaving.
According to above-mentioned principal character, described local memory has 8 LSU local store units.
According to above-mentioned principal character, described 8 MAP unit and 8 LSU local store units are not one to one, and synchronization, do not have two MAP unit can visit same LSU local store unit.
According to above-mentioned principal character, when code block length less than 768 the time, do not carry out segment processing, only use a MAP unit and first LSU local store unit.
Be to realize the method that above-mentioned purpose, the present invention provide a kind of decode system that utilizes above-mentioned Turbo code that Turbo code is decoded, wherein this method comprises the steps:
Whether judge code block length K greater than 768, i.e. step 1; In this way, then will import in the input memory cell that three tunnel soft information leave this input store in;
Continue to judge whether a plurality of MAP unit of Turbo code decoder is in the Ready state;
After a plurality of MAP unit all was in the Ready state, each MAP unit took out the soft value of information from a plurality of different input memory cell respectively and carries out iterative decoding calculating, and the value that produces in the decoding computational process is stored in respectively in a plurality of LSU local store units;
Judging whether to reach maximum iteration time or cyclic redundancy (CRC) verification passes through; Then soft information is declared output firmly in this way, K output the result be kept in the output storage, as otherwise return step 1;
K is less than or equal to 768 like code block length, and then code block does not carry out segment processing, three tunnel information is left in the predetermined input memory cell of input store, continues afterwards to judge whether the MAP unit that one of Turbo code decoder is scheduled to is in the Ready state; So predetermined MAP unit is in the Ready state, and then this MAP unit soft value of information of taking-up from predetermined input memory cell is carried out iterative decoding calculating, and the value that produces in the decoding computational process is stored in the predetermined LSU local store unit; Judge whether to reach maximum iteration time or CRC check is passed through; Then soft information is declared output firmly in this way, K output the result be kept in the output storage, as otherwise return step 1.
According to above-mentioned principal character, this Turbo code decoder has 8 MAP unit, is respectively first to the 8th MAP unit; The decode system of this Turbo code also is provided with 8 LSU local store units accordingly; Be respectively first to the 8th LSU local store unit, and input store have 8 the input memory cell, be respectively first to the 8th the input memory cell; K is less than or equal to 768 like code block length; Then three tunnel information are left in the first input memory cell of input store, follow-uply from the first input memory cell, take out the soft value of information by a MAP unit and carry out iterative decoding and calculate, the value that produces in the decoding computational process is stored in first LSU local store unit.
According to above-mentioned principal character, in step 2, the soft information of input is divided into three road d1, d2, d3, wherein the length of d1, d2, d3 is respectively K+4, and three tunnel information are divided into respectively in 8 sections 8 different input memory cell that leave this input store in.
According to above-mentioned principal character, in step 5, described each MAP unit comprises that first softly goes into the soft unit that goes out; The first external information computing unit, interleave unit, second softly goes into the soft unit that goes out; The second external information computing unit; The deinterleaving unit, iteration control unit and softly go into to go out firmly to declare firmly the unit, the inner handling process in each MAP unit comprises:
Step 1: with system bits d1
(i), check information d2
(i)And external information is input to first and softly goes into the soft unit that goes out, and calculates log-likelihood information, i=1 wherein ..., 8, represent the input of 8 different input memory cell;
Step 2: the first external information computing unit calculates new external information according to the external information of log-likelihood information and input;
Step 3: interleave unit is with system bits d1
(i), after new external information interweaves, with check information d3
(i)Be input to second together and softly go into the soft unit that goes out, calculate log-likelihood information;
Step 4: the second external information computing unit utilizes second softly to go into the soft output that goes out the unit and calculate an external information more accurately;
Step 5: the deinterleaving unit carries out deinterleaving to the external information that calculates;
Step 6: the iteration control unit carries out the CRC computing to the external information after the deinterleaving earlier, if CRC check is not passed through, judges whether to reach maximum iteration time again;
Step 7: if CRC check through or reach maximum iteration time, then carry out hard decision output decoder result, as do not reach maximum iteration time and then return step 1.
According to above-mentioned principal character, described first and second softly gone into the soft correction maximal posterior probability algorithm (Max*-Log-MAP algorithm) that goes out that the unit adopts the maximal posterior probability algorithm (Max-Log-MAP algorithm) revised and simplify add operation with Jacobi's formula.
According to above-mentioned principal character, go into softly to go out that the unit is inner to be adopted forward-facing branch tolerance α value and backward bifurcation to measure the β value to carry out the scheme to pushing away simultaneously soft; Its specific practice is softly to go into the soft end that goes out the data segment of cell processing and utilize the reverse recursion formula to calculate each β value constantly from single, calculates first symbol of this section always, and the β value that each calculates is constantly stored.Meanwhile, begin to calculate each α value constantly of this section from the beginning of data segment, until last symbol of this section, the α value in this section the moment is stored with the forward recursive formula.When decoding proceed to this section in the middle of each α value that calculates all capable of using and the β value in corresponding moment summation of multiplying each other constantly after constantly obtain corresponding likelihood and export, each moment likelihood that can obtain two bits is at this moment exported.
According to above-mentioned principal character, the initial value choosing method of described forward-facing branch tolerance α value and backward bifurcation tolerance β value is: the result that the border initial value of this iteration adopts last iteration to obtain, and the while calculates the border initial value of next iteration in this iteration; Its concrete implementation method is following:
(1) for the iteration first time; The α on border and β all are assumed to be even distribution; Wherein except the β initial value of first section α initial value and final stage, it is maximum that both of these case is the nought state probability, under the initial condition of the border of this supposition; Each MAP unit is gone into softly to go out the inner forward-facing branch tolerance α value in unit and backward bifurcation and measure the β value and carry out simultaneously the algorithm that pushes away is deciphered by soft, calculates the border initial value of next iteration simultaneously and stores;
(2) for non-iteration first; The result that the α on border and β all adopt last iteration to calculate; Wherein except the β initial value of first section α initial value and final stage, it is maximum that both of these case is the nought state probability, under this initial condition; Each MAP unit is gone into softly to go out the inner forward-facing branch tolerance α value in unit and backward bifurcation and measure the β value and carry out simultaneously the algorithm that pushes away is deciphered by soft, calculates the border initial value of next iteration simultaneously and upgrades the value of last stored.
According to above-mentioned principal character; This method utilizes same module to realize interweaving and the deinterleaving process; At first address generator is used to generate the address of reading of external information memory, and first softly goes into softly when going out each external information of unit latches, it is read the address latch simultaneously; Softly go into softly to go out after the unit calculates the external information value that makes new advances when first, the external information that this is new writes back it and reads the address; In later half iterative process, when second soft go into soft go out the unit and calculate the external information that makes new advances after, just store this external information into latch at first address once more, like this deinterleaving process of completion; And each code block, and the code block of length only carries out primary address calculating equally, is not that each iteration all will be carried out address computation.
Compared with prior art, the present invention has following advantage:
(1) the inner parallel processing mode that adopts of parallel block, promptly inner forward-facing branch tolerance α and the parallel relative calculation mode of backward bifurcation tolerance of adopting of parallel block so improved processing speed;
(2) in the de-interweaving method at every turn iteration generate interleaving address, improved processing speed;
(3) compare with common sliding window method, need not increase and push away length in advance, greatly reduced computation complexity and improved processing speed;
(4) compare with the method that pushes away in advance of common sliding window method, employing last iteration result provided by the invention has higher decoding performance as the method for initial value;
(5) when code length less than 768 the time, transfer the executive mode of serial automatically to, the requirement of processing speed has promptly been satisfied in processing like this, and performance is increased.
Description of drawings
Fig. 1 is the system architecture diagram of embodiment of the present invention.
Fig. 2 is the flow chart of embodiment of the present invention.
Fig. 3 is the composition Organization Chart of the MAP unit of embodiment of the present invention.
Fig. 4 is the details flow chart of a step shown in Figure 2.
Fig. 5 to Fig. 8 is the details flow chart of a step shown in Figure 2.
Fig. 9 is the performance comparison diagram of the sliding window method and the method provided by the invention of prior art.
Embodiment
Specify below in conjunction with the decode system and the method for accompanying drawing the parallel Turbo code of LTE system high speed of embodiment of the present invention.
See also shown in Figure 1ly, be the system architecture diagram of embodiment of the present invention, this decode system comprises:
Input store, in order to receive the soft information through coding of input, this input store comprises 8 input memory cell in the present embodiment; Be respectively first to the 8th input memory cell, this soft information comprises system bits, check digit 1 and check digit 2, stipulates according to the LTE agreement; Its length is 3*K+12, and wherein K is a code block length, and the length of d1, d2, d3 is respectively K+4; Three tunnel information are divided into respectively in 8 sections 8 different input memory cell that leave this input store in; When code block length K＜768, do not carry out segment processing, three tunnel information are left in the first input memory cell of input store;
Input controller is connected with input store, controls exporting in the Turbo code decoder to soft information input and with information of input store;
The Turbo code decoder has 8 MAP unit, is respectively first to the 8th MAP unit, after these 8 MAP are in the Ready state, take out the soft value of information from 8 different input memory cell respectively and carries out iterative decoding calculating;
Local memory has 8 LSU local store units, is used for the value that store M AP unit decodes computational process produces; Since in the existence that interweaves, 8 MAP unit and 8 LSU local store units are not one to one, just the LSU local store unit read and write of a MAP unit is not necessarily first LSU local store unit; But synchronization; Do not have two MAP unit can visit same LSU local store unit, this is the characteristics decision of the LTE interleaver that do not have contention, when code block length K less than 768 the time; Do not carry out segment processing, only use a MAP unit and first LSU local store unit;
O controller is declared the output result firmly in order to control Turbo code decoder;
Declare output storage firmly, storage Turbo code decoder is declared the output result firmly.
See also shown in Figure 2ly, the flow chart for embodiment of the present invention comprises the steps:
Step 200: judge that whether code block length K is greater than 768; In this way, then carry out step 201, be about to import three tunnel soft information d1, d2, d3 (length is respectively K+4) and be divided into respectively in 8 sections 8 different input memory cell that leave this input store in;
Step 203: continue to judge whether 8 MAP unit of Turbo code decoder are in the Ready state;
Step 204: after 8 MAP unit all were in the Ready state, each MAP unit took out the soft value of information from 8 different input memory cell respectively and carries out iterative decoding calculating, and the value that produces in the decoding computational process is stored in respectively in 8 LSU local store units;
Step 206: judge whether to reach maximum iteration time or CRC check is passed through; Then carry out step 207 in this way, soon soft information is declared output firmly, K output the result be kept in the output storage, as otherwise return step 200;
K is less than or equal to 768 like code block length; Then carry out step 202, promptly code block does not carry out segment processing, three tunnel information is left in the first input memory cell of input store; Continue afterwards to judge whether a MAP unit of Turbo code decoder is in Ready state, i.e. step 208; Carry out step 205 afterwards, promptly only from the first input memory cell, take out the soft value of information through a MAP unit and carry out iterative decoding calculating, the value that produces in the decoding computational process is stored in first LSU local store unit; Judge whether to reach maximum iteration time afterwards or CRC check is passed through; Then carry out step 209 in this way, soon soft information is declared output firmly, K output the result be kept in the output storage, as otherwise return step 200.
See also shown in Figure 3ly, be the composition Organization Chart of the MAP unit of embodiment of the present invention, the soft unit that goes out is softly gone into by first in this MAP unit; The first external information computing unit, interleave unit, second softly goes into the soft unit that goes out; The second external information computing unit, deinterleaving unit, iteration control unit; Softly go into to go out firmly to declare firmly the unit and form, wherein:
Described first softly goes into softly to go out the unit according to system bits, and first check digit 1 and external information are calculated log-likelihood information;
The described first external information computing unit softly goes into softly to go out the log-likelihood information of unit output and the external information of input is calculated new external information according to first;
Described interleave unit interweaves system bits information and new external information;
Described second softly goes into softly to go out the unit and calculate the log-likelihood information according to the interweaving information and second check digit 2;
The described second external information computing unit is softly gone into the soft output that goes out the unit and is calculated an external information more accurately according to second;
Described deinterleaving unit external information accurately carries out deinterleaving;
The external information of described iteration control unit after according to deinterleaving judges whether stop iteration;
Describedly softly go into to go out firmly to declare firmly the unit and carry out hard decision output according to the external information of iterative instruction after that stop that the iteration control unit sends to deinterleaving.
See also shown in Figure 4ly,, comprise the steps: for each MAP unit among Fig. 3 carries out the details flow chart of iterative decoding
Step 400: with system bits d1
(i), check information d2
(i)And external information is input to the first soft soft cell S ISO1 of going out of going into, and calculates log-likelihood information, i=1 wherein ..., 8, represent the input of 8 different input memory cell;
Step 401: the first external information computing unit calculates new external information according to the external information of log-likelihood information and input;
Step 402: interleave unit is with system bits d1
(i), after new external information interweaves, with check information d3
(i)Be input to the second soft soft cell S ISO2 of going out of going into together, calculate log-likelihood information;
Step 403: the second external information computing unit utilizes the output of SISO2 to calculate an external information more accurately;
Step 404: the deinterleaving unit carries out deinterleaving to the external information that calculates;
Step 405: the iteration control unit carries out CRC computing (CRC that stipulates in the LTE system) to the external information after the deinterleaving earlier, if CRC check is not passed through, judges whether to reach maximum iteration time again.
Step 406: if CRC check through or reach maximum iteration time, then carry out hard decision output decoder result, as do not reach maximum iteration time and then forward step 400 to.
See also Fig. 5 to shown in Figure 8, be the flow chart of SISO1 computational methods among Fig. 2, SISO2 is similar with the SISO1 computational methods, no longer repeated description.Adopt the maximal posterior probability algorithm (Max-Log-MAP algorithm) of the correction of using usually in the practical applications in this method; The Max-Log-MAP algorithm mainly is that forward-facing branch tolerance α and backward bifurcation tolerance β are calculated; Realize iterative decoding through state transitions; Other guide has announcement in the prior art, no longer specifies here, explains mainly how α value and β value realize parallel computation.
Go into softly to go out (SISO) inner α value and β value of adopting and carry out scheme simultaneously soft to pushing away.Specific practice is to utilize the β value in each moment of reverse recursion formula calculating from the end of the data segment of single SISO processing, calculates first symbol of this section always, and the β value that each calculates is constantly stored.Meanwhile, begin to calculate each α value constantly of this section from the beginning of data segment, until last symbol of this section, the α value in this section the moment is stored with the forward recursive formula.Said process is as shown in Figure 5.When decoding proceed to this section in the middle of constantly the time, each α value that calculates all capable of using and the β value in corresponding moment summation of multiplying each other constantly backward obtains corresponding likelihood output, each moment likelihood that can obtain two bits is at this moment exported, and is as shown in Figure 7.
In force, suppose that code length is N, degree of parallelism is P, then is equivalent to have P MAP decoder to decode simultaneously, and the code word number that each decoder need be handled is N/P.Be equivalent to original code length is divided into the P section, each section is decoded by a decoder respectively.Because P MAP decoder decoded simultaneously, so the α initial value of each segment encode and β initial value all uncertain (except first section the α initial value and the β initial value of final stage) therefore need to solve each data section boundary initial-value problem.
The present invention calculates the border initial value of next iteration simultaneously through the result that the border initial value that makes this iteration adopts last iteration to obtain in this iteration, concrete implementation method is following:
1. for the iteration first time; The α on border and β all are assumed to be even distribution (except first section the α initial value and the β initial value of final stage; It is maximum that both of these case is the nought state probability), under the initial condition of the border of this supposition, decode by Fig. 5 and single MAP unit internal algorithm shown in Figure 6 in each MAP unit; Calculate the border initial value of next iteration simultaneously and store, as shown in Figure 7.
2. for non-iteration first; The α on border and β all adopt result that last iteration calculates (except first section the α initial value and the β initial value of final stage; It is maximum that both of these case is the nought state probability), under this initial condition, decode according to Fig. 5 and single MAP unit internal algorithm shown in Figure 6 in each MAP unit; Calculate the border initial value of next iteration simultaneously and upgrade the value of last stored, as shown in Figure 8.
Accomplishing above-mentioned forward-facing branch tolerance α and backward bifurcation tolerance β calculates and exports likelihood information and just can carry out the calculating of external information.
In addition, of the present invention interweaving conciliates interleaving process and can use same module to realize, as among Fig. 3 interweave and deinterleaving can be merged into an address generator module.At first address generator is used to generate the address of reading of external information memory, when SISO1 latchs each external information, it is read the address latch simultaneously, and after SISO1 calculated the external information value that makes new advances, the external information that this is new write back it and reads the address.In later half iterative process; After the external information that SISO2 calculating makes new advances; Just store this external information into latch at first address once more, the deinterleaving process of accomplishing like this, and each code block; And the code block of length only carries out primary address calculating equally, is not that each iteration all will be carried out address computation.
When implementing, the present invention realizes that with 8 bits main memory is constructed as follows shown in the table
| Title | Number | Type | The degree of depth | The bit bit wide |
| The soft bit of system | 8×2 | Twoport | 768 | 8 |
| Check digit 1 soft bit | 8×2 | Twoport | 768 | 8 |
| Check digit 2 soft bits | 8×2 | Twoport | 768 | 8 |
| α and β | 8 | Single port | 384 | 128 |
| The soft bit of external information | 8×2 | Twoport | 768 | 9 |
| The interleaving address table | 2 | ROM | 44387/2 | 34 |
According to the standard of LTE, per second will transmit the 102K information bit, if be to calculate for 9 times according to maximum iteration time, clock frequency is 102*1000*1000*2*9/8=229.5MHZ, considers other expenses, and main clock frequency requires to be not less than 240MHZ.
Compared with prior art, the present invention has following advantage:
(1) the inner parallel processing mode that adopts of parallel block, promptly inner forward-facing branch tolerance α and the parallel relative calculation mode of backward bifurcation tolerance of adopting of parallel block so improved processing speed;
(2) in the de-interweaving method at every turn iteration generate interleaving address, improved processing speed;
(3) compare with common sliding window method, need not increase and push away length in advance, greatly reduced computation complexity and improved processing speed;
(4) compare with the method that pushes away in advance of common sliding window method, employing last iteration result provided by the invention has higher decoding performance as the method for initial value, and concrete simulation result is seen shown in Figure 9;
(5) when code length less than 768 the time, transfer the executive mode of serial automatically to, the requirement of processing speed had both been satisfied in processing like this, and performance is increased.
Claims (18)
1. the decode system of a Turbo code is characterized in that, comprising:
Input store is in order to receive the soft information through coding of input;
Input controller is connected with input store, and the control input store exports in the Turbo code decoder to soft information input and with information;
The Turbo code decoder has a plurality of MAP unit, and this MAP unit takes out the soft value of information from input store and carries out iterative decoding calculating;
Local memory is used for storing the value that Turbo code decoder computational process produces;
O controller is declared the output result firmly in order to control Turbo code decoder;
Declare output storage firmly, storage Turbo code decoder is declared the output result firmly.
2. the decode system of Turbo code according to claim 1 is characterized in that, described decode system is the Turbo code decode system of 8 parallel-by-bits in a kind of LTE of the being applied to system.
3. the decode system of Turbo code according to claim 1 is characterized in that, described input store comprises 8 input memory cell.
4. the decode system of Turbo code according to claim 1 is characterized in that, described soft information is divided into three tunnel information according to system bits, first check digit 1 and second check digit 2.
5. the decode system of Turbo code according to claim 4 is characterized in that, described code block length was not carried out segment processing less than 768 o'clock, three tunnel information is left in the first input memory cell of input store; When code block length greater than 768 the time, three tunnel information are divided into respectively in 8 sections 8 different input memory cell that leave this input store in.
6. the decode system of Turbo code according to claim 4; It is characterized in that; Described Turbo code decoder has 8 MAP unit, after these 8 MAP are in the Ready state, take out the soft value of information from 8 different input memory cell respectively and carries out iterative decoding calculating.
7. the decode system of Turbo code according to claim 6 is characterized in that, described each MAP unit comprises that first softly goes into the soft unit that goes out; The first external information computing unit, interleave unit, second softly goes into the soft unit that goes out; The second external information computing unit, deinterleaving unit, iteration control unit and softly go into to go out firmly to declare firmly the unit; Wherein
Described first softly goes into softly to go out the unit according to system bits, and first check digit 1 and external information are calculated log-likelihood information;
The described first external information computing unit softly goes into softly to go out the log-likelihood information of unit output and the external information of input is calculated new external information according to first;
Described interleave unit interweaves system bits information and new external information;
Described second softly goes into softly to go out the unit and calculate the log-likelihood information according to the interweaving information and second check digit 2;
The described second external information computing unit is softly gone into the soft output that goes out the unit and is calculated an external information more accurately according to second;
Described deinterleaving unit external information accurately carries out deinterleaving;
The external information of described iteration control unit after according to deinterleaving judges whether stop iteration;
Describedly softly go into to go out firmly to declare firmly the unit and carry out hard decision output according to the external information of iterative instruction after that stop that the iteration control unit sends to deinterleaving.
8. the decode system of Turbo code according to claim 1 is characterized in that, described local memory has 8 LSU local store units.
9. according to the decode system of claim 6 or 7 or 8 described Turbo codes; It is characterized in that; Described 8 MAP unit and 8 LSU local store units are not one to one, and synchronization, do not have two MAP unit can visit same LSU local store unit.
10. according to the decode system of claim 6 or 7 or 8 described Turbo codes, it is characterized in that, when code block length less than 768 the time, do not carry out segment processing, only use a MAP unit and first LSU local store unit.
11. the method that the decode system that utilizes the described Turbo code of claim 1 is decoded to Turbo code is characterized in that this method comprises the steps:
Whether judge code block length K greater than 768, i.e. step 1; In this way, then will import in the input memory cell that three tunnel soft information leave this input store in;
Continue to judge whether a plurality of MAP unit of Turbo code decoder is in the Ready state;
After a plurality of MAP unit all was in the Ready state, each MAP unit took out the soft value of information from a plurality of different input memory cell respectively and carries out iterative decoding calculating, and the value that produces in the decoding computational process is stored in respectively in a plurality of LSU local store units;
Judge whether to reach maximum iteration time or CRC check is passed through; Then soft information is declared output firmly in this way, K output the result be kept in the output storage, as otherwise return step 1;
K is less than or equal to 768 like code block length, and then code block does not carry out segment processing, three tunnel information is left in the predetermined input memory cell of input store, continues afterwards to judge whether the MAP unit that one of Turbo code decoder is scheduled to is in the Ready state; So predetermined MAP unit is in the Ready state, and then this MAP unit soft value of information of taking-up from predetermined input memory cell is carried out iterative decoding calculating, and the value that produces in the decoding computational process is stored in the predetermined LSU local store unit; Judge whether to reach maximum iteration time or CRC check is passed through; Then soft information is declared output firmly in this way, K output the result be kept in the output storage, as otherwise return step 1.
12. method according to claim 11; It is characterized in that this Turbo code decoder has 8 MAP unit, be respectively first to the 8th MAP unit; The decode system of this Turbo code also is provided with 8 LSU local store units accordingly; Be respectively first to the 8th LSU local store unit, and input store have 8 the input memory cell, be respectively first to the 8th the input memory cell; K is less than or equal to 768 like code block length; Then three tunnel information are left in the first input memory cell of input store, follow-uply from the first input memory cell, take out the soft value of information by a MAP unit and carry out iterative decoding and calculate, the value that produces in the decoding computational process is stored in first LSU local store unit.
13. method according to claim 12; It is characterized in that, in step 2, the soft information of importing is divided into three road d1, d2, d3; Wherein the length of d1, d2, d3 is respectively K+4, and three tunnel information are divided into respectively in 8 sections 8 different input memory cell that leave this input store in.
14. method according to claim 12 is characterized in that, in the described step 5; Described each MAP unit comprises that first softly goes into the soft unit that goes out, the first external information computing unit, interleave unit; Second softly goes into the soft unit that goes out, the second external information computing unit, deinterleaving unit; Iteration control unit and softly go into to go out firmly to declare firmly the unit, the inner handling process in each MAP unit comprises:
Step 1: with system bits d1
(i), the first check information d2
(i)And external information is input to first and softly goes into the soft unit that goes out, and calculates log-likelihood information, i=1 wherein ..., 8, represent the input of 8 different input memory cell;
Step 2: the first external information computing unit calculates new external information according to the external information of log-likelihood information and input;
Step 3: interleave unit is with system bits d1
(i), after new external information interweaves, with the second check information d3
(i)Be input to second together and softly go into the soft unit that goes out, calculate log-likelihood information;
Step 4: the second external information computing unit utilizes second softly to go into the soft output that goes out the unit and calculate an external information more accurately;
Step 5: the deinterleaving unit carries out deinterleaving to the external information that calculates;
Step 6: the iteration control unit carries out the CRC computing to the external information after the deinterleaving earlier, if CRC check is not passed through, judges whether to reach maximum iteration time again;
Step 7: if CRC check through or reach maximum iteration time, then carry out hard decision output decoder result, as do not reach maximum iteration time and then return step 1.
15. method according to claim 14 is characterized in that, described first and second softly goes into softly to go out the unit and adopt Max-Log-MAP algorithm and Max*-Log-MAP algorithm.
16. method according to claim 15 is characterized in that, goes into softly to go out that the unit is inner to be adopted forward-facing branch tolerance α value and backward bifurcation to measure the β value to carry out the scheme to pushing away simultaneously soft; Its specific practice is softly to go into the soft end that goes out the data segment of cell processing and utilize the reverse recursion formula to calculate each β value constantly from single, calculates first symbol of this section always, and the β value that each calculates is constantly stored.Meanwhile, begin to calculate each α value constantly of this section from the beginning of data segment, until last symbol of this section, the α value in this section the moment is stored with the forward recursive formula.When decoding proceed to this section in the middle of each α value that calculates all capable of using and the β value in corresponding moment summation of multiplying each other constantly after constantly obtain corresponding likelihood and export, each moment likelihood that can obtain two bits is at this moment exported.
17. method according to claim 16; It is characterized in that; The initial value choosing method of described forward-facing branch tolerance α value and backward bifurcation tolerance β value is: the result that the border initial value of this iteration adopts last iteration to obtain, and the while calculates the border initial value of next iteration in this iteration; Its concrete implementation method is following:
(1) for the iteration first time; The α on border and β all are assumed to be even distribution; Wherein except the β initial value of first section α initial value and final stage, it is maximum that both of these case is the nought state probability, under the initial condition of the border of this supposition; Each MAP unit is gone into softly to go out the inner forward-facing branch tolerance α value in unit and backward bifurcation and measure the β value and carry out simultaneously the algorithm that pushes away is deciphered by soft, calculates the border initial value of next iteration simultaneously and stores;
(2) for non-iteration first; The result that the α on border and β all adopt last iteration to calculate; Wherein except the β initial value of first section α initial value and final stage, it is maximum that both of these case is the nought state probability, under this initial condition; Each MAP unit is gone into softly to go out the inner forward-facing branch tolerance α value in unit and backward bifurcation and measure the β value and carry out simultaneously the algorithm that pushes away is deciphered by soft, calculates the border initial value of next iteration simultaneously and upgrades the value of last stored.
18. method according to claim 15; It is characterized in that this method utilizes same module to realize interweaving and the deinterleaving process, at first address generator is used to generate the address of reading of external information memory; First soft go into soft when going out each external information of unit latches; It is read the address latch simultaneously, softly go into softly to go out after the unit calculates the external information value that makes new advances when first, the external information that this is new writes back it and reads the address; In later half iterative process, when second soft go into soft go out the unit and calculate the external information that makes new advances after, just store this external information into latch at first address once more, like this deinterleaving process of completion; And each code block, and the code block of length only carries out primary address calculating equally, is not that each iteration all will be carried out address computation.
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