JPS54130111A - Coding system - Google Patents

Coding system

Info

Publication number
JPS54130111A
JPS54130111A JP3682878A JP3682878A JPS54130111A JP S54130111 A JPS54130111 A JP S54130111A JP 3682878 A JP3682878 A JP 3682878A JP 3682878 A JP3682878 A JP 3682878A JP S54130111 A JPS54130111 A JP S54130111A
Authority
JP
Japan
Prior art keywords
bits
codes
signal
gates
converted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3682878A
Other languages
Japanese (ja)
Inventor
Mitsuo Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3682878A priority Critical patent/JPS54130111A/en
Publication of JPS54130111A publication Critical patent/JPS54130111A/en
Pending legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE: To achieve the improvement in recording density with simple circuit constitution by converting the binary signal of 2 bits to 4 bit codes of the specified type.
CONSTITUTION: When the binary signal of 2 bits is applied to a shift register 1 operating synchronously with the clock of a clock generator 4, the signal wherein 2 bits are 1 set is converted to the 4-bit signal of assigned codes X, Y based on the chart by a 4-bit register 5 via AND gates 11, 10, AND gates 8, 6, etc. connecting to inverters 9, 7. This converted signal is changed according to the bits of the codes X, Y by the gates 11, 13 and the input signals 00 to 11 to the shift register 2 are converted to the codes which are of the same characteristics as those of the 3PM coded signals of 4 bits of 1000, 0001, 0010, 0100 respectively and whose recording density may be increased.
COPYRIGHT: (C)1979,JPO&Japio
JP3682878A 1978-03-31 1978-03-31 Coding system Pending JPS54130111A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3682878A JPS54130111A (en) 1978-03-31 1978-03-31 Coding system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3682878A JPS54130111A (en) 1978-03-31 1978-03-31 Coding system

Publications (1)

Publication Number Publication Date
JPS54130111A true JPS54130111A (en) 1979-10-09

Family

ID=12480597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3682878A Pending JPS54130111A (en) 1978-03-31 1978-03-31 Coding system

Country Status (1)

Country Link
JP (1) JPS54130111A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0059224A1 (en) * 1980-09-05 1982-09-08 Mitsubishi Denki Kabushiki Kaisha System for coding and decoding binary data
EP0110625A2 (en) * 1982-11-24 1984-06-13 Storage Technology Corporation Circuit for encoding data pulses

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0059224A1 (en) * 1980-09-05 1982-09-08 Mitsubishi Denki Kabushiki Kaisha System for coding and decoding binary data
EP0110625A2 (en) * 1982-11-24 1984-06-13 Storage Technology Corporation Circuit for encoding data pulses

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