JPS55150042A - Code converter - Google Patents

Code converter

Info

Publication number
JPS55150042A
JPS55150042A JP5728079A JP5728079A JPS55150042A JP S55150042 A JPS55150042 A JP S55150042A JP 5728079 A JP5728079 A JP 5728079A JP 5728079 A JP5728079 A JP 5728079A JP S55150042 A JPS55150042 A JP S55150042A
Authority
JP
Japan
Prior art keywords
data
bits
signal
bit
binary coded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5728079A
Other languages
Japanese (ja)
Inventor
Masahiro Noguchi
Itaru Kawasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP5728079A priority Critical patent/JPS55150042A/en
Publication of JPS55150042A publication Critical patent/JPS55150042A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To convert the n-bit fixed binary coded number data into the floating binary coded number data of m+l bits, by using the signal of the higher-rank m bit of the shift register circuit for the data of the mantissa part and the signal of l bits of the counter circuit for the data of the exponent part each.
CONSTITUTION: The output signal of the higher-rank m bits of shift register circuit 2 on n bit in which the stored data is shifted toward the higher-rank bit by the stored clock signal is used for the data of the mantssa part. On the other hand, the output signal of l bits of counter circuit 3 which receives the down-counting by the data input strobe signal is used for the data of the exponent part. And the output signal of delay circuit 5 which gives the delay of the necessary time to the data input strobe signal is delivered in the form of data strobe signal. As a result, the code converter can be obtained to convert the fixed binary coded number data of n bits into the floating binary coded number data of m+l bits.
COPYRIGHT: (C)1980,JPO&Japio
JP5728079A 1979-05-10 1979-05-10 Code converter Pending JPS55150042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5728079A JPS55150042A (en) 1979-05-10 1979-05-10 Code converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5728079A JPS55150042A (en) 1979-05-10 1979-05-10 Code converter

Publications (1)

Publication Number Publication Date
JPS55150042A true JPS55150042A (en) 1980-11-21

Family

ID=13051115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5728079A Pending JPS55150042A (en) 1979-05-10 1979-05-10 Code converter

Country Status (1)

Country Link
JP (1) JPS55150042A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5924342A (en) * 1982-07-30 1984-02-08 Hitachi Ltd Arithmetic device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5924342A (en) * 1982-07-30 1984-02-08 Hitachi Ltd Arithmetic device
JPH0425577B2 (en) * 1982-07-30 1992-05-01 Hitachi Ltd

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