JPS55159248A - Operating system - Google Patents

Operating system

Info

Publication number
JPS55159248A
JPS55159248A JP6587579A JP6587579A JPS55159248A JP S55159248 A JPS55159248 A JP S55159248A JP 6587579 A JP6587579 A JP 6587579A JP 6587579 A JP6587579 A JP 6587579A JP S55159248 A JPS55159248 A JP S55159248A
Authority
JP
Japan
Prior art keywords
decimal point
data
output
floating
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6587579A
Other languages
Japanese (ja)
Inventor
Isao Fukushima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6587579A priority Critical patent/JPS55159248A/en
Publication of JPS55159248A publication Critical patent/JPS55159248A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To speed up the operating processing, by sequentially converting the floating decimal point data to the fixed decimal point data, in the output of a pipeline type operating circuit.
CONSTITUTION: The input data is a fixed decimal point data. The data is operated by converting it into the floating decimal point to prevent the overflow in the operating processing circuit. The output after operation is converted again and returned to the fixed decimal point. To convert the data, the position of the decimal point of the floating decimal point is shifted. The reference value of the shift is set in the latch circuit. The result is output by 2 clocks in the operating circuit. That is, after the end of the operation by floating decimal point, shift is made according to the number of shifts in the latch circuit to output the data of fixed decimal point.
COPYRIGHT: (C)1980,JPO&Japio
JP6587579A 1979-05-28 1979-05-28 Operating system Pending JPS55159248A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6587579A JPS55159248A (en) 1979-05-28 1979-05-28 Operating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6587579A JPS55159248A (en) 1979-05-28 1979-05-28 Operating system

Publications (1)

Publication Number Publication Date
JPS55159248A true JPS55159248A (en) 1980-12-11

Family

ID=13299579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6587579A Pending JPS55159248A (en) 1979-05-28 1979-05-28 Operating system

Country Status (1)

Country Link
JP (1) JPS55159248A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6126135A (en) * 1984-07-16 1986-02-05 Nec Corp Conversion circuit of floating point data
JP2004213622A (en) * 2002-12-27 2004-07-29 Arm Ltd Data processing device and method converting number between fixed point display and floating point display

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6126135A (en) * 1984-07-16 1986-02-05 Nec Corp Conversion circuit of floating point data
JP2004213622A (en) * 2002-12-27 2004-07-29 Arm Ltd Data processing device and method converting number between fixed point display and floating point display
JP2009093662A (en) * 2002-12-27 2009-04-30 Arm Ltd Data processing apparatus and method for converting number between fixed-point and floating-point representations

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