JPS5533204A - Digital control system - Google Patents

Digital control system

Info

Publication number
JPS5533204A
JPS5533204A JP10496278A JP10496278A JPS5533204A JP S5533204 A JPS5533204 A JP S5533204A JP 10496278 A JP10496278 A JP 10496278A JP 10496278 A JP10496278 A JP 10496278A JP S5533204 A JPS5533204 A JP S5533204A
Authority
JP
Japan
Prior art keywords
signal
bits
digital
output
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10496278A
Other languages
Japanese (ja)
Inventor
Kenji Koro
Motomi Sugano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP10496278A priority Critical patent/JPS5533204A/en
Publication of JPS5533204A publication Critical patent/JPS5533204A/en
Pending legal-status Critical Current

Links

Landscapes

  • Picture Signal Circuits (AREA)
  • Feedback Control In General (AREA)

Abstract

PURPOSE: To make it possible to obtain a control signal output of more bits without reference to the number of bits of an input signal by obtaining a controlled variable by adding or subtracting, one by one, corresponding to a digital signal shifted by a fixed value and a control variable one cycle before.
CONSTITUTION: A digital input signal, after being stored temporarily in RAM9, is transferred by a clock signal to shift register 10, where it is delayed by one colck signal, and the output of shift register 10 is transferred to comparator 13, where it is compared with a no-delay signal applied direct from RAM. According to the comparison result, a signal of "1", "0" or "-1" applied to operator 11 is added to a one-cycle preceding controlled variable read out from RAM15, thereby extracting a digital control signal from output terminal 12. Consequently, the number of bits of the control signal can be increased without reference to the number of bits of the A/D converter.
COPYRIGHT: (C)1980,JPO&Japio
JP10496278A 1978-08-30 1978-08-30 Digital control system Pending JPS5533204A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10496278A JPS5533204A (en) 1978-08-30 1978-08-30 Digital control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10496278A JPS5533204A (en) 1978-08-30 1978-08-30 Digital control system

Publications (1)

Publication Number Publication Date
JPS5533204A true JPS5533204A (en) 1980-03-08

Family

ID=14394716

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10496278A Pending JPS5533204A (en) 1978-08-30 1978-08-30 Digital control system

Country Status (1)

Country Link
JP (1) JPS5533204A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58104576A (en) * 1981-12-16 1983-06-22 Matsushita Electric Ind Co Ltd Ghost eliminating device
JPS58104577A (en) * 1981-12-16 1983-06-22 Matsushita Electric Ind Co Ltd Ghost eliminating device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58104576A (en) * 1981-12-16 1983-06-22 Matsushita Electric Ind Co Ltd Ghost eliminating device
JPS58104577A (en) * 1981-12-16 1983-06-22 Matsushita Electric Ind Co Ltd Ghost eliminating device
JPH0259669B2 (en) * 1981-12-16 1990-12-13 Matsushita Electric Ind Co Ltd

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